net: add opencore 10/100 ethernet mac driver
This patch ports the opencore 10/100 ethernet mac driver ethoc.c from linux kernel to u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Thomas Chou
Ben Warren
parent
bd75db3feb
commit
f6569884b4
@ -39,6 +39,7 @@ COBJS-$(CONFIG_E1000) += e1000.o
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COBJS-$(CONFIG_EEPRO100) += eepro100.o
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COBJS-$(CONFIG_ENC28J60) += enc28j60.o
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COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
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COBJS-$(CONFIG_ETHOC) += ethoc.o
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COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
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COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
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COBJS-$(CONFIG_FTMAC100) += ftmac100.o
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511
drivers/net/ethoc.c
Normal file
511
drivers/net/ethoc.c
Normal file
@ -0,0 +1,511 @@
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/*
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* Opencore 10/100 ethernet mac driver
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*
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* Copyright (C) 2007-2008 Avionic Design Development GmbH
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* Copyright (C) 2008-2009 Avionic Design GmbH
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* Thierry Reding <thierry.reding@avionic-design.de>
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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/* register offsets */
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#define MODER 0x00
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#define INT_SOURCE 0x04
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#define INT_MASK 0x08
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#define IPGT 0x0c
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#define IPGR1 0x10
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#define IPGR2 0x14
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#define PACKETLEN 0x18
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#define COLLCONF 0x1c
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#define TX_BD_NUM 0x20
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#define CTRLMODER 0x24
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#define MIIMODER 0x28
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#define MIICOMMAND 0x2c
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#define MIIADDRESS 0x30
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#define MIITX_DATA 0x34
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#define MIIRX_DATA 0x38
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#define MIISTATUS 0x3c
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#define MAC_ADDR0 0x40
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#define MAC_ADDR1 0x44
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#define ETH_HASH0 0x48
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#define ETH_HASH1 0x4c
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#define ETH_TXCTRL 0x50
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/* mode register */
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#define MODER_RXEN (1 << 0) /* receive enable */
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#define MODER_TXEN (1 << 1) /* transmit enable */
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#define MODER_NOPRE (1 << 2) /* no preamble */
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#define MODER_BRO (1 << 3) /* broadcast address */
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#define MODER_IAM (1 << 4) /* individual address mode */
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#define MODER_PRO (1 << 5) /* promiscuous mode */
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#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
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#define MODER_LOOP (1 << 7) /* loopback */
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#define MODER_NBO (1 << 8) /* no back-off */
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#define MODER_EDE (1 << 9) /* excess defer enable */
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#define MODER_FULLD (1 << 10) /* full duplex */
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#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
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#define MODER_DCRC (1 << 12) /* delayed CRC enable */
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#define MODER_CRC (1 << 13) /* CRC enable */
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#define MODER_HUGE (1 << 14) /* huge packets enable */
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#define MODER_PAD (1 << 15) /* padding enabled */
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#define MODER_RSM (1 << 16) /* receive small packets */
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/* interrupt source and mask registers */
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#define INT_MASK_TXF (1 << 0) /* transmit frame */
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#define INT_MASK_TXE (1 << 1) /* transmit error */
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#define INT_MASK_RXF (1 << 2) /* receive frame */
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#define INT_MASK_RXE (1 << 3) /* receive error */
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#define INT_MASK_BUSY (1 << 4)
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#define INT_MASK_TXC (1 << 5) /* transmit control frame */
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#define INT_MASK_RXC (1 << 6) /* receive control frame */
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#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
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#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
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#define INT_MASK_ALL ( \
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INT_MASK_TXF | INT_MASK_TXE | \
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INT_MASK_RXF | INT_MASK_RXE | \
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INT_MASK_TXC | INT_MASK_RXC | \
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INT_MASK_BUSY \
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)
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/* packet length register */
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#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
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#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
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#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
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PACKETLEN_MAX(max))
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/* transmit buffer number register */
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#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
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/* control module mode register */
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#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
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#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
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#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
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/* MII mode register */
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#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
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#define MIIMODER_NOPRE (1 << 8) /* no preamble */
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/* MII command register */
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#define MIICOMMAND_SCAN (1 << 0) /* scan status */
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#define MIICOMMAND_READ (1 << 1) /* read status */
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#define MIICOMMAND_WRITE (1 << 2) /* write control data */
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/* MII address register */
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#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
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#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
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#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
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MIIADDRESS_RGAD(reg))
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/* MII transmit data register */
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#define MIITX_DATA_VAL(x) ((x) & 0xffff)
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/* MII receive data register */
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#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
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/* MII status register */
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#define MIISTATUS_LINKFAIL (1 << 0)
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#define MIISTATUS_BUSY (1 << 1)
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#define MIISTATUS_INVALID (1 << 2)
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/* TX buffer descriptor */
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#define TX_BD_CS (1 << 0) /* carrier sense lost */
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#define TX_BD_DF (1 << 1) /* defer indication */
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#define TX_BD_LC (1 << 2) /* late collision */
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#define TX_BD_RL (1 << 3) /* retransmission limit */
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#define TX_BD_RETRY_MASK (0x00f0)
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#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
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#define TX_BD_UR (1 << 8) /* transmitter underrun */
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#define TX_BD_CRC (1 << 11) /* TX CRC enable */
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#define TX_BD_PAD (1 << 12) /* pad enable */
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#define TX_BD_WRAP (1 << 13)
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#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
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#define TX_BD_READY (1 << 15) /* TX buffer ready */
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#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
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#define TX_BD_LEN_MASK (0xffff << 16)
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#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
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TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
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/* RX buffer descriptor */
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#define RX_BD_LC (1 << 0) /* late collision */
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#define RX_BD_CRC (1 << 1) /* RX CRC error */
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#define RX_BD_SF (1 << 2) /* short frame */
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#define RX_BD_TL (1 << 3) /* too long */
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#define RX_BD_DN (1 << 4) /* dribble nibble */
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#define RX_BD_IS (1 << 5) /* invalid symbol */
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#define RX_BD_OR (1 << 6) /* receiver overrun */
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#define RX_BD_MISS (1 << 7)
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#define RX_BD_CF (1 << 8) /* control frame */
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#define RX_BD_WRAP (1 << 13)
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#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
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#define RX_BD_EMPTY (1 << 15)
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#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
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#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
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RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
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#define ETHOC_BUFSIZ 1536
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#define ETHOC_ZLEN 64
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#define ETHOC_BD_BASE 0x400
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#define ETHOC_TIMEOUT (HZ / 2)
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#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
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/**
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* struct ethoc - driver-private device structure
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* @num_tx: number of send buffers
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* @cur_tx: last send buffer written
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* @dty_tx: last buffer actually sent
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* @num_rx: number of receive buffers
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* @cur_rx: current receive buffer
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*/
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struct ethoc {
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u32 num_tx;
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u32 cur_tx;
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u32 dty_tx;
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u32 num_rx;
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u32 cur_rx;
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};
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/**
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* struct ethoc_bd - buffer descriptor
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* @stat: buffer statistics
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* @addr: physical memory address
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*/
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struct ethoc_bd {
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u32 stat;
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u32 addr;
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};
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static inline u32 ethoc_read(struct eth_device *dev, loff_t offset)
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{
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return readl(dev->iobase + offset);
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}
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static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data)
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{
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writel(data, dev->iobase + offset);
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}
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static inline void ethoc_read_bd(struct eth_device *dev, int index,
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struct ethoc_bd *bd)
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{
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loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
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bd->stat = ethoc_read(dev, offset + 0);
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bd->addr = ethoc_read(dev, offset + 4);
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}
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static inline void ethoc_write_bd(struct eth_device *dev, int index,
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const struct ethoc_bd *bd)
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{
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loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
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ethoc_write(dev, offset + 0, bd->stat);
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ethoc_write(dev, offset + 4, bd->addr);
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}
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static inline void ethoc_set_mac_address(struct eth_device *dev)
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{
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u8 *mac = dev->enetaddr;
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ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
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(mac[4] << 8) | (mac[5] << 0));
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ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
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}
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static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
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{
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ethoc_write(dev, INT_SOURCE, mask);
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}
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static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
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{
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u32 mode = ethoc_read(dev, MODER);
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mode |= MODER_RXEN | MODER_TXEN;
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ethoc_write(dev, MODER, mode);
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}
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static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
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{
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u32 mode = ethoc_read(dev, MODER);
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mode &= ~(MODER_RXEN | MODER_TXEN);
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ethoc_write(dev, MODER, mode);
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}
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static int ethoc_init_ring(struct eth_device *dev)
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{
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struct ethoc *priv = (struct ethoc *)dev->priv;
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struct ethoc_bd bd;
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int i;
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priv->cur_tx = 0;
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priv->dty_tx = 0;
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priv->cur_rx = 0;
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/* setup transmission buffers */
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bd.stat = TX_BD_IRQ | TX_BD_CRC;
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for (i = 0; i < priv->num_tx; i++) {
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if (i == priv->num_tx - 1)
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bd.stat |= TX_BD_WRAP;
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ethoc_write_bd(dev, i, &bd);
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}
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bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
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for (i = 0; i < priv->num_rx; i++) {
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bd.addr = (u32)NetRxPackets[i];
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if (i == priv->num_rx - 1)
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bd.stat |= RX_BD_WRAP;
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flush_dcache(bd.addr, PKTSIZE_ALIGN);
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ethoc_write_bd(dev, priv->num_tx + i, &bd);
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}
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return 0;
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}
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static int ethoc_reset(struct eth_device *dev)
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{
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u32 mode;
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/* TODO: reset controller? */
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ethoc_disable_rx_and_tx(dev);
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/* TODO: setup registers */
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/* enable FCS generation and automatic padding */
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mode = ethoc_read(dev, MODER);
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mode |= MODER_CRC | MODER_PAD;
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ethoc_write(dev, MODER, mode);
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/* set full-duplex mode */
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mode = ethoc_read(dev, MODER);
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mode |= MODER_FULLD;
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ethoc_write(dev, MODER, mode);
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ethoc_write(dev, IPGT, 0x15);
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ethoc_ack_irq(dev, INT_MASK_ALL);
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ethoc_enable_rx_and_tx(dev);
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return 0;
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}
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static int ethoc_init(struct eth_device *dev, bd_t * bd)
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{
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struct ethoc *priv = (struct ethoc *)dev->priv;
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printf("ethoc\n");
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ethoc_set_mac_address(dev);
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priv->num_tx = 1;
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priv->num_rx = PKTBUFSRX;
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ethoc_write(dev, TX_BD_NUM, priv->num_tx);
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ethoc_init_ring(dev);
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ethoc_reset(dev);
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return 0;
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}
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static int ethoc_update_rx_stats(struct ethoc_bd *bd)
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{
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int ret = 0;
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if (bd->stat & RX_BD_TL) {
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debug("ETHOC: " "RX: frame too long\n");
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ret++;
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}
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if (bd->stat & RX_BD_SF) {
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debug("ETHOC: " "RX: frame too short\n");
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ret++;
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}
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if (bd->stat & RX_BD_DN)
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debug("ETHOC: " "RX: dribble nibble\n");
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if (bd->stat & RX_BD_CRC) {
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debug("ETHOC: " "RX: wrong CRC\n");
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ret++;
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}
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if (bd->stat & RX_BD_OR) {
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debug("ETHOC: " "RX: overrun\n");
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ret++;
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}
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if (bd->stat & RX_BD_LC) {
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debug("ETHOC: " "RX: late collision\n");
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ret++;
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}
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return ret;
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}
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static int ethoc_rx(struct eth_device *dev, int limit)
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{
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struct ethoc *priv = (struct ethoc *)dev->priv;
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int count;
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for (count = 0; count < limit; ++count) {
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u32 entry;
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struct ethoc_bd bd;
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entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
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ethoc_read_bd(dev, entry, &bd);
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if (bd.stat & RX_BD_EMPTY)
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break;
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debug("%s(): RX buffer %d, %x received\n",
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__func__, priv->cur_rx, bd.stat);
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if (ethoc_update_rx_stats(&bd) == 0) {
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int size = bd.stat >> 16;
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size -= 4; /* strip the CRC */
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NetReceive((void *)bd.addr, size);
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}
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/* clear the buffer descriptor so it can be reused */
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flush_dcache(bd.addr, PKTSIZE_ALIGN);
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bd.stat &= ~RX_BD_STATS;
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bd.stat |= RX_BD_EMPTY;
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ethoc_write_bd(dev, entry, &bd);
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priv->cur_rx++;
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}
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return count;
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}
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static int ethoc_update_tx_stats(struct ethoc_bd *bd)
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{
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if (bd->stat & TX_BD_LC)
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debug("ETHOC: " "TX: late collision\n");
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if (bd->stat & TX_BD_RL)
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debug("ETHOC: " "TX: retransmit limit\n");
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if (bd->stat & TX_BD_UR)
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debug("ETHOC: " "TX: underrun\n");
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if (bd->stat & TX_BD_CS)
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debug("ETHOC: " "TX: carrier sense lost\n");
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return 0;
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}
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static void ethoc_tx(struct eth_device *dev)
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{
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struct ethoc *priv = (struct ethoc *)dev->priv;
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u32 entry = priv->dty_tx % priv->num_tx;
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struct ethoc_bd bd;
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ethoc_read_bd(dev, entry, &bd);
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if ((bd.stat & TX_BD_READY) == 0)
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(void)ethoc_update_tx_stats(&bd);
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}
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static int ethoc_send(struct eth_device *dev, volatile void *packet, int length)
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{
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struct ethoc *priv = (struct ethoc *)dev->priv;
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struct ethoc_bd bd;
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u32 entry;
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u32 pending;
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int tmo;
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entry = priv->cur_tx % priv->num_tx;
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ethoc_read_bd(dev, entry, &bd);
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if (unlikely(length < ETHOC_ZLEN))
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bd.stat |= TX_BD_PAD;
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else
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bd.stat &= ~TX_BD_PAD;
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bd.addr = (u32)packet;
|
||||
|
||||
flush_dcache(bd.addr, length);
|
||||
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
|
||||
bd.stat |= TX_BD_LEN(length);
|
||||
ethoc_write_bd(dev, entry, &bd);
|
||||
|
||||
/* start transmit */
|
||||
bd.stat |= TX_BD_READY;
|
||||
ethoc_write_bd(dev, entry, &bd);
|
||||
|
||||
/* wait for transfer to succeed */
|
||||
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
|
||||
while (1) {
|
||||
pending = ethoc_read(dev, INT_SOURCE);
|
||||
ethoc_ack_irq(dev, pending & ~INT_MASK_RX);
|
||||
if (pending & INT_MASK_BUSY)
|
||||
debug("%s(): packet dropped\n", __func__);
|
||||
|
||||
if (pending & INT_MASK_TX) {
|
||||
ethoc_tx(dev);
|
||||
break;
|
||||
}
|
||||
if (get_timer(0) >= tmo) {
|
||||
debug("%s(): timed out\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
debug("%s(): packet sent\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ethoc_halt(struct eth_device *dev)
|
||||
{
|
||||
ethoc_disable_rx_and_tx(dev);
|
||||
}
|
||||
|
||||
static int ethoc_recv(struct eth_device *dev)
|
||||
{
|
||||
u32 pending;
|
||||
|
||||
pending = ethoc_read(dev, INT_SOURCE);
|
||||
ethoc_ack_irq(dev, pending);
|
||||
if (pending & INT_MASK_BUSY)
|
||||
debug("%s(): packet dropped\n", __func__);
|
||||
if (pending & INT_MASK_RX) {
|
||||
debug("%s(): rx irq\n", __func__);
|
||||
ethoc_rx(dev, PKTBUFSRX);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ethoc_initialize(u8 dev_num, int base_addr)
|
||||
{
|
||||
struct ethoc *priv;
|
||||
struct eth_device *dev;
|
||||
|
||||
priv = malloc(sizeof(*priv));
|
||||
if (!priv)
|
||||
return 0;
|
||||
dev = malloc(sizeof(*dev));
|
||||
if (!dev) {
|
||||
free(priv);
|
||||
return 0;
|
||||
}
|
||||
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
dev->priv = priv;
|
||||
dev->iobase = base_addr;
|
||||
dev->init = ethoc_init;
|
||||
dev->halt = ethoc_halt;
|
||||
dev->send = ethoc_send;
|
||||
dev->recv = ethoc_recv;
|
||||
sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
|
||||
|
||||
eth_register(dev);
|
||||
return 1;
|
||||
}
|
||||
@ -51,6 +51,7 @@ int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||
int e1000_initialize(bd_t *bis);
|
||||
int eepro100_initialize(bd_t *bis);
|
||||
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
|
||||
int ethoc_initialize(u8 dev_num, int base_addr);
|
||||
int eth_3com_initialize (bd_t * bis);
|
||||
int fec_initialize (bd_t *bis);
|
||||
int fecmxc_initialize (bd_t *bis);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user