leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mvebu: pinctrl: Add SD/eMMC PHY selector to the driver

Browse Source 
When the pin control driver selects SD/eMMC function for
a pin group, there is additional configuration to be done
for this case - switch the PHY to work with SDHCI interface.
This patch adds the missing functionality into the pin
control driver.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Konstantin Porotchkin 2018-05-25 14:20:52 +08:00 committed by Stefan Roese
parent f246648d37
commit f5db5979df
1 changed files with 57 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -16,8 +16,48 @@
#include <asm/arch-armada8k/soc-info.h>
#include "pinctrl-mvebu.h"
#define AP_EMMC_PHY_CTRL_REG 0x100
#define CP_EMMC_PHY_CTRL_REG 0x424
#define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
#define AP806_EMMC_CLK_PIN_ID 0
#define AP806_EMMC_CLK_FUNC 0x1
#define CP110_EMMC_CLK_PIN_ID 56
#define CP110_EMMC_CLK_FUNC 0xe
DECLARE_GLOBAL_DATA_PTR;
/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
* To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
* eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
* controller:
* - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
* - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
* If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
* muxltiplexer register to be on SDIO/eMMC controller
*/
void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
if ((pin == AP806_EMMC_CLK_PIN_ID) &&
(func == AP806_EMMC_CLK_FUNC)) {
clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
EMMC_PHY_CTRL_SDPHY_EN);
}
} else if (!fdt_node_check_compatible(blob, node,
"marvell,armada-8k-cpm-pinctrl")) {
if ((pin == CP110_EMMC_CLK_PIN_ID) &&
(func == CP110_EMMC_CLK_FUNC)) {
clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
EMMC_PHY_CTRL_SDPHY_EN);
}
}
}
/*
* mvebu_pinctrl_set_state: configure pin functions.
* @dev: the pinctrl device to be configured.
@ -47,9 +87,16 @@ int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
/*
* Check if setup of PHY mux is needed for this pins group.
* Only the first pin id in array is tested, all the rest use the same
* pin function.
*/
mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
for (i = 0; i < pin_count; i++) {
int reg_offset;
int field_offset;
int reg_offset;
int field_offset;
int pin = pin_arr[i];
if (function > priv->max_func) {
@ -96,6 +143,14 @@ static int mvebu_pinctrl_set_state_all(struct udevice *dev,
return -EINVAL;
}
/* Check if setup of PHY mux is needed for this pins group. */
if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,
func_arr[AP806_EMMC_CLK_PIN_ID]);
else
mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,
func_arr[CP110_EMMC_CLK_PIN_ID]);
for (pin = 0; pin < priv->pin_cnt; pin++) {
int reg_offset;
int field_offset;