arm: ti814x: Remove remaining support code
When the ti814x_evm config was removed most, but not all, of the
relevant support code was remove. Get rid of what was missed.
Fixes: 50b5326868 ("ti814x: Remove platform")
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
2b210540b1
commit
f55281665a
@ -13,7 +13,7 @@
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#include <asm/arch/clocks_am33xx.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
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#if defined(CONFIG_TI816X)
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#include <asm/arch/clock_ti81xx.h>
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#endif
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@ -44,9 +44,7 @@ struct cm_alwon {
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unsigned int mmu_clkstctrl;
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unsigned int mmucfg_clkstctrl;
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unsigned int ocmc0clkstctrl;
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#if defined(CONFIG_TI814X)
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unsigned int vcpclkstctrl;
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int ocmc1clkstctrl;
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#endif
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unsigned int mpuclkstctrl;
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@ -67,16 +65,7 @@ struct cm_alwon {
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unsigned int gpio1clkctrl;
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unsigned int i2c0clkctrl;
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unsigned int i2c1clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int mcasp345clkctrl;
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unsigned int atlclkctrl;
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unsigned int mlbclkctrl;
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unsigned int pataclkctrl;
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unsigned int resv1[1];
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unsigned int uart3clkctrl;
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unsigned int uart4clkctrl;
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unsigned int uart5clkctrl;
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int resv1[1];
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unsigned int timer1clkctrl;
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unsigned int timer2clkctrl;
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@ -93,16 +82,12 @@ struct cm_alwon {
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unsigned int mmudataclkctrl;
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unsigned int resv2[2];
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unsigned int mmucfgclkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int resv3[2];
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int resv3[1];
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unsigned int sdioclkctrl;
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#endif
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unsigned int ocmc0clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int vcpclkctrl;
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int ocmc1clkctrl;
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#endif
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unsigned int resv4[2];
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@ -112,9 +97,7 @@ struct cm_alwon {
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unsigned int ethernet0clkctrl;
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unsigned int ethernet1clkctrl;
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unsigned int mpuclkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int debugssclkctrl;
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int resv6[1];
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#endif
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unsigned int l3clkctrl;
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@ -126,14 +109,7 @@ struct cm_alwon {
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unsigned int tptc1clkctrl;
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unsigned int tptc2clkctrl;
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unsigned int tptc3clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int resv6[4];
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unsigned int dcan01clkctrl;
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unsigned int mmchs0clkctrl;
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unsigned int mmchs1clkctrl;
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unsigned int mmchs2clkctrl;
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unsigned int custefuseclkctrl;
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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unsigned int sr0clkctrl;
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unsigned int sr1clkctrl;
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#endif
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@ -16,8 +16,6 @@
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#include <asm/arch/hardware_am33xx.h>
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#elif defined(CONFIG_TI816X)
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#include <asm/arch/hardware_ti816x.h>
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#elif defined(CONFIG_TI814X)
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#include <asm/arch/hardware_ti814x.h>
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#elif defined(CONFIG_AM43XX)
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#include <asm/arch/hardware_am43xx.h>
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#endif
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@ -1,60 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* hardware_ti814x.h
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*
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* TI814x hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __AM33XX_HARDWARE_TI814X_H
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#define __AM33XX_HARDWARE_TI814X_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x48020000
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/* Watchdog Timer */
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#define WDT_BASE 0x481C7000
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/* Control Module Base Address */
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#define CTRL_BASE 0x48140000
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#define CTRL_DEVICE_BASE 0x48140600
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/* PRCM Base Address */
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#define PRCM_BASE 0x48180000
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#define CM_PER 0x44E00000
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#define CM_WKUP 0x44E00400
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#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
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#define PRM_RSTST (PRM_RSTCTRL + 8)
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/* PLL Subsystem Base Address */
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#define PLL_SUBSYS_BASE 0x481C5000
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x48140E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x47C0C400
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#define DDR_PHY_DATA_ADDR 0x47C0C4C8
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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#define DDR_DATA_REGS_NR 4
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#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
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#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A100800
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/* RTC base address */
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#define RTC_BASE 0x480C0000
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/* OTG */
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#define USB0_OTG_BASE 0x47401000
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#define USB1_OTG_BASE 0x47401800
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#endif /* __AM33XX_HARDWARE_TI814X_H */
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@ -24,10 +24,7 @@
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#define OMAP_HSMMC1_BASE 0x48060000
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#define OMAP_HSMMC2_BASE 0x481D8000
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#if defined(CONFIG_TI814X)
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#undef MMC_CLOCK_REFERENCE
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#define MMC_CLOCK_REFERENCE 192 /* MHz */
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#elif defined(CONFIG_TI816X)
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#if defined(CONFIG_TI816X)
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#undef MMC_CLOCK_REFERENCE
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#define MMC_CLOCK_REFERENCE 48 /* MHz */
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#endif
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@ -20,8 +20,6 @@
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#ifdef CONFIG_AM33XX
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#include <asm/arch/mux_am33xx.h>
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#elif defined(CONFIG_TI814X)
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#include <asm/arch/mux_ti814x.h>
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#elif defined(CONFIG_TI816X)
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#include <asm/arch/mux_ti816x.h>
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#elif defined(CONFIG_AM43XX)
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@ -1,311 +0,0 @@
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/*
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* mux_ti814x.h
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MUX_TI814X_H_
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#define _MUX_TI814X_H_
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/* PAD Control Fields */
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#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
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#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
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#define PULLUDEN (0x0 << 16) /* Pull up enabled */
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#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
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#define MODE(val) val /* used for Readability */
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#define MUX_CFG(value, offset) \
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{ \
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int tmp; \
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tmp = __raw_readl(CTRL_BASE + offset); \
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tmp &= PINCNTL_RSV_MSK; \
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__raw_writel(tmp | value, (CTRL_BASE + offset));\
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}
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/*
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* PAD CONTROL OFFSETS
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* Field names corresponds to the pad signal name
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*/
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struct pad_signals {
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int pincntl1;
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int pincntl2;
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int pincntl3;
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int pincntl4;
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int pincntl5;
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int pincntl6;
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int pincntl7;
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int pincntl8;
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int pincntl9;
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int pincntl10;
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int pincntl11;
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int pincntl12;
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int pincntl13;
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int pincntl14;
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int pincntl15;
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int pincntl16;
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int pincntl17;
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int pincntl18;
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int pincntl19;
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int pincntl20;
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int pincntl21;
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int pincntl22;
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int pincntl23;
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int pincntl24;
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int pincntl25;
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int pincntl26;
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int pincntl27;
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int pincntl28;
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int pincntl29;
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int pincntl30;
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int pincntl31;
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int pincntl32;
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int pincntl33;
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int pincntl34;
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int pincntl35;
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int pincntl36;
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int pincntl37;
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int pincntl38;
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int pincntl39;
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int pincntl40;
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int pincntl41;
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int pincntl42;
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int pincntl43;
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int pincntl44;
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int pincntl45;
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int pincntl46;
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int pincntl47;
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int pincntl48;
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int pincntl49;
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int pincntl50;
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int pincntl51;
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int pincntl52;
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int pincntl53;
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int pincntl54;
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int pincntl55;
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int pincntl56;
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int pincntl57;
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int pincntl58;
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int pincntl59;
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int pincntl60;
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int pincntl61;
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int pincntl62;
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int pincntl63;
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int pincntl64;
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int pincntl65;
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int pincntl66;
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int pincntl67;
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int pincntl68;
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int pincntl69;
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int pincntl70;
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int pincntl71;
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int pincntl72;
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int pincntl73;
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int pincntl74;
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int pincntl75;
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int pincntl76;
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int pincntl77;
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int pincntl78;
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int pincntl79;
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int pincntl80;
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int pincntl81;
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int pincntl82;
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int pincntl83;
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int pincntl84;
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int pincntl85;
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int pincntl86;
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int pincntl87;
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int pincntl88;
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int pincntl89;
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int pincntl90;
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int pincntl91;
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int pincntl92;
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int pincntl93;
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int pincntl94;
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int pincntl95;
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int pincntl96;
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int pincntl97;
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int pincntl98;
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int pincntl99;
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int pincntl100;
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int pincntl101;
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int pincntl102;
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int pincntl103;
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int pincntl104;
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int pincntl105;
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int pincntl106;
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int pincntl107;
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int pincntl108;
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int pincntl109;
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int pincntl110;
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int pincntl111;
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int pincntl112;
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int pincntl113;
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int pincntl114;
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int pincntl115;
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int pincntl116;
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int pincntl117;
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int pincntl118;
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int pincntl119;
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int pincntl120;
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int pincntl121;
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int pincntl122;
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int pincntl123;
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int pincntl124;
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int pincntl125;
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int pincntl126;
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int pincntl127;
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int pincntl128;
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int pincntl129;
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int pincntl130;
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int pincntl131;
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int pincntl132;
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int pincntl133;
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int pincntl134;
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int pincntl135;
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int pincntl136;
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int pincntl137;
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int pincntl138;
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int pincntl139;
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int pincntl140;
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int pincntl141;
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int pincntl142;
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int pincntl143;
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int pincntl144;
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int pincntl145;
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int pincntl146;
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int pincntl147;
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int pincntl148;
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int pincntl149;
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int pincntl150;
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int pincntl151;
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int pincntl152;
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int pincntl153;
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int pincntl154;
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int pincntl155;
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int pincntl156;
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int pincntl157;
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int pincntl158;
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int pincntl159;
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int pincntl160;
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int pincntl161;
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int pincntl162;
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int pincntl163;
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int pincntl164;
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int pincntl165;
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int pincntl166;
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int pincntl167;
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int pincntl168;
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int pincntl169;
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int pincntl170;
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int pincntl171;
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int pincntl172;
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int pincntl173;
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int pincntl174;
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int pincntl175;
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int pincntl176;
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int pincntl177;
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int pincntl178;
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int pincntl179;
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int pincntl180;
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int pincntl181;
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int pincntl182;
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int pincntl183;
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int pincntl184;
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int pincntl185;
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int pincntl186;
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int pincntl187;
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int pincntl188;
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int pincntl189;
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int pincntl190;
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int pincntl191;
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int pincntl192;
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int pincntl193;
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int pincntl194;
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int pincntl195;
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int pincntl196;
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int pincntl197;
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int pincntl198;
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int pincntl199;
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int pincntl200;
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int pincntl201;
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int pincntl202;
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int pincntl203;
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int pincntl204;
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int pincntl205;
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int pincntl206;
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int pincntl207;
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int pincntl208;
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int pincntl209;
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int pincntl210;
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int pincntl211;
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int pincntl212;
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int pincntl213;
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int pincntl214;
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int pincntl215;
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int pincntl216;
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int pincntl217;
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int pincntl218;
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int pincntl219;
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int pincntl220;
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int pincntl221;
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int pincntl222;
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int pincntl223;
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int pincntl224;
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int pincntl225;
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int pincntl226;
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int pincntl227;
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int pincntl228;
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int pincntl229;
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int pincntl230;
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int pincntl231;
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int pincntl232;
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int pincntl233;
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int pincntl234;
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int pincntl235;
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int pincntl236;
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int pincntl237;
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int pincntl238;
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int pincntl239;
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int pincntl240;
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int pincntl241;
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int pincntl242;
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int pincntl243;
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int pincntl244;
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int pincntl245;
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int pincntl246;
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int pincntl247;
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int pincntl248;
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int pincntl249;
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int pincntl250;
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int pincntl251;
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int pincntl252;
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int pincntl253;
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int pincntl254;
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int pincntl255;
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int pincntl256;
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int pincntl257;
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int pincntl258;
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int pincntl259;
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int pincntl260;
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int pincntl261;
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int pincntl262;
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int pincntl263;
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int pincntl264;
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int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI814X_H_ */
|
||||
@ -20,7 +20,7 @@
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40310000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4030B800
|
||||
#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#define NON_SECURE_SRAM_START 0x40300000
|
||||
#define NON_SECURE_SRAM_END 0x40320000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4031B800
|
||||
|
||||
@ -9,21 +9,7 @@
|
||||
#define BOOT_DEVICE_NONE 0x00
|
||||
#define BOOT_DEVICE_MMC2_2 0xFF
|
||||
|
||||
#if defined(CONFIG_TI814X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_NAND_I2C 0x06
|
||||
#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
#define BOOT_DEVICE_SPI 0x15
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x44
|
||||
#define BOOT_DEVICE_CPGMAC 0x46
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#if defined(CONFIG_TI816X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x03
|
||||
|
||||
@ -75,14 +75,6 @@ config OMAP54XX
|
||||
imply SPL_SERIAL
|
||||
imply SYS_I2C_OMAP24XX
|
||||
|
||||
config TI814X
|
||||
bool "TI814X SoC"
|
||||
select SPECIFY_CONSOLE_INDEX
|
||||
help
|
||||
Support for AM335x SOC from Texas Instruments.
|
||||
The AM335x high performance SOC features a Cortex-A8
|
||||
ARM core and more.
|
||||
|
||||
config TI816X
|
||||
bool "TI816X SoC"
|
||||
select SPECIFY_CONSOLE_INDEX
|
||||
|
||||
@ -8,16 +8,6 @@ config TARGET_TI816X_EVM
|
||||
|
||||
endif
|
||||
|
||||
if TI814X
|
||||
|
||||
config TARGET_TI814X_EVM
|
||||
bool "Support ti814x_evm"
|
||||
help
|
||||
This option specifies support for the TI8148
|
||||
EVM development platform.
|
||||
|
||||
endif
|
||||
|
||||
if AM33XX
|
||||
|
||||
config AM33XX_CHILISOM
|
||||
|
||||
@ -3,7 +3,6 @@
|
||||
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
|
||||
obj-$(CONFIG_AM33XX) += clock_am33xx.o
|
||||
obj-$(CONFIG_TI814X) += clock_ti814x.o
|
||||
obj-$(CONFIG_AM43XX) += clock_am43xx.o
|
||||
|
||||
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
|
||||
|
||||
@ -1,410 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* clock_ti814x.c
|
||||
*
|
||||
* Clocks for TI814X based boards
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* PRCM */
|
||||
#define PRCM_MOD_EN 0x2
|
||||
|
||||
/* CLK_SRC */
|
||||
#define OSC_SRC0 0
|
||||
#define OSC_SRC1 1
|
||||
|
||||
#define L3_OSC_SRC OSC_SRC0
|
||||
|
||||
#define OSC_0_FREQ 20
|
||||
|
||||
#define DCO_HS2_MIN 500
|
||||
#define DCO_HS2_MAX 1000
|
||||
#define DCO_HS1_MIN 1000
|
||||
#define DCO_HS1_MAX 2000
|
||||
|
||||
#define SELFREQDCO_HS2 0x00000801
|
||||
#define SELFREQDCO_HS1 0x00001001
|
||||
|
||||
#define MPU_N 0x1
|
||||
#define MPU_M 0x3C
|
||||
#define MPU_M2 1
|
||||
#define MPU_CLKCTRL 0x1
|
||||
|
||||
#define L3_N 19
|
||||
#define L3_M 880
|
||||
#define L3_M2 4
|
||||
#define L3_CLKCTRL 0x801
|
||||
|
||||
#define DDR_N 19
|
||||
#define DDR_M 666
|
||||
#define DDR_M2 2
|
||||
#define DDR_CLKCTRL 0x801
|
||||
|
||||
/* ADPLLJ register values */
|
||||
#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
|
||||
#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
|
||||
#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
|
||||
#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
|
||||
#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
|
||||
#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
|
||||
#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
|
||||
#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
|
||||
#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
|
||||
#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
|
||||
#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
|
||||
#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
|
||||
ADPLLJ_CLKCTRL_CLKOUTEN | \
|
||||
ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
|
||||
ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
|
||||
|
||||
#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
|
||||
#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
|
||||
#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
|
||||
ADPLLJ_STATUS_FREQLOCK)
|
||||
#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
|
||||
#define ADPLLJ_STATUS_BYPASS (1 << 0)
|
||||
#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
|
||||
ADPLLJ_STATUS_BYPASS)
|
||||
|
||||
#define ADPLLJ_TENABLE_ENB (1 << 0)
|
||||
#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
|
||||
|
||||
#define ADPLLJ_M2NDIV_M2SHIFT 16
|
||||
|
||||
#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
|
||||
#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
|
||||
#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
|
||||
|
||||
struct ad_pll {
|
||||
unsigned int pwrctrl;
|
||||
unsigned int clkctrl;
|
||||
unsigned int tenable;
|
||||
unsigned int tenablediv;
|
||||
unsigned int m2ndiv;
|
||||
unsigned int mn2div;
|
||||
unsigned int fracdiv;
|
||||
unsigned int bwctrl;
|
||||
unsigned int fracctrl;
|
||||
unsigned int status;
|
||||
unsigned int m3div;
|
||||
unsigned int rampctrl;
|
||||
};
|
||||
|
||||
#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
|
||||
|
||||
#define ENET_CLKCTRL_CMPL 0x30000
|
||||
|
||||
#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
|
||||
|
||||
struct sata_pll {
|
||||
unsigned int pllcfg0;
|
||||
unsigned int pllcfg1;
|
||||
unsigned int pllcfg2;
|
||||
unsigned int pllcfg3;
|
||||
unsigned int pllcfg4;
|
||||
unsigned int pllstatus;
|
||||
unsigned int rxstatus;
|
||||
unsigned int txstatus;
|
||||
unsigned int testcfg;
|
||||
};
|
||||
|
||||
#define SEL_IN_FREQ (0x1 << 31)
|
||||
#define DIGCLRZ (0x1 << 30)
|
||||
#define ENDIGLDO (0x1 << 4)
|
||||
#define APLL_CP_CURR (0x1 << 3)
|
||||
#define ENBGSC_REF (0x1 << 2)
|
||||
#define ENPLLLDO (0x1 << 1)
|
||||
#define ENPLL (0x1 << 0)
|
||||
|
||||
#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
|
||||
#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
|
||||
#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
|
||||
#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
|
||||
ENPLLLDO | ENPLL)
|
||||
|
||||
#define PLL_LOCK (0x1 << 0)
|
||||
|
||||
#define ENSATAMODE (0x1 << 31)
|
||||
#define PLLREFSEL (0x1 << 30)
|
||||
#define MDIVINT (0x4b << 18)
|
||||
#define EN_CLKAUX (0x1 << 5)
|
||||
#define EN_CLK125M (0x1 << 4)
|
||||
#define EN_CLK100M (0x1 << 3)
|
||||
#define EN_CLK50M (0x1 << 2)
|
||||
|
||||
#define SATA_PLLCFG1 (ENSATAMODE | \
|
||||
PLLREFSEL | \
|
||||
MDIVINT | \
|
||||
EN_CLKAUX | \
|
||||
EN_CLK125M | \
|
||||
EN_CLK100M | \
|
||||
EN_CLK50M)
|
||||
|
||||
#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
|
||||
#define PLLDO_EN_LDO_STABLE (0x1 << 11)
|
||||
#define PLLDO_EN_BUF_CUR (0x1 << 7)
|
||||
#define PLLDO_EN_LP (0x1 << 6)
|
||||
#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
|
||||
|
||||
#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
|
||||
PLLDO_EN_LDO_STABLE | \
|
||||
PLLDO_EN_BUF_CUR | \
|
||||
PLLDO_EN_LP | \
|
||||
PLLDO_CTRL_TRIM_1_4V)
|
||||
|
||||
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
|
||||
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
|
||||
const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
|
||||
|
||||
/*
|
||||
* Enable the peripheral clock for required peripherals
|
||||
*/
|
||||
static void enable_per_clocks(void)
|
||||
{
|
||||
/* HSMMC1 */
|
||||
writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
|
||||
while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
/* Ethernet */
|
||||
writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
|
||||
writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
|
||||
while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
|
||||
;
|
||||
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
|
||||
while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
|
||||
;
|
||||
|
||||
/* RTC clocks */
|
||||
writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
|
||||
writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
|
||||
while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* select the HS1 or HS2 for DCO Freq
|
||||
* return : CLKCTRL
|
||||
*/
|
||||
static u32 pll_dco_freq_sel(u32 clkout_dco)
|
||||
{
|
||||
if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
|
||||
return SELFREQDCO_HS2;
|
||||
else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
|
||||
return SELFREQDCO_HS1;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* select the sigma delta config
|
||||
* return: sigma delta val
|
||||
*/
|
||||
static u32 pll_sigma_delta_val(u32 clkout_dco)
|
||||
{
|
||||
u32 sig_val = 0;
|
||||
|
||||
sig_val = (clkout_dco + 225) / 250;
|
||||
sig_val = sig_val << 24;
|
||||
|
||||
return sig_val;
|
||||
}
|
||||
|
||||
/*
|
||||
* configure individual ADPLLJ
|
||||
*/
|
||||
static void pll_config(u32 base, u32 n, u32 m, u32 m2,
|
||||
u32 clkctrl_val, int adpllj)
|
||||
{
|
||||
const struct ad_pll *adpll = (struct ad_pll *)base;
|
||||
u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
|
||||
u32 sig_val = 0, hs_mod = 0;
|
||||
|
||||
m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
|
||||
mn2val = m;
|
||||
|
||||
/* calculate clkout_dco */
|
||||
clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
|
||||
|
||||
/* sigma delta & Hs mode selection skip for ADPLLS*/
|
||||
if (adpllj) {
|
||||
sig_val = pll_sigma_delta_val(clkout_dco);
|
||||
hs_mod = pll_dco_freq_sel(clkout_dco);
|
||||
}
|
||||
|
||||
/* by-pass pll */
|
||||
read_clkctrl = readl(&adpll->clkctrl);
|
||||
writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
|
||||
while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
|
||||
!= ADPLLJ_STATUS_BYPASSANDACK)
|
||||
;
|
||||
|
||||
/* clear TINITZ */
|
||||
read_clkctrl = readl(&adpll->clkctrl);
|
||||
writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
|
||||
|
||||
/*
|
||||
* ref_clk = 20/(n + 1);
|
||||
* clkout_dco = ref_clk * m;
|
||||
* clk_out = clkout_dco/m2;
|
||||
*/
|
||||
read_clkctrl = readl(&adpll->clkctrl) &
|
||||
~(ADPLLJ_CLKCTRL_LPMODE |
|
||||
ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
|
||||
ADPLLJ_CLKCTRL_REGM4XEN);
|
||||
writel(m2nval, &adpll->m2ndiv);
|
||||
writel(mn2val, &adpll->mn2div);
|
||||
|
||||
/* Skip for modena(ADPLLS) */
|
||||
if (adpllj) {
|
||||
writel(sig_val, &adpll->fracdiv);
|
||||
writel((read_clkctrl | hs_mod), &adpll->clkctrl);
|
||||
}
|
||||
|
||||
/* Load M2, N2 dividers of ADPLL */
|
||||
writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
|
||||
writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
|
||||
|
||||
/* Load M, N dividers of ADPLL */
|
||||
writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
|
||||
writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
|
||||
|
||||
/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
|
||||
read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
|
||||
if (adpllj)
|
||||
writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
|
||||
&adpll->clkctrl);
|
||||
|
||||
/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
|
||||
read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
|
||||
writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
|
||||
|
||||
/* Wait for phase and freq lock */
|
||||
while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
|
||||
ADPLLJ_STATUS_PHSFRQLOCK)
|
||||
;
|
||||
}
|
||||
|
||||
static void unlock_pll_control_mmr(void)
|
||||
{
|
||||
/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
|
||||
writel(0x1EDA4C3D, 0x481C5040);
|
||||
writel(0x2FF1AC2B, 0x48140060);
|
||||
writel(0xF757FDC0, 0x48140064);
|
||||
writel(0xE2BC3A6D, 0x48140068);
|
||||
writel(0x1EBF131D, 0x4814006c);
|
||||
writel(0x6F361E05, 0x48140070);
|
||||
}
|
||||
|
||||
static void mpu_pll_config(void)
|
||||
{
|
||||
pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
|
||||
}
|
||||
|
||||
static void l3_pll_config(void)
|
||||
{
|
||||
u32 l3_osc_src, rd_osc_src = 0;
|
||||
|
||||
l3_osc_src = L3_OSC_SRC;
|
||||
rd_osc_src = readl(OSC_SRC_CTRL);
|
||||
|
||||
if (OSC_SRC0 == l3_osc_src)
|
||||
writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
|
||||
else
|
||||
writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
|
||||
|
||||
pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
|
||||
}
|
||||
|
||||
void ddr_pll_config(unsigned int ddrpll_m)
|
||||
{
|
||||
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
|
||||
}
|
||||
|
||||
void sata_pll_config(void)
|
||||
{
|
||||
/*
|
||||
* This sequence for configuring the SATA PLL
|
||||
* resident in the control module is documented
|
||||
* in TI8148 TRM section 21.3.1
|
||||
*/
|
||||
writel(SATA_PLLCFG1, &spll->pllcfg1);
|
||||
udelay(50);
|
||||
|
||||
writel(SATA_PLLCFG3, &spll->pllcfg3);
|
||||
udelay(50);
|
||||
|
||||
writel(SATA_PLLCFG0_1, &spll->pllcfg0);
|
||||
udelay(50);
|
||||
|
||||
writel(SATA_PLLCFG0_2, &spll->pllcfg0);
|
||||
udelay(50);
|
||||
|
||||
writel(SATA_PLLCFG0_3, &spll->pllcfg0);
|
||||
udelay(50);
|
||||
|
||||
writel(SATA_PLLCFG0_4, &spll->pllcfg0);
|
||||
udelay(50);
|
||||
|
||||
while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
|
||||
;
|
||||
}
|
||||
|
||||
void enable_dmm_clocks(void)
|
||||
{
|
||||
writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
|
||||
writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
|
||||
writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
|
||||
while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
|
||||
;
|
||||
writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
|
||||
while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
|
||||
;
|
||||
while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
|
||||
;
|
||||
writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
|
||||
while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
|
||||
;
|
||||
writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
|
||||
while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
|
||||
;
|
||||
}
|
||||
|
||||
void setup_clocks_for_console(void)
|
||||
{
|
||||
unlock_pll_control_mmr();
|
||||
/* UART0 */
|
||||
writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
|
||||
while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
}
|
||||
|
||||
void setup_early_clocks(void)
|
||||
{
|
||||
setup_clocks_for_console();
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure the PLL/PRCM for necessary peripherals
|
||||
*/
|
||||
void prcm_init(void)
|
||||
{
|
||||
/* Enable the control module */
|
||||
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
|
||||
|
||||
/* Configure PLLs */
|
||||
mpu_pll_config();
|
||||
l3_pll_config();
|
||||
sata_pll_config();
|
||||
|
||||
/* Enable the required peripherals */
|
||||
enable_per_clocks();
|
||||
}
|
||||
@ -28,26 +28,6 @@ static struct cm_device_inst *cm_device =
|
||||
(struct cm_device_inst *)CM_DEVICE_INST;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TI814X
|
||||
void config_dmm(const struct dmm_lisa_map_regs *regs)
|
||||
{
|
||||
struct dmm_lisa_map_regs *hw_lisa_map_regs =
|
||||
(struct dmm_lisa_map_regs *)DMM_BASE;
|
||||
|
||||
enable_dmm_clocks();
|
||||
|
||||
writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
|
||||
writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
|
||||
writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
|
||||
writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
|
||||
|
||||
writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
|
||||
writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
|
||||
writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
|
||||
writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void config_vtp(int nr)
|
||||
{
|
||||
writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
|
||||
|
||||
@ -183,7 +183,7 @@ void save_omap_boot_params(void)
|
||||
|
||||
gd->arch.omap_boot_mode = boot_mode;
|
||||
|
||||
#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
|
||||
#if !defined(CONFIG_TI816X) && \
|
||||
!defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
|
||||
|
||||
/* CH flags */
|
||||
|
||||
@ -704,7 +704,7 @@ config SYS_I2C_BUS_MAX
|
||||
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
|
||||
default 2 if TI816X
|
||||
default 3 if OMAP34XX || AM33XX || AM43XX
|
||||
default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
|
||||
default 4 if ARCH_SOCFPGA || OMAP44XX
|
||||
default 5 if OMAP54XX
|
||||
help
|
||||
Define the maximum number of available I2C buses.
|
||||
|
||||
@ -79,10 +79,6 @@ struct cpsw_slave_regs {
|
||||
u32 tx_pri_map;
|
||||
#ifdef CONFIG_AM33XX
|
||||
u32 gap_thresh;
|
||||
#elif defined(CONFIG_TI814X)
|
||||
u32 ts_ctl;
|
||||
u32 ts_seq_ltype;
|
||||
u32 ts_vlan;
|
||||
#endif
|
||||
u32 sa_lo;
|
||||
u32 sa_hi;
|
||||
|
||||
@ -1,102 +0,0 @@
|
||||
/*
|
||||
* ti814x_evm.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_TI814X_EVM_H
|
||||
#define __CONFIG_TI814X_EVM_H
|
||||
|
||||
#include <asm/arch/omap.h>
|
||||
|
||||
/* commands to include */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80200000\0" \
|
||||
"fdtaddr=0x80F80000\0" \
|
||||
"rdaddr=0x81000000\0" \
|
||||
"bootfile=/boot/uImage\0" \
|
||||
"fdtfile=\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
||||
"ramrootfstype=ext2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"ramargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${ramroot} " \
|
||||
"rootfstype=${ramrootfstype}\0" \
|
||||
"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
||||
"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
|
||||
"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"ramboot=echo Booting from ramdisk ...; " \
|
||||
"run ramargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"fdtfile=ti814x-evm.dtb\0" \
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
|
||||
/**
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x80000000
|
||||
|
||||
/**
|
||||
* Platform/Board specific defs
|
||||
*/
|
||||
#define CFG_SYS_TIMERBASE 0x4802E000
|
||||
|
||||
/* NS16550 Configuration */
|
||||
#define CFG_SYS_NS16550_CLK (48000000)
|
||||
#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
|
||||
|
||||
/* CPU */
|
||||
|
||||
/* Defines for SPL */
|
||||
|
||||
/*
|
||||
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||
* 64 bytes before this address should be set aside for u-boot.img's
|
||||
* header. That is 0x800FFFC0--0x80800000 should not be used for any
|
||||
* other needs.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Since SPL did pll and ddr initialization for us,
|
||||
* we don't need to do it twice.
|
||||
*/
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
|
||||
|
||||
#endif /* ! __CONFIG_TI814X_EVM_H */
|
||||
Loading…
Reference in New Issue
Block a user