Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig
This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
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@ -1599,6 +1599,7 @@ config TARGET_LS1021AQDS
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select LS1_DEEP_SLEEP
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select PEN_ADDR_BIG_ENDIAN
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select SUPPORT_SPL
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select SYS_FSL_DDR
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select FSL_DDR_INTERACTIVE
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@ -1617,6 +1618,7 @@ config TARGET_LS1021ATWR
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select LS1_DEEP_SLEEP
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select PEN_ADDR_BIG_ENDIAN
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select SUPPORT_SPL
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select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
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select GPIO_EXTRA_HEADER
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@ -1681,6 +1683,7 @@ config TARGET_LS1021AIOT
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select PEN_ADDR_BIG_ENDIAN
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select SUPPORT_SPL
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select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
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select GPIO_EXTRA_HEADER
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@ -51,6 +51,9 @@ config MAX_CPUS
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config PEN_ADDR_BIG_ENDIAN
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bool
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config SYS_CCI400_OFFSET
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hex "Offset for CCI400 base"
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depends on SYS_FSL_HAS_CCI400
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@ -68,7 +68,6 @@
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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@ -242,7 +242,6 @@
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* MMC
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*/
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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@ -152,7 +152,6 @@
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/* GPIO */
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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