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powerpc: P1020RDB-PD: Separate from P1_P2_RDB_PC in Kconfig

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Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020RDB_PD.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun
2016-11-17 13:53:33 -08:00
parent aa14620c2e
commit f404b66ce1
11 changed files with 24 additions and 20 deletions
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3
board/freescale/p1_p2_rdb_pc/Kconfig
View File

@@ -1,6 +1,7 @@
if TARGET_P1_P2_RDB_PC || \
TARGET_P1020MBG || \
TARGET_P1020RDB_PC
TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD
config SYS_BOARD
default "p1_p2_rdb_pc"

2
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = {
.refresh_rate_ps = 7800000,
.tfaw_ps = 30000,
};
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,

4
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
#endif
@@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);

2
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,