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powerpc: P1020RDB-PD: Separate from P1_P2_RDB_PC in Kconfig

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Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020RDB_PD.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-11-17 13:53:33 -08:00
parent aa14620c2e
commit f404b66ce1
11 changed files with 24 additions and 20 deletions
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5
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -125,6 +125,11 @@ config TARGET_P1020RDB_PC
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1020RDB_PD
bool "Support P1020RDB-PD"
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"

3
board/freescale/p1_p2_rdb_pc/Kconfig
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@ -1,6 +1,7 @@
if TARGET_P1_P2_RDB_PC || \
TARGET_P1020MBG || \
TARGET_P1020RDB_PC
TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD
config SYS_BOARD
default "p1_p2_rdb_pc"

2
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = {
.refresh_rate_ps = 7800000,
.tfaw_ps = 30000,
};
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,

4
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
#endif
@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);

2
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,

4
configs/P1020RDB-PD_NAND_defconfig
View File

@ -2,12 +2,12 @@ CONFIG_PPC=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_TPL=y

4
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y

4
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y

3
configs/P1020RDB-PD_defconfig
View File

@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y

12
include/configs/p1_p2_rdb_pc.h
View File

@ -58,7 +58,7 @@
* 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
*/
#if defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_BOARDNAME "P1020RDB-PD"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
@ -336,7 +336,7 @@
#define SPD_EEPROM_ADDRESS 0x52
#undef CONFIG_FSL_DDR_INTERACTIVE
#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#else
@ -406,7 +406,7 @@
/*
* Local Bus Definitions
*/
#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
#define CONFIG_SYS_FLASH_BASE 0xec000000
#elif defined(CONFIG_P1020UTM)
@ -455,7 +455,7 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
#if defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#else
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
@ -466,7 +466,7 @@
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#if defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
@ -853,7 +853,7 @@
#endif
#endif
#if defined(CONFIG_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif

1
scripts/config_whitelist.txt
View File

@ -3384,7 +3384,6 @@ CONFIG_OS_ENV_ADDR
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
CONFIG_P1020
CONFIG_P1020RDB_PD
CONFIG_P1020UTM
CONFIG_P1021
CONFIG_P1021RDB