x86: conga-qeval20-qa3: Add support for internal UART
This patch adds support to enable and use the internal BayTrail UART instead of the one integrated in the Super IO Winbond chip. For this, a 2nd defconfig file is added. This is useful for tests done for the congatec SoM used on baseboards without such a Super IO chip. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -12,6 +12,7 @@
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int board_early_init_f(void)
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{
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#ifndef CONFIG_INTERNAL_UART
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/*
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* The FSP enables the BayTrail internal legacy UART (again).
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* Disable it again, so that the Winbond one can be used.
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@ -21,6 +22,7 @@ int board_early_init_f(void)
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/* Enable the legacy UART in the Winbond W83627 Super IO chip */
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winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
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UART0_BASE, UART0_IRQ);
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#endif
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return 0;
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}
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63
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
Normal file
63
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
Normal file
@ -0,0 +1,63 @@
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CONFIG_X86=y
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CONFIG_VENDOR_CONGATEC=y
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CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
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CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
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CONFIG_INTERNAL_UART=y
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CONFIG_HAVE_INTEL_ME=y
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CONFIG_ENABLE_MRC_CACHE=y
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CONFIG_SMP=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_GENERATE_PIRQ_TABLE=y
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CONFIG_GENERATE_MP_TABLE=y
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CONFIG_GENERATE_ACPI_TABLE=y
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CONFIG_SEABIOS=y
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_CPU=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CPU=y
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CONFIG_WINBOND_W83627=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_ETH=y
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CONFIG_E1000=y
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CONFIG_DM_PCI=y
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CONFIG_DM_RTC=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0x3f8
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CONFIG_DEBUG_UART_CLOCK=1843200
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CONFIG_SYS_NS16550=y
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CONFIG_ICH_SPI=y
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CONFIG_TIMER=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_114=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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