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Merge branch 'origin' into kconfig-for-1.3.1

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Conflicts:

	drivers/Makefile
This commit is contained in:
Grant Likely 2007-11-16 21:01:19 -07:00
commit efe33035ac
40 changed files with 1995 additions and 241 deletions
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322
CHANGELOG
View File

@ -1,3 +1,297 @@
commit fd329e6f05bbdfe6bd71b0e09f0c76d3b0a025a5
Author: Luotao Fu <l.fu@pengutronix.de>
Date: Wed Nov 14 18:58:33 2007 +0100
Fix the i2c frequency and default address in rsdproto board
rsdproto board support has wrong I2C frequency and wrong return value
handling.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
commit 429c180edad038f91c989cb14b478228092e7054
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Nov 17 01:45:38 2007 +0100
powerpc: Backout relocation changes for MPC5121, too.
Apply Grant Likely's backout to MPC5121 code, too.
Pointed out by Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 1c3dd43338a077165e7e0309cb3994e65d2bdbf8
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Tue Nov 13 22:18:33 2007 -0700
powerpc: Backout relocation changes.
Ugh. I *hate* to back this change out, but these compiler flags don't
work for relocation on all versions of GCC. I've not been able to
reproduce the environment in my setup (and hence, not been able to
find a combination that *does* work), so I've got no choice but to go
back to the old gcc flags and linker script.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 5c15010efad980ad5498cc565fc1ed70df2f52b4
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Tue Nov 13 09:11:05 2007 +0100
Fixed mips_io_port_base build errors.
This patch has been sent on:
- 29 Sep 2007
Although mips_io_port_base is currently a part of IDE command, it is quite
fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
it to MIPS general part, and introduce `set_io_port_base()' from Linux.
This patch is triggered by multiple definition of `mips_io_port_base' build
error on gth2 (and tb0229 also needs this fix.)
board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 6ecbb7a3fa9b0940ed33e490d195d4b6830b2422
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Nov 17 01:30:40 2007 +0100
Fix a bug in the slave serial programming mode for the Xilinx
Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if
the most significant bit was set, which did not work on any
architecture where "char" defaulted to be an unsigned type.
Based on a patch by Angelos Manousaridis <amanous@inaccessnetworks.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit d08b7233bc252faad8339e7ca0ddfd62fa79903c
Author: Jon Loeliger <jdl@freescale.com>
Date: Thu Nov 1 12:23:29 2007 -0500
86xx: Fix broken variable reference when #def DEBUGing.
Sometimes you can't reference the DDR2 controller variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
commit f9d9164d9c6b5a7f0393fd8d7e246b8a0326bc19
Author: Jason Jin <Jason.jin@freescale.com>
Date: Fri Oct 26 18:32:00 2007 +0800
make 8610 board use pixis reset
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit db74b3c1c9481a6bffbf8cd445e5bcbf6908e836
Author: Jason Jin <Jason.jin@freescale.com>
Date: Mon Oct 29 19:26:21 2007 +0800
Unify pixis_reset altbank across board families
Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
commit 64bf555465c7926be13e1046ac0d0f05ac72829c
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Wed Nov 7 08:19:21 2007 +0100
Fix warning: pointer targets in assignment differ in signedness
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 7a60ee7c6248a958c5757d3660a1702723a2786d
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Wed Nov 7 08:19:19 2007 +0100
Fix warning differ in signedness in common/cmd_ide.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 955413f35f054a82e40042f1dbcf501c6a05719b
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:27:52 2007 -0700
Revert "Correct relocation fixup for mpc5xx"
This reverts commit 3649cd99ba815b6601868735765602f00ef3692b.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit e15633888a058aacb31a62d2cf1278e1e4c236ab
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:24:32 2007 -0700
Revert "Correct fixup relocation for MPC5xxx"
This reverts commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 139365fbe566d0fc619a1ed04452ec5388f0cef8
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:21:04 2007 -0700
Revert "Correct fixup relocation for mpc8220"
This reverts commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 70922342369e5e39b286fe21e768a239ca07a514
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:20:57 2007 -0700
Revert "Correct fixup relocation for mpc824x"
This reverts commit f3a52fe05923935db86985daf9438e2f70ac39aa.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 96279ab4cad60cb5972aa934fbe4845ac02cc75a
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:20:50 2007 -0700
Revert "Correct fixup relocation for mpc8260"
This reverts commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 928fe33b24cdf382a8dc8687fed24b1961cdb5d6
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:20:43 2007 -0700
Revert "Correct fixup relocation for mpc83xx"
This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit c93945e8f9e300860d2bf73a2549ce5794f8bd00
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Thu Nov 15 08:20:25 2007 -0700
Revert "[MPC512x] Correct fixup relocation"
This reverts commit 8d17979d0359492a822a0a409d26e3a3549b4cd4.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 54fd6c93c28a0a45352fff5dd92673401ff563f2
Author: Stefan Roese <sr@denx.de>
Date: Tue Nov 13 08:18:20 2007 +0100
ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching
Signed-off-by: Stefan Roese <sr@denx.de>
commit 1ce55151c85d068f70317a8d65c61058b891afb4
Author: Heiko Schocher <hs@denx.de>
Date: Tue Nov 13 07:50:29 2007 +0100
[UC101] SRAM now with 2 MB working.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 8d737a28152ec12873f8544cca1fb39a49e5e693
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Thu Nov 8 12:50:18 2007 -0600
ColdFire: MCF5329 - Remove reset registers from CCM
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit 7d7cdea769a60b0a6e4c18bef7f9d648fd14b8d7
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Thu Nov 8 12:31:11 2007 -0600
ColdFire: MCF5329 - Add Reset structure to immap_5329.h
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit 09b26cf00d76d75fdf7fdc4b13e4dd929743bc21
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Thu Nov 8 12:19:01 2007 -0600
ColdFire: MCF5329 - revert include/asm-m68k/m5329.h file mode
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit 225a24b5e062ad94627424508ae814f51dbe1a34
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Wed Nov 7 18:00:54 2007 -0600
ColdFire: MCF5445x - Update correct RAMBAR and missing linker files
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit 248c7c14835f34d5d910b45e5600050e58ca6cab
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Wed Nov 7 17:56:15 2007 -0600
ColdFire: MCF532x - Update do_reset() using core reset
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit d9240a5f827eb3b476a6ba2938d01f1a9e7688f4
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Wed Nov 7 17:51:00 2007 -0600
ColdFire: Update cpu flag for 4.2-xx compiler
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
commit 1f103105a3746ab12279b63b8c1d372c0ce2cc58
Author: Roy Zang <tie-fei.zang@freescale.com>
Date: Mon Nov 5 17:39:24 2007 +0800
Implement general ULi 526x Ethernet driver support in U-boot
This patch implements general ULi 526x Ethernet driver.
Until now, it is the only native Ethernet port on
MPC8610HPCD board, but it could be used on other boards
with ULi 526x Ethernet port as well.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
commit 71bc6e6474fea8ef481b9b45d1edd7ad1f6dfbbd
Author: Larry Johnson <lrj@arlinx.com>
Date: Thu Nov 1 08:46:50 2007 -0500
NET: Add Ethernet 1000BASE-X support for PPC4xx
This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and
"miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which
returns non-zero iff the PHY registers are configured for 1000BASE-X. The
"mii info" command is modified to distinguish between 1000BASE-T and -X.
Signed-off-by: Larry Johnson <lrj@acm.org>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
commit 298035df4948b113d29ac0e694717d34b95bc5dc
Author: Larry Johnson <lrj@arlinx.com>
Date: Wed Oct 31 11:21:29 2007 -0500
NET: Cosmetic changes
Signed-off-by: Larry Johnson <lrj@acm.org>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
commit 992742a5b09d9040adbd156fb90756af66ade310
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Nov 3 23:09:27 2007 +0100
Cleanup coding style; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit e881cb563e32f45832b7b6db77bdcd017adcbb41
Author: Bruce Adler <bruce.adler@ccpu.com>
Date: Fri Nov 2 13:15:42 2007 -0700
@ -161,6 +455,26 @@ Date: Mon Oct 29 17:40:35 2007 -0400
Signed-off-by: Justin Flammia <jflammia@savantav.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
commit 31548249decf18a6b877a18436b6139dd483fe4a
Author: Justin Flammia <jflammia@savantav.com>
Date: Mon Oct 29 17:40:35 2007 -0400
DHCP Client Fix
This is a multi-part message in MIME format.
commit e6e505eae94ed721e123e177489291fc4544b7b8
Author: Justin Flammia <jflammia@savantav.com>
Date: Mon Oct 29 17:19:03 2007 -0400
Found a bug in the way the DHCP Request packet is built, where the IP address
that is offered by the server is bound to prematurely. This patch is a fix of
that bug where the IP address offered by the DHCP server is not used until
after the DHCP ACK from the server is received.
Signed-off-by: Justin Flammia <jflammia@savantav.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
commit e8ee8f3ade2a06c1893dd5e68f223070d650c7ed
Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Thu Oct 25 17:16:22 2007 -0500
@ -412,6 +726,14 @@ Date: Tue Oct 23 10:22:16 2007 +0100
Move PL01* serial drivers to drivers/serial and adjust Makefiles.
commit 20d500d531a6b971ce6cc1bf191cb0092cdc0afc
Author: Stefan Roese <sr@denx.de>
Date: Tue Oct 23 10:17:42 2007 +0200
ppc4xx: lwmon5: Some further GPIO config changes
Signed-off-by: Stefan Roese <sr@denx.de>
commit de9a738faa7c2f47286119c3bfebc3dfbfe7d86d
Author: Vlad Lungu <vlad@comsys.ro>
Date: Sun Oct 21 22:10:10 2007 +0900

2
Makefile
View File

@ -24,7 +24,7 @@
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 0
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h

4
board/dbau1x00/dbau1x00.c
View File

@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
{
@ -77,6 +78,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#ifdef CONFIG_IDE_PCMCIA
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */

5
board/freescale/common/pixis.c
View File

@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK 0x40
#endif
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp ^= 0x40;
tmp ^= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}

144
board/freescale/m54455evb/u-boot.atm Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

141
board/freescale/m54455evb/u-boot.int Normal file
View File

@ -0,0 +1,141 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5445x/start.o (.text)
lib_m68k/traps.o (.text)
lib_m68k/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

6
board/gth2/gth2.c
View File

@ -26,14 +26,13 @@
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
unsigned long mips_io_port_base = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
@ -147,6 +146,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */

5
board/incaip/incaip.c
View File

@ -25,7 +25,7 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h>
extern uint incaip_get_cpuclk(void);
@ -85,7 +85,6 @@ long int initdram(int board_type)
int checkboard (void)
{
unsigned long chipid = *INCA_IP_WDT_CHIPID;
int part_num;
@ -107,5 +106,7 @@ int checkboard (void)
printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
set_io_port_base(0);
return 0;
}

26
board/lwmon5/lwmon5.c
View File

@ -96,6 +96,23 @@ int board_early_init_f(void)
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
/*
* Reset PHY's:
* The PHY's need a 2nd reset pulse, since the MDIO address is latched
* upon reset, and with the first reset upon powerup, the addresses are
* not latched reliable, since the IRQ line is multiplexed with an
* MDIO address. A 2nd reset at this time will make sure, that the
* correct address is latched.
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(1000);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
return 0;
}
@ -230,15 +247,6 @@ int misc_init_r(void)
/* Write lime controller memory parameters */
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
* Reset PHY's
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
/*
* Init display controller
*/

4
board/pb1x00/pb1x00.c
View File

@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
{
@ -69,6 +70,9 @@ int checkboard (void)
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
set_io_port_base(0);
#if defined(CONFIG_IDE_PCMCIA) && 0
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */

2
board/purple/flash.c
View File

@ -299,7 +299,7 @@ void flash_print_info (flash_info_t *info)
int i;
uchar *boottype;
uchar *bootletter;
uchar *fmt;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";

3
board/purple/purple.c
View File

@ -26,6 +26,7 @@
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
@ -145,6 +146,8 @@ int checkboard (void)
printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
set_io_port_base(0);
return 0;
}

4
board/rsdproto/rsdproto.c
View File

@ -210,7 +210,7 @@ void read_RS5C372_time (struct tm *timedate)
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
timedate->tm_sec = BCD_TO_BIN (buffer[0]);
timedate->tm_min = BCD_TO_BIN (buffer[1]);
timedate->tm_hour = BCD_TO_BIN (buffer[2]);
@ -231,7 +231,7 @@ int read_LM84_temp (int address)
unsigned char buffer[8];
/*int rc;*/
if (i2c_read (address, 0, 1, buffer, 1)) {
if (! i2c_read (address, 0, 1, buffer, 1)) {
return (int) buffer[0];
} else {
/*printf("i2c error %02x\n", rc); */

7
board/tb0229/tb0229.c
View File

@ -13,10 +13,9 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h>
#include <pci.h>
unsigned long mips_io_port_base = 0;
#if defined(CONFIG_PCI)
static struct pci_controller hose;
@ -26,17 +25,17 @@ void pci_init_board (void)
}
#endif
long int initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
set_io_port_base(0);
return 0;
}

16
common/cmd_ide.c
View File

@ -54,10 +54,6 @@
#ifndef __PPC__
#include <asm/io.h>
#ifdef __MIPS__
/* Macros depend on this variable */
unsigned long mips_io_port_base = 0;
#endif
#endif
#ifdef CONFIG_IDE_8xx_DIRECT
@ -1136,9 +1132,9 @@ static void ide_ident (block_dev_desc_t *dev_desc)
input_swap_data (device, iobuf, ATA_SECTORWORDS);
ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
ident_cpy ((unsigned char*)dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
ident_cpy ((unsigned char*)dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
ident_cpy ((unsigned char*)dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
#ifdef __LITTLE_ENDIAN
/*
* firmware revision and model number have Big Endian Byte
@ -1953,9 +1949,9 @@ static void atapi_inquiry(block_dev_desc_t * dev_desc)
return;
/* copy device ident strings */
ident_cpy(dev_desc->vendor,&iobuf[8],8);
ident_cpy(dev_desc->product,&iobuf[16],16);
ident_cpy(dev_desc->revision,&iobuf[32],5);
ident_cpy((unsigned char*)dev_desc->vendor,&iobuf[8],8);
ident_cpy((unsigned char*)dev_desc->product,&iobuf[16],16);
ident_cpy((unsigned char*)dev_desc->revision,&iobuf[32],5);
dev_desc->lun=0;
dev_desc->lba=0;

8
common/cmd_mii.c
View File

@ -112,9 +112,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
"%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
miiphy_is_1000base_x (devname, j)
? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}
@ -496,9 +498,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
"%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
miiphy_is_1000base_x (devname, j)
? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}

282
common/miiphyutil.c
View File

@ -49,10 +49,10 @@
struct mii_dev {
struct list_head link;
char *name;
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
};
static struct list_head mii_devs;
@ -62,21 +62,21 @@ static struct mii_dev *current_mii;
*
* Initialize global data. Need to be called before any other miiphy routine.
*/
void miiphy_init()
void miiphy_init ()
{
INIT_LIST_HEAD(&mii_devs);
current_mii = NULL;
INIT_LIST_HEAD (&mii_devs);
current_mii = NULL;
}
/*****************************************************************************
*
* Register read and write MII access routines for the device <name>.
*/
void miiphy_register(char *name,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value))
void miiphy_register (char *name,
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value))
{
struct list_head *entry;
struct mii_dev *new_dev;
@ -84,63 +84,64 @@ void miiphy_register(char *name,
unsigned int name_len;
/* check if we have unique name */
list_for_each(entry, &mii_devs) {
miidev = list_entry(entry, struct mii_dev, link);
if (strcmp(miidev->name, name) == 0) {
printf("miiphy_register: non unique device name '%s'\n",
name);
list_for_each (entry, &mii_devs) {
miidev = list_entry (entry, struct mii_dev, link);
if (strcmp (miidev->name, name) == 0) {
printf ("miiphy_register: non unique device name "
"'%s'\n", name);
return;
}
}
/* allocate memory */
name_len = strlen(name);
new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
name_len = strlen (name);
new_dev =
(struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
if(new_dev == NULL) {
printf("miiphy_register: cannot allocate memory for '%s'\n",
name);
if (new_dev == NULL) {
printf ("miiphy_register: cannot allocate memory for '%s'\n",
name);
return;
}
memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
/* initalize mii_dev struct fields */
INIT_LIST_HEAD(&new_dev->link);
INIT_LIST_HEAD (&new_dev->link);
new_dev->read = read;
new_dev->write = write;
new_dev->name = (char *)(new_dev + 1);
strncpy(new_dev->name, name, name_len);
strncpy (new_dev->name, name, name_len);
new_dev->name[name_len] = '\0';
debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
new_dev->name, new_dev->read, new_dev->write);
debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
new_dev->name, new_dev->read, new_dev->write);
/* add it to the list */
list_add_tail(&new_dev->link, &mii_devs);
list_add_tail (&new_dev->link, &mii_devs);
if (!current_mii)
current_mii = new_dev;
}
int miiphy_set_current_dev(char *devname)
int miiphy_set_current_dev (char *devname)
{
struct list_head *entry;
struct mii_dev *dev;
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
current_mii = dev;
return 0;
}
}
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return 1;
}
char *miiphy_get_current_dev()
char *miiphy_get_current_dev ()
{
if (current_mii)
return current_mii->name;
@ -156,8 +157,8 @@ char *miiphy_get_current_dev()
* Returns:
* 0 on success
*/
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
struct list_head *entry;
struct mii_dev *dev;
@ -165,22 +166,22 @@ int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
int read_ret = 0;
if (!devname) {
printf("NULL device name!\n");
printf ("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
read_ret = dev->read(devname, addr, reg, value);
read_ret = dev->read (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return ((found_dev) ? read_ret : 1);
}
@ -193,8 +194,8 @@ int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
* Returns:
* 0 on success
*/
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
struct list_head *entry;
struct mii_dev *dev;
@ -202,22 +203,22 @@ int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
int write_ret = 0;
if (!devname) {
printf("NULL device name!\n");
printf ("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
if (strcmp (devname, dev->name) == 0) {
found_dev = 1;
write_ret = dev->write(devname, addr, reg, value);
write_ret = dev->write (devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
printf ("No such device: %s\n", devname);
return ((found_dev) ? write_ret : 1);
}
@ -226,23 +227,22 @@ int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
*
* Print out list of registered MII capable devices.
*/
void miiphy_listdev(void)
void miiphy_listdev (void)
{
struct list_head *entry;
struct mii_dev *dev;
puts("MII devices: ");
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
printf("'%s' ", dev->name);
puts ("MII devices: ");
list_for_each (entry, &mii_devs) {
dev = list_entry (entry, struct mii_dev, link);
printf ("'%s' ", dev->name);
}
puts("\n");
puts ("\n");
if (current_mii)
printf("Current device: '%s'\n", current_mii->name);
printf ("Current device: '%s'\n", current_mii->name);
}
/*****************************************************************************
*
* Read the OUI, manufacture's model number, and revision number.
@ -254,9 +254,7 @@ void miiphy_listdev(void)
* Returns:
* 0 on success
*/
int miiphy_info (char *devname,
unsigned char addr,
unsigned int *oui,
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev)
{
unsigned int reg = 0;
@ -288,13 +286,12 @@ int miiphy_info (char *devname,
#ifdef DEBUG
printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
#endif
*oui = ( reg >> 10);
*model = (unsigned char) ((reg >> 4) & 0x0000003F);
*rev = (unsigned char) ( reg & 0x0000000F);
*oui = (reg >> 10);
*model = (unsigned char)((reg >> 4) & 0x0000003F);
*rev = (unsigned char)(reg & 0x0000000F);
return (0);
}
/*****************************************************************************
*
* Reset the PHY.
@ -345,104 +342,138 @@ int miiphy_reset (char *devname, unsigned char addr)
return (0);
}
/*****************************************************************************
*
* Determine the ethernet speed (10/100).
* Determine the ethernet speed (10/100/1000). Return 10 on error.
*/
int miiphy_speed (char *devname, unsigned char addr)
{
unsigned short reg;
u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if (reg != 0xFFFF) {
if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
return (_1000BASET);
}
}
u16 btsr;
/*
* Check for 1000BASE-X. If it is supported, then assume that the speed
* is 1000.
*/
if (miiphy_is_1000base_x (devname, addr)) {
return _1000BASET;
}
/*
* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
*/
/* Check for 1000BASE-T. */
if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
printf ("PHY 1000BT status");
goto miiphy_read_failed;
}
if (btsr != 0xFFFF &&
(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
return _1000BASET;
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY speed read failed, assuming 10bT\n");
return (_10BASET);
if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
printf ("PHY speed");
goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN speed read failed, assuming 10bT\n");
return (_10BASET);
}
if ((reg & PHY_ANLPAR_100) != 0) {
return (_100BASET);
} else {
return (_10BASET);
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
printf ("PHY AN speed");
goto miiphy_read_failed;
}
return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
}
/* Get speed from basic control settings. */
else if (reg & PHY_BMCR_100MB) {
return (_100BASET);
} else {
return (_10BASET);
}
return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
miiphy_read_failed:
printf (" read failed, assuming 10BASE-T\n");
return _10BASET;
}
/*****************************************************************************
*
* Determine full/half duplex.
* Determine full/half duplex. Return half on error.
*/
int miiphy_duplex (char *devname, unsigned char addr)
{
unsigned short reg;
u16 bmcr, anlpar;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if ( (reg != 0xFFFF) &&
(reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
if ((reg & PHY_1000BTSR_1000FD) !=0) {
return (FULL);
} else {
return (HALF);
}
u16 btsr;
/* Check for 1000BASE-X. */
if (miiphy_is_1000base_x (devname, addr)) {
/* 1000BASE-X */
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
printf ("1000BASE-X PHY AN duplex");
goto miiphy_read_failed;
}
}
/*
* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
*/
/* Check for 1000BASE-T. */
if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
printf ("PHY 1000BT status");
goto miiphy_read_failed;
}
if (btsr != 0xFFFF) {
if (btsr & PHY_1000BTSR_1000FD) {
return FULL;
} else if (btsr & PHY_1000BTSR_1000HD) {
return HALF;
}
}
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY duplex read failed, assuming half duplex\n");
return (HALF);
if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
puts ("PHY duplex");
goto miiphy_read_failed;
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
if (bmcr & PHY_BMCR_AUTON) {
/* Get auto-negotiation results. */
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN duplex read failed, assuming half duplex\n");
return (HALF);
}
if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
return (FULL);
} else {
return (HALF);
if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
puts ("PHY AN duplex");
goto miiphy_read_failed;
}
return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
FULL : HALF;
}
/* Get speed from basic control settings. */
else if (reg & PHY_BMCR_DPLX) {
return (FULL);
} else {
return (HALF);
}
return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
miiphy_read_failed:
printf (" read failed, assuming half duplex\n");
return HALF;
}
/*****************************************************************************
*
* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
* 1000BASE-T, or on error.
*/
int miiphy_is_1000base_x (char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
u16 exsr;
if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
printf ("PHY extended status read failed, assuming no "
"1000BASE-X\n");
return 0;
}
return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
#else
return 0;
#endif
}
#ifdef CFG_FAULT_ECHO_LINK_DOWN
@ -455,7 +486,7 @@ int miiphy_link (char *devname, unsigned char addr)
unsigned short reg;
/* dummy read; needed to latch some phys */
(void)miiphy_read(devname, addr, PHY_BMSR, &reg);
(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
puts ("PHY_BMSR read failed, assuming no link\n");
return (0);
@ -469,5 +500,4 @@ int miiphy_link (char *devname, unsigned char addr)
}
}
#endif
#endif /* CONFIG_MII */

2
common/spartan2.c
View File

@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val < 0), TRUE, cookie);
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);

2
common/spartan3.c
View File

@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val < 0), TRUE, cookie);
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);

4
cpu/mcf523x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif

29
cpu/mcf52x2/config.mk
View File

@ -24,4 +24,33 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is5249=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
is5282=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
ifneq (,$(findstring CONFIG_M5249,$(is5249)))
PLATFORM_CPPFLAGS += -mcpu=5249
endif
ifneq (,$(findstring CONFIG_M5253,$(is5253)))
PLATFORM_CPPFLAGS += -mcpu=5253
endif
ifneq (,$(findstring CONFIG_M5271,$(is5271)))
PLATFORM_CPPFLAGS += -mcpu=5271
endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
else
PLATFORM_CPPFLAGS += -m5307
endif

4
cpu/mcf532x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif

8
cpu/mcf532x/cpu.c
View File

@ -35,14 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
wdp->cr = 0;
udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
wdp->cr = WTM_WCR_EN;
while (1) ;
rcm->rcr |= RCM_RCR_SOFTRST;
/* we don't return! */
return 0;

4
cpu/mcf5445x/config.mk
View File

@ -24,4 +24,8 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
else
PLATFORM_CPPFLAGS += -m5407 -fPIC
endif

2
cpu/mcf5445x/start.S
View File

@ -136,7 +136,7 @@ _start:
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l #0, %d0

4
cpu/mpc86xx/cpu.c
View File

@ -120,7 +120,7 @@ checkcpu(void)
static inline void
soft_restart(unsigned long addr)
{
#ifndef CONFIG_MPC8641HPCN
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
/*
* SRR0 has system reset vector, SRR1 has default MSR value
@ -148,7 +148,7 @@ soft_restart(unsigned long addr)
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifndef CONFIG_MPC8641HPCN
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
#ifdef CFG_RESET_ADDRESS
ulong addr = CFG_RESET_ADDRESS;

6
cpu/mpc86xx/spd_sdram.c
View File

@ -1270,10 +1270,12 @@ spd_sdram(void)
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
}
debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
memsize_ddr1, memsize_ddr2);
debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
/*
* If neither DDR controller is enabled return 0.

1
drivers/Makefile
View File

@ -108,6 +108,7 @@ COBJS-y += smc91111.o
COBJS-y += tigon3.o
COBJS-y += tsec.o
COBJS-y += tsi108_eth.o
COBJS-y += uli526x.o
#
# PCI/PCMCIA device drivers

996
drivers/uli526x.c Normal file
View File

@ -0,0 +1,996 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
*
* Description:
* ULI 526x Ethernet port driver.
* Based on the Linux driver: drivers/net/tulip/uli526x.c
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
/* some kernel function compatible define */
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_ULI526X)
#undef DEBUG
/* Board/System/Debug information/definition */
#define ULI_VENDOR_ID 0x10B9
#define ULI5261_DEVICE_ID 0x5261
#define ULI5263_DEVICE_ID 0x5263
/* ULi M5261 ID*/
#define PCI_ULI5261_ID ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID
/* ULi M5263 ID*/
#define PCI_ULI5263_ID ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID
#define ULI526X_IO_SIZE 0x100
#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
#define TX_BUF_ALLOC 0x300
#define RX_ALLOC_SIZE PKTSIZE
#define ULI526X_RESET 1
#define CR0_DEFAULT 0
#define CR6_DEFAULT 0x22200000
#define CR7_DEFAULT 0x180c1
#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
#define MAX_PACKET_SIZE 1514
#define ULI5261_MAX_MULTICAST 14
#define RX_COPY_SIZE 100
#define MAX_CHECK_PACKET 0x8000
#define ULI526X_10MHF 0
#define ULI526X_100MHF 1
#define ULI526X_10MFD 4
#define ULI526X_100MFD 5
#define ULI526X_AUTO 8
#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
/* CR9 definition: SROM/MII */
#define CR9_SROM_READ 0x4800
#define CR9_SRCS 0x1
#define CR9_SRCLK 0x2
#define CR9_CRDOUT 0x8
#define SROM_DATA_0 0x0
#define SROM_DATA_1 0x4
#define PHY_DATA_1 0x20000
#define PHY_DATA_0 0x00000
#define MDCLKH 0x10000
#define PHY_POWER_DOWN 0x800
#define SROM_V41_CODE 0x14
#define SROM_CLK_WRITE(data, ioaddr) do { \
outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
udelay(5); \
outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
udelay(5); \
outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
udelay(5); \
} while (0)
/* Structure/enum declaration */
struct tx_desc {
u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
char *tx_buf_ptr; /* Data for us */
struct tx_desc *next_tx_desc;
};
struct rx_desc {
u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
char *rx_buf_ptr; /* Data for us */
struct rx_desc *next_rx_desc;
};
struct uli526x_board_info {
u32 chip_id; /* Chip vendor/Device ID */
pci_dev_t pdev;
long ioaddr; /* I/O base address */
u32 cr0_data;
u32 cr5_data;
u32 cr6_data;
u32 cr7_data;
u32 cr15_data;
/* pointer for memory physical address */
dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
dma_addr_t first_tx_desc_dma;
dma_addr_t first_rx_desc_dma;
/* descriptor pointer */
unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
unsigned char *buf_pool_start; /* Tx buffer pool align dword */
unsigned char *desc_pool_ptr; /* descriptor pool memory */
struct tx_desc *first_tx_desc;
struct tx_desc *tx_insert_ptr;
struct tx_desc *tx_remove_ptr;
struct rx_desc *first_rx_desc;
struct rx_desc *rx_ready_ptr; /* packet come pointer */
unsigned long tx_packet_cnt; /* transmitted packet count */
u16 PHY_reg4; /* Saved Phyxcer register 4 value */
u8 media_mode; /* user specify media mode */
u8 op_mode; /* real work dedia mode */
u8 phy_addr;
/* NIC SROM data */
unsigned char srom[128];
};
enum uli526x_offsets {
DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
DCR15 = 0x78
};
enum uli526x_CR6_bits {
CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
};
/* Global variable declaration -- */
static unsigned char uli526x_media_mode = ULI526X_AUTO;
static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
__attribute__ ((aligned(32)));
static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
/* For module input parameter */
static int mode = 8;
/* function declaration -- */
static int uli526x_start_xmit(struct eth_device *dev,
volatile void *packet, int length);
static const struct ethtool_ops netdev_ethtool_ops;
static u16 read_srom_word(long, int);
static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
static void allocate_rx_buffer(struct uli526x_board_info *);
static void update_cr6(u32, unsigned long);
static u16 phy_read(unsigned long, u8, u8, u32);
static u16 phy_readby_cr10(unsigned long, u8, u8);
static void phy_write(unsigned long, u8, u8, u16, u32);
static void phy_writeby_cr10(unsigned long, u8, u8, u16);
static void phy_write_1bit(unsigned long, u32, u32);
static u16 phy_read_1bit(unsigned long, u32);
static int uli526x_rx_packet(struct eth_device *);
static void uli526x_free_tx_pkt(struct eth_device *,
struct uli526x_board_info *);
static void uli526x_reuse_buf(struct rx_desc *);
static void uli526x_init(struct eth_device *);
static void uli526x_set_phyxcer(struct uli526x_board_info *);
static int uli526x_init_one(struct eth_device *, bd_t *);
static void uli526x_disable(struct eth_device *);
static void set_mac_addr(struct eth_device *);
static struct pci_device_id uli526x_pci_tbl[] = {
{ ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
{ ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
{}
};
/* ULI526X network board routine */
/*
* Search ULI526X board, register it
*/
int uli526x_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
struct uli526x_board_info *db; /* board information structure */
u32 iobase;
int idx = 0;
while (1) {
/* Find PCI device */
devno = pci_find_devices(uli526x_pci_tbl, idx++);
if (devno < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
dev = (struct eth_device *)malloc(sizeof *dev);
sprintf(dev->name, "uli526x#%d\n", card_number);
db = (struct uli526x_board_info *)
malloc(sizeof(struct uli526x_board_info));
dev->priv = db;
db->pdev = devno;
dev->iobase = iobase;
dev->init = uli526x_init_one;
dev->halt = uli526x_disable;
dev->send = uli526x_start_xmit;
dev->recv = uli526x_rx_packet;
/* init db */
db->ioaddr = dev->iobase;
/* get chip id */
pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
#ifdef DEBUG
printf("uli526x: uli526x @0x%x\n", iobase);
printf("uli526x: chip_id%x\n", db->chip_id);
#endif
eth_register(dev);
card_number++;
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
udelay(10 * 1000);
}
return card_number;
}
static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
{
struct uli526x_board_info *db = dev->priv;
int i;
switch (mode) {
case ULI526X_10MHF:
case ULI526X_100MHF:
case ULI526X_10MFD:
case ULI526X_100MFD:
uli526x_media_mode = mode;
break;
default:
uli526x_media_mode = ULI526X_AUTO;
break;
}
/* Allocate Tx/Rx descriptor memory */
db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
if (db->desc_pool_ptr == NULL)
return 0;
db->buf_pool_ptr = &buf_pool[0];
db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
if (db->buf_pool_ptr == NULL)
return 0;
db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
db->first_tx_desc_dma = db->desc_pool_dma_ptr;
db->buf_pool_start = db->buf_pool_ptr;
db->buf_pool_dma_start = db->buf_pool_dma_ptr;
#ifdef DEBUG
printf("%s(): db->ioaddr= 0x%x\n",
__FUNCTION__, db->ioaddr);
printf("%s(): media_mode= 0x%x\n",
__FUNCTION__, uli526x_media_mode);
printf("%s(): db->desc_pool_ptr= 0x%x\n",
__FUNCTION__, db->desc_pool_ptr);
printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
__FUNCTION__, db->desc_pool_dma_ptr);
printf("%s(): db->buf_pool_ptr= 0x%x\n",
__FUNCTION__, db->buf_pool_ptr);
printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
__FUNCTION__, db->buf_pool_dma_ptr);
#endif
/* read 64 word srom data */
for (i = 0; i < 64; i++)
((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
i));
/* Set Node address */
if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
/* SROM absent, so write MAC address to ID Table */
set_mac_addr(dev);
else { /*Exist SROM*/
for (i = 0; i < 6; i++)
dev->enetaddr[i] = db->srom[20 + i];
}
#ifdef DEBUG
for (i = 0; i < 6; i++)
printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
#endif
db->PHY_reg4 = 0x1e0;
/* system variable init */
db->cr6_data = CR6_DEFAULT ;
db->cr6_data |= ULI526X_TXTH_256;
db->cr0_data = CR0_DEFAULT;
uli526x_init(dev);
return 1;
}
static void uli526x_disable(struct eth_device *dev)
{
#ifdef DEBUG
printf("uli526x_disable\n");
#endif
struct uli526x_board_info *db = dev->priv;
if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
/* Reset & stop ULI526X board */
outl(ULI526X_RESET, db->ioaddr + DCR0);
udelay(5);
phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
/* reset the board */
db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
update_cr6(db->cr6_data, dev->iobase);
outl(0, dev->iobase + DCR7); /* Disable Interrupt */
outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
}
}
/* Initialize ULI526X board
* Reset ULI526X board
* Initialize TX/Rx descriptor chain structure
* Send the set-up frame
* Enable Tx/Rx machine
*/
static void uli526x_init(struct eth_device *dev)
{
struct uli526x_board_info *db = dev->priv;
u8 phy_tmp;
u16 phy_value;
u16 phy_reg_reset;
/* Reset M526x MAC controller */
outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
udelay(100);
outl(db->cr0_data, db->ioaddr + DCR0);
udelay(5);
/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
db->phy_addr = 1;
db->tx_packet_cnt = 0;
for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
/* peer add */
phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
if (phy_value != 0xffff && phy_value != 0) {
db->phy_addr = phy_tmp;
break;
}
}
#ifdef DEBUG
printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
#endif
if (phy_tmp == 32)
printf("Can not find the phy address!!!");
/* Parser SROM and media mode */
db->media_mode = uli526x_media_mode;
if (!(inl(db->ioaddr + DCR12) & 0x8)) {
/* Phyxcer capability setting */
phy_reg_reset = phy_read(db->ioaddr,
db->phy_addr, 0, db->chip_id);
phy_reg_reset = (phy_reg_reset | 0x8000);
phy_write(db->ioaddr, db->phy_addr, 0,
phy_reg_reset, db->chip_id);
udelay(500);
/* Process Phyxcer Media Mode */
uli526x_set_phyxcer(db);
}
/* Media Mode Process */
if (!(db->media_mode & ULI526X_AUTO))
db->op_mode = db->media_mode; /* Force Mode */
/* Initialize Transmit/Receive decriptor and CR3/4 */
uli526x_descriptor_init(db, db->ioaddr);
/* Init CR6 to program M526X operation */
update_cr6(db->cr6_data, db->ioaddr);
/* Init CR7, interrupt active bit */
db->cr7_data = CR7_DEFAULT;
outl(db->cr7_data, db->ioaddr + DCR7);
/* Init CR15, Tx jabber and Rx watchdog timer */
outl(db->cr15_data, db->ioaddr + DCR15);
/* Enable ULI526X Tx/Rx function */
db->cr6_data |= CR6_RXSC | CR6_TXSC;
update_cr6(db->cr6_data, db->ioaddr);
while (!(inl(db->ioaddr + DCR12) & 0x8))
udelay(10);
}
/*
* Hardware start transmission.
* Send a packet to media from the upper layer.
*/
static int uli526x_start_xmit(struct eth_device *dev,
volatile void *packet, int length)
{
struct uli526x_board_info *db = dev->priv;
struct tx_desc *txptr;
unsigned int len = length;
/* Too large packet check */
if (len > MAX_PACKET_SIZE) {
printf(": big packet = %d\n", len);
return 0;
}
/* No Tx resource check, it never happen nromally */
if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
printf("No Tx resource %ld\n", db->tx_packet_cnt);
return 0;
}
/* Disable NIC interrupt */
outl(0, dev->iobase + DCR7);
/* transmit this packet */
txptr = db->tx_insert_ptr;
memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
/* Point to next transmit free descriptor */
db->tx_insert_ptr = txptr->next_tx_desc;
/* Transmit Packet Process */
if ((db->tx_packet_cnt < TX_DESC_CNT)) {
txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
db->tx_packet_cnt++; /* Ready to send */
outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
}
/* Got ULI526X status */
db->cr5_data = inl(db->ioaddr + DCR5);
outl(db->cr5_data, db->ioaddr + DCR5);
#ifdef TX_DEBUG
printf("%s(): length = 0x%x\n", __FUNCTION__, length);
printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
#endif
outl(db->cr7_data, dev->iobase + DCR7);
uli526x_free_tx_pkt(dev, db);
return length;
}
/*
* Free TX resource after TX complete
*/
static void uli526x_free_tx_pkt(struct eth_device *dev,
struct uli526x_board_info *db)
{
struct tx_desc *txptr;
u32 tdes0;
txptr = db->tx_remove_ptr;
while (db->tx_packet_cnt) {
tdes0 = le32_to_cpu(txptr->tdes0);
/* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
if (tdes0 & 0x80000000)
break;
/* A packet sent completed */
db->tx_packet_cnt--;
if (tdes0 != 0x7fffffff) {
#ifdef TX_DEBUG
printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
#endif
if (tdes0 & TDES0_ERR_MASK) {
if (tdes0 & 0x0002) { /* UnderRun */
if (!(db->cr6_data & CR6_SFT)) {
db->cr6_data = db->cr6_data |
CR6_SFT;
update_cr6(db->cr6_data,
db->ioaddr);
}
}
}
}
txptr = txptr->next_tx_desc;
}/* End of while */
/* Update TX remove pointer to next */
db->tx_remove_ptr = txptr;
}
/*
* Receive the come packet and pass to upper layer
*/
static int uli526x_rx_packet(struct eth_device *dev)
{
struct uli526x_board_info *db = dev->priv;
struct rx_desc *rxptr;
int rxlen = 0;
u32 rdes0;
rxptr = db->rx_ready_ptr;
rdes0 = le32_to_cpu(rxptr->rdes0);
#ifdef RX_DEBUG
printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
#endif
if (!(rdes0 & 0x80000000)) { /* packet owner check */
if ((rdes0 & 0x300) != 0x300) {
/* A packet without First/Last flag */
/* reuse this buf */
printf("A packet without First/Last flag");
uli526x_reuse_buf(rxptr);
} else {
/* A packet with First/Last flag */
rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
#ifdef RX_DEBUG
printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
#endif
/* error summary bit check */
if (rdes0 & 0x8000) {
/* This is a error packet */
printf("Eroor: rdes0: %lx\n", rdes0);
}
if (!(rdes0 & 0x8000) ||
((db->cr6_data & CR6_PM) && (rxlen > 6))) {
#ifdef RX_DEBUG
printf("%s(): rx_skb_ptr =%x\n",
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rxlen =%x\n",
__FUNCTION__, rxlen);
printf("%s(): buf addr =%x\n",
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rxlen =%x\n",
__FUNCTION__, rxlen);
int i;
for (i = 0; i < 0x20; i++)
printf("%s(): data[%x] =%x\n",
__FUNCTION__, i, rxptr->rx_buf_ptr[i]);
#endif
NetReceive(rxptr->rx_buf_ptr, rxlen);
uli526x_reuse_buf(rxptr);
} else {
/* Reuse SKB buffer when the packet is error */
printf("Reuse buffer, rdes0");
uli526x_reuse_buf(rxptr);
}
}
rxptr = rxptr->next_rx_desc;
}
db->rx_ready_ptr = rxptr;
return rxlen;
}
/*
* Reuse the RX buffer
*/
static void uli526x_reuse_buf(struct rx_desc *rxptr)
{
if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
rxptr->rdes0 = cpu_to_le32(0x80000000);
else
printf("Buffer reuse method error");
}
/*
* Initialize transmit/Receive descriptor
* Using Chain structure, and allocate Tx/Rx buffer
*/
static void uli526x_descriptor_init(struct uli526x_board_info *db,
unsigned long ioaddr)
{
struct tx_desc *tmp_tx;
struct rx_desc *tmp_rx;
unsigned char *tmp_buf;
dma_addr_t tmp_tx_dma, tmp_rx_dma;
dma_addr_t tmp_buf_dma;
int i;
/* tx descriptor start pointer */
db->tx_insert_ptr = db->first_tx_desc;
db->tx_remove_ptr = db->first_tx_desc;
outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
/* rx descriptor start pointer */
db->first_rx_desc = (void *)db->first_tx_desc +
sizeof(struct tx_desc) * TX_DESC_CNT;
db->first_rx_desc_dma = db->first_tx_desc_dma +
sizeof(struct tx_desc) * TX_DESC_CNT;
db->rx_ready_ptr = db->first_rx_desc;
outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
#ifdef DEBUG
printf("%s(): db->first_tx_desc= 0x%x\n",
__FUNCTION__, db->first_tx_desc);
printf("%s(): db->first_rx_desc_dma= 0x%x\n",
__FUNCTION__, db->first_rx_desc_dma);
#endif
/* Init Transmit chain */
tmp_buf = db->buf_pool_start;
tmp_buf_dma = db->buf_pool_dma_start;
tmp_tx_dma = db->first_tx_desc_dma;
for (tmp_tx = db->first_tx_desc, i = 0;
i < TX_DESC_CNT; i++, tmp_tx++) {
tmp_tx->tx_buf_ptr = tmp_buf;
tmp_tx->tdes0 = cpu_to_le32(0);
tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
tmp_tx_dma += sizeof(struct tx_desc);
tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
tmp_tx->next_tx_desc = tmp_tx + 1;
tmp_buf = tmp_buf + TX_BUF_ALLOC;
tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
}
(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
tmp_tx->next_tx_desc = db->first_tx_desc;
/* Init Receive descriptor chain */
tmp_rx_dma = db->first_rx_desc_dma;
for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
i++, tmp_rx++) {
tmp_rx->rdes0 = cpu_to_le32(0);
tmp_rx->rdes1 = cpu_to_le32(0x01000600);
tmp_rx_dma += sizeof(struct rx_desc);
tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
tmp_rx->next_rx_desc = tmp_rx + 1;
}
(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
tmp_rx->next_rx_desc = db->first_rx_desc;
/* pre-allocate Rx buffer */
allocate_rx_buffer(db);
}
/*
* Update CR6 value
* Firstly stop ULI526X, then written value and start
*/
static void update_cr6(u32 cr6_data, unsigned long ioaddr)
{
outl(cr6_data, ioaddr + DCR6);
udelay(5);
}
/*
* Allocate rx buffer,
*/
static void allocate_rx_buffer(struct uli526x_board_info *db)
{
int index;
struct rx_desc *rxptr;
rxptr = db->first_rx_desc;
u32 addr;
for (index = 0; index < RX_DESC_CNT; index++) {
addr = (u32)NetRxPackets[index];
addr += (16 - (addr & 15));
rxptr->rx_buf_ptr = (char *) addr;
rxptr->rdes2 = cpu_to_le32(addr);
rxptr->rdes0 = cpu_to_le32(0x80000000);
#ifdef DEBUG
printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
printf("%s(): rxptr buf address = 0x%x\n", \
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
#endif
rxptr = rxptr->next_rx_desc;
}
}
/*
* Read one word data from the serial ROM
*/
static u16 read_srom_word(long ioaddr, int offset)
{
int i;
u16 srom_data = 0;
long cr9_ioaddr = ioaddr + DCR9;
outl(CR9_SROM_READ, cr9_ioaddr);
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
/* Send the Read Command 110b */
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
/* Send the offset */
for (i = 5; i >= 0; i--) {
srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
SROM_CLK_WRITE(srom_data, cr9_ioaddr);
}
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
for (i = 16; i > 0; i--) {
outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
udelay(5);
srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
? 1 : 0);
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
udelay(5);
}
outl(CR9_SROM_READ, cr9_ioaddr);
return srom_data;
}
/*
* Set 10/100 phyxcer capability
* AUTO mode : phyxcer register4 is NIC capability
* Force mode: phyxcer register4 is the force media
*/
static void uli526x_set_phyxcer(struct uli526x_board_info *db)
{
u16 phy_reg;
/* Phyxcer capability setting */
phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
if (db->media_mode & ULI526X_AUTO) {
/* AUTO Mode */
phy_reg |= db->PHY_reg4;
} else {
/* Force Mode */
switch (db->media_mode) {
case ULI526X_10MHF: phy_reg |= 0x20; break;
case ULI526X_10MFD: phy_reg |= 0x40; break;
case ULI526X_100MHF: phy_reg |= 0x80; break;
case ULI526X_100MFD: phy_reg |= 0x100; break;
}
}
/* Write new capability to Phyxcer Reg4 */
if (!(phy_reg & 0x01e0)) {
phy_reg |= db->PHY_reg4;
db->media_mode |= ULI526X_AUTO;
}
phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
/* Restart Auto-Negotiation */
phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
udelay(50);
}
/*
* Write a word to Phy register
*/
static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
u16 phy_data, u32 chip_id)
{
u16 i;
unsigned long ioaddr;
if (chip_id == PCI_ULI5263_ID) {
phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
return;
}
/* M5261/M5263 Chip */
ioaddr = iobase + DCR9;
/* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send write command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* written trasnition */
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
/* Write a word data to PHY controller */
for (i = 0x8000; i > 0; i >>= 1)
phy_write_1bit(ioaddr, phy_data & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
}
/*
* Read a word data from phy register
*/
static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
{
int i;
u16 phy_data;
unsigned long ioaddr;
if (chip_id == PCI_ULI5263_ID)
return phy_readby_cr10(iobase, phy_addr, offset);
/* M5261/M5263 Chip */
ioaddr = iobase + DCR9;
/* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send read command(10) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
/* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Skip transition state */
phy_read_1bit(ioaddr, chip_id);
/* read 16bit data */
for (phy_data = 0, i = 0; i < 16; i++) {
phy_data <<= 1;
phy_data |= phy_read_1bit(ioaddr, chip_id);
}
return phy_data;
}
static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
{
unsigned long ioaddr, cr10_value;
ioaddr = iobase + DCR10;
cr10_value = phy_addr;
cr10_value = (cr10_value<<5) + offset;
cr10_value = (cr10_value<<16) + 0x08000000;
outl(cr10_value, ioaddr);
udelay(1);
while (1) {
cr10_value = inl(ioaddr);
if (cr10_value & 0x10000000)
break;
}
return (cr10_value&0x0ffff);
}
static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
u8 offset, u16 phy_data)
{
unsigned long ioaddr, cr10_value;
ioaddr = iobase + DCR10;
cr10_value = phy_addr;
cr10_value = (cr10_value<<5) + offset;
cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
outl(cr10_value, ioaddr);
udelay(1);
}
/*
* Write one bit data to Phy Controller
*/
static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
{
outl(phy_data , ioaddr); /* MII Clock Low */
udelay(1);
outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
udelay(1);
outl(phy_data , ioaddr); /* MII Clock Low */
udelay(1);
}
/*
* Read one bit phy data from PHY controller
*/
static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
{
u16 phy_data;
outl(0x50000 , ioaddr);
udelay(1);
phy_data = (inl(ioaddr) >> 19) & 0x1;
outl(0x40000 , ioaddr);
udelay(1);
return phy_data;
}
/*
* Set MAC address to ID Table
*/
static void set_mac_addr(struct eth_device *dev)
{
int i;
u16 addr;
struct uli526x_board_info *db = dev->priv;
outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
/* Reset dianostic pointer port */
outl(0x1c0, db->ioaddr + DCR13);
outl(0, db->ioaddr + DCR14); /* Clear reset port */
outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
outl(0, db->ioaddr + DCR14); /* Clear reset port */
outl(0, db->ioaddr + DCR13); /* Clear CR13 */
/* Select ID Table access port */
outl(0x1b0, db->ioaddr + DCR13);
/* Read MAC address from CR14 */
for (i = 0; i < 3; i++) {
addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
outl(addr, db->ioaddr + DCR14);
}
/* write end */
outl(0, db->ioaddr + DCR13); /* Clear CR13 */
outl(0, db->ioaddr + DCR0); /* Clear CR0 */
udelay(10);
return;
}
#endif

29
include/asm-m68k/immap_5329.h
View File

@ -57,7 +57,8 @@
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
#define MMAP_CCM 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0004
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
@ -479,20 +480,22 @@ typedef struct wdog_ctrl {
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rstctrl; /* 0x00 Reset Controller register */
u8 rststat; /* 0x01 Reset Status register */
u16 res1; /* 0x02 - 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 res2; /* 0x06 */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0A Chip identification register */
u32 res3; /* 0x0C */
u16 misccr; /* 0x10 Miscellaneous control register */
u16 cdr; /* 0x12 Clock divider register */
u16 uhcsr; /* 0x14 USB Host controller status register */
u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
u16 ccr; /* 0x00 Chip configuration register */
u16 res2; /* 0x02 */
u16 rcon; /* 0x04 Rreset configuration register */
u16 cir; /* 0x06 Chip identification register */
u32 res3; /* 0x08 */
u16 misccr; /* 0x0A Miscellaneous control register */
u16 cdr; /* 0x0C Clock divider register */
u16 uhcsr; /* 0x10 USB Host controller status register */
u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */
} ccm_t;
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */

15
include/asm-m68k/m5329.h
View File

@ -245,6 +245,21 @@
#define CSCR_BSTR (0x00000010)
#define CSCR_BSTW (0x00000008)
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for RSR */
#define RCM_RSR_LOL (0x01)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/

4
include/asm-m68k/m5445x.h
View File

@ -792,8 +792,8 @@
#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
#define GPIO_PAR_FEC_FEC0_MII (0x07)
#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02)
#define GPIO_PAR_FEC_FEC0_ATA (0x01)
#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
/* Bit definitions and macros for PAR_DMA */

16
include/asm-mips/io.h
View File

@ -71,7 +71,21 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
extern const unsigned long mips_io_port_base;
/*
* Gcc will generate code to load the value of mips_io_port_base after each
* function call which may be fairly wasteful in some cases. So we don't
* play quite by the book. We tell gcc mips_io_port_base is a long variable
* which solves the code generation issue. Now we need to violate the
* aliasing rules a little to make initialization possible and finally we
* will need the barrier() to fight side effects of the aliasing chat.
* This trickery will eventually collapse under gcc's optimizer. Oh well.
*/
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
}
/*
* Thanks to James van Artsdalen for a better timing-fix than

1
include/configs/MPC8544DS.h
View File

@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
/* define to use L1 as initial stack */

1
include/configs/MPC8641HPCN.h
View File

@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */

4
include/configs/lwmon5.h
View File

@ -432,7 +432,7 @@
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
@ -473,7 +473,7 @@
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \

4
include/configs/rsdproto.h
View File

@ -92,8 +92,8 @@
/* enable I2C */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x30
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */

110
include/miiphy.h
View File

@ -26,56 +26,49 @@
|
| Author: Mark Wisner
|
| Change Activity-
|
| Date Description of Change BY
| --------- --------------------- ---
| 04-May-99 Created MKW
| 07-Jul-99 Added full duplex support MKW
| 08-Sep-01 Tweaks gvb
|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
#define _miiphy_h_
#include <net.h>
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset(char *devname, unsigned char addr);
int miiphy_speed(char *devname, unsigned char addr);
int miiphy_duplex(char *devname, unsigned char addr);
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset (char *devname, unsigned char addr);
int miiphy_speed (char *devname, unsigned char addr);
int miiphy_duplex (char *devname, unsigned char addr);
int miiphy_is_1000base_x (char *devname, unsigned char addr);
#ifdef CFG_FAULT_ECHO_LINK_DOWN
int miiphy_link(char *devname, unsigned char addr);
int miiphy_link (char *devname, unsigned char addr);
#endif
void miiphy_init(void);
void miiphy_init (void);
void miiphy_register(char *devname,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
void miiphy_register (char *devname,
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
int miiphy_set_current_dev(char *devname);
char *miiphy_get_current_dev(void);
int miiphy_set_current_dev (char *devname);
char *miiphy_get_current_dev (void);
void miiphy_listdev(void);
void miiphy_listdev (void);
#define BB_MII_DEVNAME "bbmii"
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
unsigned char reg, unsigned short *value);
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
unsigned char reg, unsigned short value);
/* phy seed setup */
#define AUTO 99
#define _1000BASET 1000
#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#define HALF 22
@ -90,9 +83,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_ANNPTR 0x07
#define PHY_ANLPNP 0x08
#define PHY_1000BTCR 0x09
#define PHY_1000BTSR 0x0A
#define PHY_ANLPNP 0x08
#define PHY_1000BTCR 0x09
#define PHY_1000BTSR 0x0A
#define PHY_EXSR 0x0F
#define PHY_PHYSTS 0x10
#define PHY_MIPSCR 0x11
#define PHY_MIPGSR 0x12
@ -115,10 +109,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_BMCR_DPLX 0x0100
#define PHY_BMCR_COL_TST 0x0080
#define PHY_BMCR_SPEED_MASK 0x2040
#define PHY_BMCR_1000_MBPS 0x0040
#define PHY_BMCR_100_MBPS 0x2000
#define PHY_BMCR_10_MBPS 0x0000
#define PHY_BMCR_SPEED_MASK 0x2040
#define PHY_BMCR_1000_MBPS 0x0040
#define PHY_BMCR_100_MBPS 0x2000
#define PHY_BMCR_10_MBPS 0x0000
/* phy BMSR */
#define PHY_BMSR_100T4 0x8000
@ -126,6 +120,7 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_BMSR_100TXH 0x2000
#define PHY_BMSR_10TF 0x1000
#define PHY_BMSR_10TH 0x0800
#define PHY_BMSR_EXT_STAT 0x0100
#define PHY_BMSR_PRE_SUP 0x0040
#define PHY_BMSR_AUTN_COMP 0x0020
#define PHY_BMSR_RF 0x0010
@ -138,23 +133,42 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_ANLPAR_NP 0x8000
#define PHY_ANLPAR_ACK 0x4000
#define PHY_ANLPAR_RF 0x2000
#define PHY_ANLPAR_ASYMP 0x0800
#define PHY_ANLPAR_PAUSE 0x0400
#define PHY_ANLPAR_T4 0x0200
#define PHY_ANLPAR_TXFD 0x0100
#define PHY_ANLPAR_TX 0x0080
#define PHY_ANLPAR_10FD 0x0040
#define PHY_ANLPAR_10 0x0020
#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
/* phy ANLPAR 1000BASE-X */
#define PHY_X_ANLPAR_NP 0x8000
#define PHY_X_ANLPAR_ACK 0x4000
#define PHY_X_ANLPAR_RF_MASK 0x3000
#define PHY_X_ANLPAR_PAUSE_MASK 0x0180
#define PHY_X_ANLPAR_HD 0x0040
#define PHY_X_ANLPAR_FD 0x0020
#define PHY_ANLPAR_PSB_MASK 0x001f
#define PHY_ANLPAR_PSB_802_3 0x0001
#define PHY_ANLPAR_PSB_802_9 0x0002
#define PHY_ANLPAR_PSB_MASK 0x001f
#define PHY_ANLPAR_PSB_802_3 0x0001
#define PHY_ANLPAR_PSB_802_9 0x0002
/* PHY_1000BTSR */
#define PHY_1000BTSR_MSCF 0x8000
#define PHY_1000BTSR_MSCR 0x4000
#define PHY_1000BTSR_LRS 0x2000
#define PHY_1000BTSR_RRS 0x1000
#define PHY_1000BTSR_1000FD 0x0800
#define PHY_1000BTSR_1000HD 0x0400
/* phy 1000BTCR */
#define PHY_1000BTCR_1000FD 0x0200
#define PHY_1000BTCR_1000HD 0x0100
/* phy 1000BTSR */
#define PHY_1000BTSR_MSCF 0x8000
#define PHY_1000BTSR_MSCR 0x4000
#define PHY_1000BTSR_LRS 0x2000
#define PHY_1000BTSR_RRS 0x1000
#define PHY_1000BTSR_1000FD 0x0800
#define PHY_1000BTSR_1000HD 0x0400
/* phy EXSR */
#define PHY_EXSR_1000XF 0x8000
#define PHY_EXSR_1000XH 0x4000
#define PHY_EXSR_1000TF 0x2000
#define PHY_EXSR_1000TH 0x1000
#endif

5
lib_mips/board.c
View File

@ -62,6 +62,11 @@ static ulong mem_malloc_start;
static ulong mem_malloc_end;
static ulong mem_malloc_brk;
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
unsigned long mips_io_port_base = -1;
/*
* The Malloc area is immediately below the monitor copy in DRAM

4
net/eth.c
View File

@ -54,6 +54,7 @@ extern int rtl8169_initialize(bd_t*);
extern int scc_initialize(bd_t*);
extern int skge_initialize(bd_t*);
extern int tsi108_eth_initialize(bd_t*);
extern int uli526x_initialize(bd_t *);
extern int tsec_initialize(bd_t*, int, char *);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
@ -238,6 +239,9 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_TSI108_ETH)
tsi108_eth_initialize(bis);
#endif
#if defined(CONFIG_ULI526X)
uli526x_initialize(bis);
#endif
#if defined(CONFIG_RTL8139)
rtl8139_initialize(bis);
#endif