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Fix timer problems on AMCC yucca board.

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Set Timer Clock Select to use CPU clock as a timer input source.
This commit is contained in:
Marian Balakowicz
2006-07-06 21:17:24 +02:00
parent caaeaf925f
commit edd6cf20e1
3 changed files with 7 additions and 6 deletions
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3
CHANGELOG
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@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
* Bring yucca config more in line with other AMCC boards. * Bring yucca config more in line with other AMCC boards.
* Add AMCC bamboo board to MAKEALL build script. * Add AMCC bamboo board to MAKEALL build script.

8
cpu/ppc4xx/start.S
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@@ -158,7 +158,7 @@ _start_440:
/*----------------------------------------------------------------+ /*----------------------------------------------------------------+
| Core bug fix. Clear the esr | Core bug fix. Clear the esr
+-----------------------------------------------------------------*/ +-----------------------------------------------------------------*/
addi r0,r0,0x0000 li r0,0
mtspr esr,r0 mtspr esr,r0
/*----------------------------------------------------------------*/ /*----------------------------------------------------------------*/
/* Clear and set up some registers. */ /* Clear and set up some registers. */
@@ -217,17 +217,15 @@ _start_440:
| g. FCOM: Normal operation | g. FCOM: Normal operation
| h. MMUPEI: Record even parity. Normal operation. | h. MMUPEI: Record even parity. Normal operation.
| i. FFF: Flush only as much data as necessary. | i. FFF: Flush only as much data as necessary.
| j. TCS: Timebase increments from externally supplied clock | j. TCS: Timebase increments from CPU clock.
+-----------------------------------------------------------------*/ +-----------------------------------------------------------------*/
addis r0, r0, 0x0000 li r0,0
ori r0, r0, 0x0080
mtspr ccr1, r0 mtspr ccr1, r0
/*----------------------------------------------------------------+ /*----------------------------------------------------------------+
| Reset the timebase. | Reset the timebase.
| The previous write to CCR1 sets the timebase source. | The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/ +-----------------------------------------------------------------*/
addi r0, r0, 0x0000
mtspr tbl, r0 mtspr tbl, r0
mtspr tbu, r0 mtspr tbu, r0
#endif #endif

2
include/configs/yucca.h
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@@ -243,7 +243,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH related * FLASH related