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MIPS: allow override of flush_dcache_range()

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Useful in custom HW designs which have a need to flush dcache
range in a completely non standard way.

Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
This commit is contained in:
Alex Nemirovsky 2019-12-23 20:19:20 +00:00 committed by Daniel Schwierzeck
parent dfd5321bec
commit ebdc278954
1 changed files with 1 additions and 1 deletions
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arch/mips/lib/cache.c
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@ -141,7 +141,7 @@ ops_done:
instruction_hazard_barrier(); instruction_hazard_barrier();
} }
void flush_dcache_range(ulong start_addr, ulong stop) void __weak flush_dcache_range(ulong start_addr, ulong stop)
{ {
unsigned long lsize = dcache_line_size(); unsigned long lsize = dcache_line_size();
unsigned long slsize = scache_line_size(); unsigned long slsize = scache_line_size();