clk: mtmips: add clock driver for MediaTek MT7621 SoC
This patch adds a clock driver for MediaTek MT7621 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Daniel Schwierzeck
parent
46c7e9ed03
commit
e75cc00982
@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
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obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
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obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
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288
drivers/clk/mtmips/clk-mt7621.c
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288
drivers/clk/mtmips/clk-mt7621.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#define SYSC_MAP_SIZE 0x100
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#define MEMC_MAP_SIZE 0x1000
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/* SYSC */
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#define SYSCFG0_REG 0x10
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#define XTAL_MODE_SEL GENMASK(8, 6)
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#define CLKCFG0_REG 0x2c
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#define CPU_CLK_SEL GENMASK(31, 30)
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#define PERI_CLK_SEL BIT(4)
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#define CLKCFG1_REG 0x30
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#define CUR_CLK_STS_REG 0x44
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#define CUR_CPU_FDIV GENMASK(12, 8)
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#define CUR_CPU_FFRAC GENMASK(4, 0)
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/* MEMC */
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#define MEMPLL1_REG 0x0604
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#define RG_MEPL_DIV2_SEL GENMASK(2, 1)
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#define MEMPLL6_REG 0x0618
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#define MEMPLL18_REG 0x0648
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#define RG_MEPL_PREDIV GENMASK(13, 12)
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#define RG_MEPL_FBDIV GENMASK(10, 4)
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/* Fixed 500M clock */
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#define GMPLL_CLK 500000000
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struct mt7621_clk_priv {
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void __iomem *sysc_base;
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int cpu_clk;
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int ddr_clk;
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int sys_clk;
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int xtal_clk;
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};
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enum mt7621_clk_src {
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CLK_SRC_CPU,
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CLK_SRC_DDR,
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CLK_SRC_SYS,
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CLK_SRC_XTAL,
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CLK_SRC_PERI,
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CLK_SRC_125M,
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CLK_SRC_150M,
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CLK_SRC_250M,
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CLK_SRC_270M,
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__CLK_SRC_MAX
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};
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struct mt7621_clk_map {
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u32 cgbit;
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enum mt7621_clk_src clksrc;
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};
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#define CLK_MAP(_id, _cg, _src) \
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[_id] = { .cgbit = (_cg), .clksrc = (_src) }
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#define CLK_MAP_SRC(_id, _src) \
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[_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
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static const struct mt7621_clk_map mt7621_clk_mappings[] = {
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CLK_MAP_SRC(MT7621_CLK_XTAL, CLK_SRC_XTAL),
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CLK_MAP_SRC(MT7621_CLK_CPU, CLK_SRC_CPU),
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CLK_MAP_SRC(MT7621_CLK_BUS, CLK_SRC_SYS),
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CLK_MAP_SRC(MT7621_CLK_50M, CLK_SRC_PERI),
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CLK_MAP_SRC(MT7621_CLK_125M, CLK_SRC_125M),
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CLK_MAP_SRC(MT7621_CLK_150M, CLK_SRC_150M),
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CLK_MAP_SRC(MT7621_CLK_250M, CLK_SRC_250M),
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CLK_MAP_SRC(MT7621_CLK_270M, CLK_SRC_270M),
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CLK_MAP(MT7621_CLK_HSDMA, 5, CLK_SRC_150M),
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CLK_MAP(MT7621_CLK_FE, 6, CLK_SRC_250M),
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CLK_MAP(MT7621_CLK_SP_DIVTX, 7, CLK_SRC_270M),
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CLK_MAP(MT7621_CLK_TIMER, 8, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_PCM, 11, CLK_SRC_270M),
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CLK_MAP(MT7621_CLK_PIO, 13, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_GDMA, 14, CLK_SRC_SYS),
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CLK_MAP(MT7621_CLK_NAND, 15, CLK_SRC_125M),
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CLK_MAP(MT7621_CLK_I2C, 16, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_I2S, 17, CLK_SRC_270M),
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CLK_MAP(MT7621_CLK_SPI, 18, CLK_SRC_SYS),
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CLK_MAP(MT7621_CLK_UART1, 19, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_UART2, 20, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_UART3, 21, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_ETH, 23, CLK_SRC_PERI),
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CLK_MAP(MT7621_CLK_PCIE0, 24, CLK_SRC_125M),
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CLK_MAP(MT7621_CLK_PCIE1, 25, CLK_SRC_125M),
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CLK_MAP(MT7621_CLK_PCIE2, 26, CLK_SRC_125M),
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CLK_MAP(MT7621_CLK_CRYPTO, 29, CLK_SRC_250M),
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CLK_MAP(MT7621_CLK_SHXC, 30, CLK_SRC_PERI),
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CLK_MAP_SRC(MT7621_CLK_MAX, __CLK_SRC_MAX),
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CLK_MAP_SRC(MT7621_CLK_DDR, CLK_SRC_DDR),
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};
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static ulong mt7621_clk_get_rate(struct clk *clk)
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{
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struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
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u32 val;
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switch (mt7621_clk_mappings[clk->id].clksrc) {
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case CLK_SRC_CPU:
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return priv->cpu_clk;
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case CLK_SRC_DDR:
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return priv->ddr_clk;
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case CLK_SRC_SYS:
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return priv->sys_clk;
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case CLK_SRC_XTAL:
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return priv->xtal_clk;
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case CLK_SRC_PERI:
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val = readl(priv->sysc_base + CLKCFG0_REG);
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if (val & PERI_CLK_SEL)
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return priv->xtal_clk;
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else
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return GMPLL_CLK / 10;
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case CLK_SRC_125M:
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return 125000000;
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case CLK_SRC_150M:
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return 150000000;
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case CLK_SRC_250M:
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return 250000000;
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case CLK_SRC_270M:
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return 270000000;
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default:
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return 0;
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}
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}
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static int mt7621_clk_enable(struct clk *clk)
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{
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struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
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u32 cgbit;
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cgbit = mt7621_clk_mappings[clk->id].cgbit;
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if (cgbit == UINT32_MAX)
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return -ENOSYS;
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setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
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return 0;
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}
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static int mt7621_clk_disable(struct clk *clk)
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{
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struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
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u32 cgbit;
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cgbit = mt7621_clk_mappings[clk->id].cgbit;
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if (cgbit == UINT32_MAX)
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return -ENOSYS;
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clrbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
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return 0;
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}
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static int mt7621_clk_request(struct clk *clk)
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{
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if (clk->id >= ARRAY_SIZE(mt7621_clk_mappings))
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return -EINVAL;
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return 0;
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}
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const struct clk_ops mt7621_clk_ops = {
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.request = mt7621_clk_request,
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.enable = mt7621_clk_enable,
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.disable = mt7621_clk_disable,
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.get_rate = mt7621_clk_get_rate,
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};
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static void mt7621_get_clocks(struct mt7621_clk_priv *priv, struct regmap *memc)
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{
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u32 bs, xtal_sel, clkcfg0, cur_clk, mempll, dividx, fb;
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u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk;
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static const u32 xtal_div_tbl[] = {0, 1, 2, 2};
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bs = readl(priv->sysc_base + SYSCFG0_REG);
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clkcfg0 = readl(priv->sysc_base + CLKCFG0_REG);
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cur_clk = readl(priv->sysc_base + CUR_CLK_STS_REG);
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xtal_sel = FIELD_GET(XTAL_MODE_SEL, bs);
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if (xtal_sel <= 2)
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xtal_clk = 20 * 1000 * 1000;
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else if (xtal_sel <= 5)
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xtal_clk = 40 * 1000 * 1000;
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else
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xtal_clk = 25 * 1000 * 1000;
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switch (FIELD_GET(CPU_CLK_SEL, clkcfg0)) {
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case 0:
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cpu_clk = GMPLL_CLK;
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break;
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case 1:
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regmap_read(memc, MEMPLL18_REG, &mempll);
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dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
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fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
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xtal_div = 1 << xtal_div_tbl[dividx];
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cpu_clk = (fb + 1) * xtal_clk / xtal_div;
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break;
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default:
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cpu_clk = xtal_clk;
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}
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ffiv = FIELD_GET(CUR_CPU_FDIV, cur_clk);
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ffrac = FIELD_GET(CUR_CPU_FFRAC, cur_clk);
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cpu_clk = cpu_clk / ffiv * ffrac;
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regmap_read(memc, MEMPLL6_REG, &mempll);
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dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
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fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
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xtal_div = 1 << xtal_div_tbl[dividx];
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ddr_clk = fb * xtal_clk / xtal_div;
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regmap_read(memc, MEMPLL1_REG, &bs);
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if (!FIELD_GET(RG_MEPL_DIV2_SEL, bs))
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ddr_clk *= 2;
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priv->cpu_clk = cpu_clk;
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priv->sys_clk = cpu_clk / 4;
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priv->ddr_clk = ddr_clk;
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priv->xtal_clk = xtal_clk;
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}
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static int mt7621_clk_probe(struct udevice *dev)
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{
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struct mt7621_clk_priv *priv = dev_get_priv(dev);
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struct ofnode_phandle_args args;
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struct udevice *pdev;
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struct regmap *memc;
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int ret;
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pdev = dev_get_parent(dev);
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if (!pdev)
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return -ENODEV;
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priv->sysc_base = dev_remap_addr(pdev);
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if (!priv->sysc_base)
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return -EINVAL;
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/* get corresponding memc phandle */
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ret = dev_read_phandle_with_args(dev, "mediatek,memc", NULL, 0, 0,
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&args);
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if (ret)
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return ret;
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memc = syscon_node_to_regmap(args.node);
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if (IS_ERR(memc))
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return PTR_ERR(memc);
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mt7621_get_clocks(priv, memc);
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return 0;
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}
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static const struct udevice_id mt7621_clk_ids[] = {
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{ .compatible = "mediatek,mt7621-clk" },
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{ }
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};
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U_BOOT_DRIVER(mt7621_clk) = {
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.name = "mt7621-clk",
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.id = UCLASS_CLK,
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.of_match = mt7621_clk_ids,
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.probe = mt7621_clk_probe,
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.priv_auto = sizeof(struct mt7621_clk_priv),
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.ops = &mt7621_clk_ops,
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};
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46
include/dt-bindings/clock/mt7621-clk.h
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46
include/dt-bindings/clock/mt7621-clk.h
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MT7621_CLK_H_
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#define _DT_BINDINGS_MT7621_CLK_H_
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#define MT7621_CLK_XTAL 0
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#define MT7621_CLK_CPU 1
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#define MT7621_CLK_BUS 2
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#define MT7621_CLK_50M 3
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#define MT7621_CLK_125M 4
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#define MT7621_CLK_150M 5
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#define MT7621_CLK_250M 6
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#define MT7621_CLK_270M 7
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#define MT7621_CLK_HSDMA 8
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#define MT7621_CLK_FE 9
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#define MT7621_CLK_SP_DIVTX 10
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#define MT7621_CLK_TIMER 11
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#define MT7621_CLK_PCM 12
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#define MT7621_CLK_PIO 13
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#define MT7621_CLK_GDMA 14
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#define MT7621_CLK_NAND 15
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#define MT7621_CLK_I2C 16
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#define MT7621_CLK_I2S 17
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#define MT7621_CLK_SPI 18
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#define MT7621_CLK_UART1 19
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#define MT7621_CLK_UART2 20
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#define MT7621_CLK_UART3 21
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#define MT7621_CLK_ETH 22
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#define MT7621_CLK_PCIE0 23
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#define MT7621_CLK_PCIE1 24
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#define MT7621_CLK_PCIE2 25
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#define MT7621_CLK_CRYPTO 26
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#define MT7621_CLK_SHXC 27
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#define MT7621_CLK_MAX 28
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/* for u-boot only */
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#define MT7621_CLK_DDR 29
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#endif /* _DT_BINDINGS_MT7621_CLK_H_ */
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