arm: bcmbca: add bcm4908 SoC support
BCM4908 is a Broadcom B53 based WLAN AP router SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and Broadcom uart. This SoC is supported in the linux git repository so the dts and dtsi files are stripped down version of linux copies with mininum blocks needed by u-boot. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
William Zhang
Tom Rini
parent
1b81843bac
commit
e5703df262
@ -218,6 +218,7 @@ F: arch/arm/mach-bcmbca/
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F: board/broadcom/bcmbca/
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N: bcmbca
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N: bcm[9]?47622
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N: bcm[9]?4908
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N: bcm[9]?4912
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N: bcm[9]?63138
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N: bcm[9]?63146
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@ -1182,6 +1182,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
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dtb-$(CONFIG_BCM47622) += \
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bcm947622.dtb
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dtb-$(CONFIG_BCM4908) += \
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bcm94908.dtb
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dtb-$(CONFIG_BCM4912) += \
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bcm94912.dtb
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dtb-$(CONFIG_BCM63138) += \
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127
arch/arm/dts/bcm4908.dtsi
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127
arch/arm/dts/bcm4908.dtsi
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@ -0,0 +1,127 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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compatible = "brcm,bcm4908", "brcm,bcmbca";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "brcm,brahma-b53";
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reg = <0x3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0xfff8>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x81000000 0x4000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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clocks {
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periph_clk: periph_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0xff800000 0x3000>;
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uart0: serial@640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x640 0x18>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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30
arch/arm/dts/bcm94908.dts
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30
arch/arm/dts/bcm94908.dts
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@ -0,0 +1,30 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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/dts-v1/;
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#include "bcm4908.dtsi"
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/ {
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model = "Broadcom BCM94908 Reference Board";
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compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x08000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -12,6 +12,13 @@ config BCM47622
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select DM_SERIAL
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select PL01X_SERIAL
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config BCM4908
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bool "Support for Broadcom 4908 Family"
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select ARM64
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select SYS_ARCH_TIMER
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select DM_SERIAL
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select BCM6345_SERIAL
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config BCM4912
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bool "Support for Broadcom 4912 Family"
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select ARM64
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@ -77,6 +84,7 @@ config BCM6878
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select PL01X_SERIAL
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source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
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source "arch/arm/mach-bcmbca/bcm4908/Kconfig"
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source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63146/Kconfig"
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@ -4,6 +4,7 @@
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#
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obj-$(CONFIG_BCM47622) += bcm47622/
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obj-$(CONFIG_BCM4908) += bcm4908/
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obj-$(CONFIG_BCM4912) += bcm4912/
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obj-$(CONFIG_BCM63138) += bcm63138/
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obj-$(CONFIG_BCM63146) += bcm63146/
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17
arch/arm/mach-bcmbca/bcm4908/Kconfig
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17
arch/arm/mach-bcmbca/bcm4908/Kconfig
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@ -0,0 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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if BCM4908
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config TARGET_BCM94908
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bool "Broadcom 4908 Reference Board"
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depends on ARCH_BCMBCA
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config SYS_SOC
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default "bcm4908"
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source "board/broadcom/bcmbca/Kconfig"
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endif
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5
arch/arm/mach-bcmbca/bcm4908/Makefile
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5
arch/arm/mach-bcmbca/bcm4908/Makefile
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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obj-y += mmu_table.o
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32
arch/arm/mach-bcmbca/bcm4908/mmu_table.c
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32
arch/arm/mach-bcmbca/bcm4908/mmu_table.c
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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static struct mm_region bcm94908_mem_map[] = {
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{
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 1UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* SoC peripheral */
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.virt = 0xff800000UL,
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.phys = 0xff800000UL,
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.size = 0x100000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = bcm94908_mem_map;
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@ -16,6 +16,13 @@ config SYS_CONFIG_NAME
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endif
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if TARGET_BCM94908
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config SYS_CONFIG_NAME
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default "bcm94908"
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endif
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if TARGET_BCM94912
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config SYS_CONFIG_NAME
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23
configs/bcm94908_defconfig
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23
configs/bcm94908_defconfig
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@ -0,0 +1,23 @@
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CONFIG_ARM=y
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CONFIG_COUNTER_FREQUENCY=50000000
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CONFIG_ARCH_BCMBCA=y
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CONFIG_SYS_TEXT_BASE=0x01000000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_BCM4908=y
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CONFIG_TARGET_BCM94908=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
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CONFIG_IDENT_STRING=" Broadcom BCM4908"
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CONFIG_SYS_LOAD_ADDR=0x01000000
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CONFIG_ENV_VARS_UBOOT_CONFIG=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_CACHE=y
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CONFIG_OF_EMBED=y
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CONFIG_CLK=y
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11
include/configs/bcm94908.h
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11
include/configs/bcm94908.h
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2022 Broadcom Ltd.
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*/
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#ifndef __BCM94908_H
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#define __BCM94908_H
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#endif
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