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Merge git://git.denx.de/u-boot-mpc83xx

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- Update MPC83xx platform support to current best practices, etc.
This commit is contained in:
Tom Rini
2019-05-21 07:13:35 -04:00
parent ffbad25b32 d494cdb97e
commit e1a2ed7180
220 changed files with 20058 additions and 5906 deletions
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22
drivers/board/gazerbeam.c
View File

@@ -61,7 +61,7 @@ static int _read_board_variant_data(struct udevice *dev)
struct udevice *i2c_bus;
struct udevice *dummy;
char *listname;
int mc4, mc2, sc, con;
int mc4, mc2, sc, mc2_sc, con;
int gpio_num;
int res;
@@ -78,16 +78,16 @@ static int _read_board_variant_data(struct udevice *dev)
return -EIO;
}
mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy);
if (mc2 && mc4) {
if (mc2_sc && mc4) {
debug("%s: Board hardware configuration inconsistent.\n",
dev->name);
return -EINVAL;
}
listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4";
listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4";
gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios,
ARRAY_SIZE(priv->var_gpios),
@@ -105,12 +105,7 @@ static int _read_board_variant_data(struct udevice *dev)
return sc;
}
con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
if (con < 0) {
debug("%s: Error while reading 'con' GPIO (err = %d)",
dev->name, con);
return con;
}
mc2 = mc2_sc ? (sc ? 0 : 1) : 0;
if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) {
debug("%s: Board hardware configuration inconsistent.\n",
@@ -118,6 +113,13 @@ static int _read_board_variant_data(struct udevice *dev)
return -EINVAL;
}
con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
if (con < 0) {
debug("%s: Error while reading 'con' GPIO (err = %d)",
dev->name, con);
return con;
}
priv->variant = con ? VAR_CON : VAR_CPU;
priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0));

7
drivers/clk/mpc83xx_clk.c
View File

@@ -275,6 +275,12 @@ static ulong mpc83xx_clk_get_rate(struct clk *clk)
return priv->speed[clk->id];
}
static int mpc83xx_clk_enable(struct clk *clk)
{
/* MPC83xx clocks are always enabled */
return 0;
}
int get_clocks(void)
{
/* Empty implementation to keep the prototype in common.h happy */
@@ -301,6 +307,7 @@ int get_serial_clock(void)
const struct clk_ops mpc83xx_clk_ops = {
.request = mpc83xx_clk_request,
.get_rate = mpc83xx_clk_get_rate,
.enable = mpc83xx_clk_enable,
};
static const struct udevice_id mpc83xx_clk_match[] = {

4
drivers/ddr/fsl/main.c
View File

@@ -23,8 +23,12 @@
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
#else
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
#endif
#ifdef CONFIG_PPC
#include <asm/fsl_law.h>

124
drivers/i2c/ihs_i2c.c
View File

@@ -8,8 +8,7 @@
#include <i2c.h>
#ifdef CONFIG_DM_I2C
#include <dm.h>
#include <fpgamap.h>
#include "../misc/gdsys_soc.h"
#include <regmap.h>
#else
#include <gdsys_fpga.h>
#endif
@@ -18,18 +17,24 @@
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv {
uint speed;
phys_addr_t addr;
struct regmap *map;
};
enum {
REG_INTERRUPT_STATUS = 0x00,
REG_INTERRUPT_ENABLE_CONTROL = 0x02,
REG_WRITE_MAILBOX_EXT = 0x04,
REG_WRITE_MAILBOX = 0x06,
REG_READ_MAILBOX_EXT = 0x08,
REG_READ_MAILBOX = 0x0A,
struct ihs_i2c_regs {
u16 interrupt_status;
u16 interrupt_enable_control;
u16 write_mailbox_ext;
u16 write_mailbox;
u16 read_mailbox_ext;
u16 read_mailbox;
};
#define ihs_i2c_set(map, member, val) \
regmap_set(map, struct ihs_i2c_regs, member, val)
#define ihs_i2c_get(map, member, valp) \
regmap_get(map, struct ihs_i2c_regs, member, valp)
#else /* !CONFIG_DM_I2C */
DECLARE_GLOBAL_DATA_PTR;
@@ -92,14 +97,10 @@ static int wait_for_int(bool read)
uint ctr = 0;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
struct udevice *fpga;
gdsys_soc_get_fpga(dev, &fpga);
#endif
#ifdef CONFIG_DM_I2C
fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
FPGAMAP_SIZE_16);
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
@@ -107,17 +108,18 @@ static int wait_for_int(bool read)
while (!(val & (I2CINT_ERROR_EV
| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
udelay(10);
if (ctr++ > 5000)
return 1;
if (ctr++ > 5000) {
debug("%s: timed out\n", __func__);
return -ETIMEDOUT;
}
#ifdef CONFIG_DM_I2C
fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
FPGAMAP_SIZE_16);
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
}
return (val & I2CINT_ERROR_EV) ? 1 : 0;
return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}
#ifdef CONFIG_DM_I2C
@@ -130,20 +132,16 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
{
u16 val;
u16 data;
int res;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
struct udevice *fpga;
gdsys_soc_get_fpga(dev, &fpga);
#endif
/* Clear interrupt status */
data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
#ifdef CONFIG_DM_I2C
fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
FPGAMAP_SIZE_16);
fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
FPGAMAP_SIZE_16);
ihs_i2c_set(priv->map, interrupt_status, data);
ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_SET_REG(interrupt_status, data);
I2C_GET_REG(interrupt_status, &val);
@@ -156,8 +154,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
if (len > 1)
val |= buffer[1] << 8;
#ifdef CONFIG_DM_I2C
fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
FPGAMAP_SIZE_16);
ihs_i2c_set(priv->map, write_mailbox_ext, val);
#else
I2C_SET_REG(write_mailbox_ext, val);
#endif
@@ -170,24 +167,27 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
| (is_last ? 0 : I2CMB_HOLD_BUS);
#ifdef CONFIG_DM_I2C
fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
FPGAMAP_SIZE_16);
ihs_i2c_set(priv->map, write_mailbox, data);
#else
I2C_SET_REG(write_mailbox, data);
#endif
#ifdef CONFIG_DM_I2C
if (wait_for_int(dev, read))
res = wait_for_int(dev, read);
#else
if (wait_for_int(read))
res = wait_for_int(read);
#endif
return 1;
if (res) {
if (res == -ETIMEDOUT)
debug("%s: time out while waiting for event\n", __func__);
return res;
}
/* If we want to read, get the bytes from the mailbox */
if (read) {
#ifdef CONFIG_DM_I2C
fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
FPGAMAP_SIZE_16);
ihs_i2c_get(priv->map, read_mailbox_ext, &val);
#else
I2C_GET_REG(read_mailbox_ext, &val);
#endif
@@ -206,19 +206,21 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
int read)
#endif
{
int res;
while (len) {
int transfer = min(len, 2);
bool is_last = len <= transfer;
#ifdef CONFIG_DM_I2C
if (ihs_i2c_transfer(dev, chip, data, transfer, read,
hold_bus ? false : is_last))
return 1;
res = ihs_i2c_transfer(dev, chip, data, transfer, read,
hold_bus ? false : is_last);
#else
if (ihs_i2c_transfer(chip, data, transfer, read,
hold_bus ? false : is_last))
return 1;
res = ihs_i2c_transfer(chip, data, transfer, read,
hold_bus ? false : is_last);
#endif
if (res)
return res;
data += transfer;
len -= transfer;
@@ -249,14 +251,19 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
int alen, uchar *buffer, int len, int read)
#endif
{
int res;
/* Don't hold the bus if length of data to send/receive is zero */
if (len <= 0)
return -EINVAL;
#ifdef CONFIG_DM_I2C
if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
return 1;
res = ihs_i2c_address(dev, chip, addr, alen, len);
#else
if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
return 1;
res = ihs_i2c_address(chip, addr, alen, len);
#endif
if (res)
return res;
#ifdef CONFIG_DM_I2C
return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
@@ -270,11 +277,8 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
int ihs_i2c_probe(struct udevice *bus)
{
struct ihs_i2c_priv *priv = dev_get_priv(bus);
int addr;
addr = dev_read_u32_default(bus, "reg", -1);
priv->addr = addr;
regmap_init_mem(dev_ofnode(bus), &priv->map);
return 0;
}
@@ -284,7 +288,7 @@ static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
struct ihs_i2c_priv *priv = dev_get_priv(bus);
if (speed != priv->speed && priv->speed != 0)
return 1;
return -EINVAL;
priv->speed = speed;
@@ -301,8 +305,8 @@ static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
* actucal data) or one message (just data)
*/
if (nmsgs > 2 || nmsgs == 0) {
debug("%s: Only one or two messages are supported.", __func__);
return -1;
debug("%s: Only one or two messages are supported\n", __func__);
return -ENOTSUPP;
}
omsg = nmsgs == 1 ? &dummy : msg;
@@ -322,9 +326,11 @@ static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
u32 chip_flags)
{
uchar buffer[2];
int res;
if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
return 1;
res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
if (res)
return res;
return 0;
}
@@ -366,9 +372,11 @@ static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
uchar buffer[2];
int res;
if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
return 1;
res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
if (res)
return res;
return 0;
}
@@ -399,7 +407,7 @@ static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
unsigned int speed)
{
if (speed != adap->speed)
return 1;
return -EINVAL;
return speed;
}

9
drivers/misc/gdsys_rxaui_ctrl.c
View File

@@ -29,6 +29,7 @@ struct gdsys_rxaui_ctrl_regs {
struct gdsys_rxaui_ctrl_priv {
struct regmap *map;
bool state;
};
int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val)
@@ -36,6 +37,8 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val)
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
u16 state;
priv->state = !priv->state;
rxaui_ctrl_get(priv->map, ctrl_1, &state);
if (val)
@@ -45,7 +48,7 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val)
rxaui_ctrl_set(priv->map, ctrl_1, state);
return 0;
return !priv->state;
}
static const struct misc_ops gdsys_rxaui_ctrl_ops = {
@@ -56,7 +59,9 @@ int gdsys_rxaui_ctrl_probe(struct udevice *dev)
{
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
regmap_init_mem(dev, &priv->map);
regmap_init_mem(dev_ofnode(dev), &priv->map);
priv->state = false;
return 0;
}

4
drivers/mtd/nand/raw/fsl_elbc_spl.c
View File

@@ -14,6 +14,10 @@
#include <asm/fsl_lbc.h>
#include <nand.h>
#ifdef CONFIG_MPC83xx
#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
#endif
#define WINDOW_SIZE 8192
static void nand_wait(void)

3
drivers/pci/pci_auto.c
View File

@@ -359,7 +359,8 @@ int dm_pciauto_config_device(struct udevice *dev)
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
!defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents

3
drivers/pci/pci_auto_old.c
View File

@@ -376,7 +376,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
PCI_DEV(dev));
break;
#endif
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
!defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents

2
drivers/qe/qe.c
View File

@@ -119,7 +119,7 @@ static void qe_sdma_init(void)
*/
static u8 thread_snum[] = {
/* Evthreads 16-29 are not supported in MPC8309 */
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,

24
drivers/ram/mpc83xx_sdram.c
View File

@@ -169,8 +169,8 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -179,10 +179,10 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_NEVER:
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_MPC830x) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -200,8 +200,8 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
if (!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
@@ -210,10 +210,10 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_NEVER:
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_MPC830x) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;