Merge git://git.denx.de/u-boot-mpc83xx
- Update MPC83xx platform support to current best practices, etc.
This commit is contained in:
Tom Rini
commit
e1a2ed7180
2
Kconfig
2
Kconfig
@ -512,7 +512,7 @@ config SYS_TEXT_BASE
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config SYS_CLK_FREQ
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depends on ARC || ARCH_SUNXI
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depends on ARC || ARCH_SUNXI || MPC83xx
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int "CPU clock frequency"
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help
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TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
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@ -39,6 +39,12 @@ config MPC8xx
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endchoice
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config HIGH_BATS
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bool "Enable high BAT registers"
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help
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Enable BATs (block address translation registers) 4-7 on machines
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that support them.
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source "arch/powerpc/cpu/mpc83xx/Kconfig"
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source "arch/powerpc/cpu/mpc85xx/Kconfig"
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source "arch/powerpc/cpu/mpc86xx/Kconfig"
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@ -10,38 +10,66 @@ choice
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config TARGET_MPC8308_P1M
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bool "Support mpc8308_p1m"
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select ARCH_MPC8308
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config TARGET_SBC8349
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bool "Support sbc8349"
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select ARCH_MPC8349
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config TARGET_VE8313
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bool "Support ve8313"
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select ARCH_MPC8313
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config TARGET_VME8349
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bool "Support vme8349"
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select ARCH_MPC8349
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config TARGET_CADDY2
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bool "Support caddy2"
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select ARCH_MPC8349
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config TARGET_MPC8308RDB
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bool "Support MPC8308RDB"
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select ARCH_MPC8308
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select SYS_FSL_ERRATUM_ESDHC111
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config TARGET_MPC8313ERDB
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bool "Support MPC8313ERDB"
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config TARGET_MPC8313ERDB_NOR
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bool "Support MPC8313ERDB_NOR"
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select ARCH_MPC8313
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select BOARD_EARLY_INIT_F
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select SUPPORT_SPL
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config TARGET_MPC8313ERDB_NAND
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bool "Support MPC8313ERDB_NAND"
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select ARCH_MPC8313
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select BOARD_EARLY_INIT_F
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select SUPPORT_SPL
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config TARGET_MPC8315ERDB
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bool "Support MPC8315ERDB"
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select ARCH_MPC8315
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select BOARD_EARLY_INIT_F
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config TARGET_MPC8323ERDB
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bool "Support MPC8323ERDB"
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select ARCH_MPC832X
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config TARGET_MPC832XEMDS
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bool "Support MPC832XEMDS"
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select ARCH_MPC832X
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select BOARD_EARLY_INIT_F
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config TARGET_MPC8349EMDS
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bool "Support MPC8349EMDS"
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select ARCH_MPC8349
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select BOARD_EARLY_INIT_F
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_HAS_DDR2
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config TARGET_MPC8349EMDS_SDRAM
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bool "Support MPC8349EMDS_SDRAM"
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select ARCH_MPC8349
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select BOARD_EARLY_INIT_F
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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@ -49,53 +77,272 @@ config TARGET_MPC8349EMDS
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config TARGET_MPC8349ITX
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bool "Support MPC8349ITX"
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select ARCH_MPC8349
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imply CMD_IRQ
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config TARGET_MPC837XEMDS
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bool "Support MPC837XEMDS"
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select ARCH_MPC837X
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select BOARD_EARLY_INIT_F
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imply CMD_SATA
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imply FSL_SATA
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config TARGET_MPC837XERDB
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bool "Support MPC837XERDB"
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select ARCH_MPC837X
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select BOARD_EARLY_INIT_F
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config TARGET_IDS8313
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bool "Support ids8313"
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select ARCH_MPC8313
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select DM
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imply CMD_DM
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config TARGET_KM8360
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bool "Support km8360"
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config TARGET_KMETER1
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bool "Support kmeter1"
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select ARCH_MPC8360
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imply CMD_CRAMFS
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imply CMD_DIAG
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imply FS_CRAMFS
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config TARGET_KMCOGE5NE
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bool "Support kmcoge5ne"
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select ARCH_MPC8360
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imply CMD_CRAMFS
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imply CMD_DIAG
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imply FS_CRAMFS
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config TARGET_SUVD3
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bool "Support suvd3"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_KMVECT1
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bool "Support kmvect1"
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select ARCH_MPC8309
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_KMTEGR1
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bool "Support kmtegr1"
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select ARCH_MPC8309
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_TUXX1
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bool "Support tuxx1"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_KMSUPX5
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bool "Support kmsupx5"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_TUGE1
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bool "Support tuge1"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_KMOPTI2
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bool "Support kmopti2"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_KMTEPR2
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bool "Support kmtepr2"
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select ARCH_MPC832X
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imply CMD_CRAMFS
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imply FS_CRAMFS
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config TARGET_TQM834X
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bool "Support TQM834x"
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select ARCH_MPC8349
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config TARGET_HRCON
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bool "Support hrcon"
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select ARCH_MPC8308
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select SYS_FSL_ERRATUM_ESDHC111
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config TARGET_STRIDER
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bool "Support strider"
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select ARCH_MPC8308
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select SYS_FSL_ERRATUM_ESDHC111
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imply CMD_PCA953X
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config TARGET_GAZERBEAM
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bool "Support gazerbeam"
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select ARCH_MPC8308
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select SYS_FSL_ERRATUM_ESDHC111
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imply ENV_IS_IN_FLASH
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help
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The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
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Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
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appliances.
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Features include:
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* Two gigabit ethernet ports
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* Multiple USB ports (depending on variant)
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* Several gigabit ethernet or optical fiber ports (depending on
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variant)
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* Several display port inputs and outputs, and supporting redrivers
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(depending on variant)
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* Several FPGAs with custom logic (depending on variant)
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endchoice
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config MPC83XX_QUICC_ENGINE
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bool
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# TODO: Imply MPC83xx PCI driver
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config MPC83XX_PCI_SUPPORT
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bool
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# TODO: Imply TSEC driver
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config MPC83XX_TSEC1_SUPPORT
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bool
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config MPC83XX_TSEC2_SUPPORT
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bool
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config MPC83XX_PCIE1_SUPPORT
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bool
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config MPC83XX_PCIE2_SUPPORT
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bool
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config MPC83XX_SDHC_SUPPORT
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bool
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config MPC83XX_SATA_SUPPORT
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bool
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config MPC83XX_SECOND_I2C_SUPPORT
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bool
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config MPC83XX_LDP_PIN
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bool
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config ARCH_MPC830X
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bool
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select MPC83XX_SDHC_SUPPORT
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config ARCH_MPC8308
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bool
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select ARCH_MPC830X
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select MPC83XX_TSEC1_SUPPORT
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select MPC83XX_TSEC2_SUPPORT
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select MPC83XX_PCIE1_SUPPORT
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select MPC83XX_SECOND_I2C_SUPPORT
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config ARCH_MPC8309
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bool
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select ARCH_MPC830X
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select MPC83XX_QUICC_ENGINE
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_SECOND_I2C_SUPPORT
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config ARCH_MPC831X
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bool
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_TSEC1_SUPPORT
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select MPC83XX_TSEC2_SUPPORT
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config ARCH_MPC8313
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bool
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select ARCH_MPC831X
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select MPC83XX_SECOND_I2C_SUPPORT
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config ARCH_MPC8315
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bool
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select ARCH_MPC831X
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select MPC83XX_PCIE1_SUPPORT
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select MPC83XX_PCIE2_SUPPORT
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select MPC83XX_SATA_SUPPORT
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config ARCH_MPC832X
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bool
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select MPC83XX_QUICC_ENGINE
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select MPC83XX_PCI_SUPPORT
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config ARCH_MPC834X
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bool
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config ARCH_MPC8349
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bool
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select ARCH_MPC834X
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_TSEC1_SUPPORT
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select MPC83XX_TSEC2_SUPPORT
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select MPC83XX_LDP_PIN
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select MPC83XX_SECOND_I2C_SUPPORT
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config ARCH_MPC8360
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bool
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select MPC83XX_QUICC_ENGINE
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_LDP_PIN
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select MPC83XX_SECOND_I2C_SUPPORT
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config ARCH_MPC837X
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bool
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_TSEC1_SUPPORT
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select MPC83XX_TSEC2_SUPPORT
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select MPC83XX_PCIE1_SUPPORT
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select MPC83XX_PCIE2_SUPPORT
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select MPC83XX_SDHC_SUPPORT
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select MPC83XX_SATA_SUPPORT
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select MPC83XX_LDP_PIN
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select MPC83XX_SECOND_I2C_SUPPORT
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config SYS_IMMR
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hex "Value for IMMR"
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default 0xE0000000
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help
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Address for the Internal Memory-Mapped Registers (IMMR) window used
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to configure the features of the SoC.
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source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
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menu "Legacy options"
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if ARCH_MPC8349
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#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
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choice
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prompt "PMC slot configuration"
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config PCI_ALL_PCI1
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bool "All PMC slots on PCI1"
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config PCI_ONE_PCI1
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bool "First PMC1 on PCI1"
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config PCI_TWO_PCI1
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bool "First two PMC1 on PCI1"
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endchoice
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config PCI_64BIT
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bool "PMC2 is 64bit"
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endif
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endmenu
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source "board/esd/vme8349/Kconfig"
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source "board/freescale/mpc8308rdb/Kconfig"
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source "board/freescale/mpc8313erdb/Kconfig"
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@ -29,7 +29,9 @@ obj-y += interrupts.o
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obj-y += ecc.o
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obj-$(CONFIG_QE) += qe_io.o
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obj-$(CONFIG_FSL_SERDES) += serdes.o
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ifndef CONFIG_ARCH_MPC8308
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obj-$(CONFIG_PCI) += pci.o
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endif
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obj-$(CONFIG_PCIE) += pcie.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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|
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|
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139
arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
Normal file
139
arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
Normal file
@ -0,0 +1,139 @@
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menu "Arbiter"
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choice
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prompt "Pipeline depth"
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config ACR_PIPE_DEP_UNSET
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bool "Don't set value"
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config ACR_PIPE_DEP_1
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bool "1"
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config ACR_PIPE_DEP_2
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bool "2"
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config ACR_PIPE_DEP_3
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bool "3"
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|
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config ACR_PIPE_DEP_4
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bool "4"
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endchoice
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|
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choice
|
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prompt "Repeat count"
|
||||
|
||||
config ACR_RPTCNT_UNSET
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bool "Don't set value"
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|
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config ACR_RPTCNT_1
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bool "1"
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|
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config ACR_RPTCNT_2
|
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bool "2"
|
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|
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config ACR_RPTCNT_3
|
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bool "3"
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|
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config ACR_RPTCNT_4
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bool "4"
|
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|
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config ACR_RPTCNT_5
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bool "5"
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|
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config ACR_RPTCNT_6
|
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bool "6"
|
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|
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config ACR_RPTCNT_7
|
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bool "7"
|
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|
||||
config ACR_RPTCNT_8
|
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bool "8"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address parking"
|
||||
|
||||
config ACR_APARK_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config ACR_APARK_MASTER
|
||||
bool "Park to master"
|
||||
|
||||
config ACR_APARK_LAST
|
||||
bool "Park to last owner"
|
||||
|
||||
config ACR_APARK_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Parking master"
|
||||
|
||||
config ACR_PARKM_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config ACR_PARKM_E300
|
||||
bool "e300 core"
|
||||
|
||||
config ACR_PARKM_TSEC_1_2
|
||||
bool "TSEC1, TSEC2"
|
||||
|
||||
config ACR_PARKM_USB_I2C1_BOOT
|
||||
bool "USB/I2C1_BOOT"
|
||||
|
||||
config ACR_PARKM_DMA_ESDHC_USB
|
||||
bool "DMA, ESDHC, USB"
|
||||
|
||||
config ACR_PARKM_PEX
|
||||
bool "PCI Express"
|
||||
|
||||
if MPC83XX_QUICC_ENGINE
|
||||
|
||||
config ACR_PARKM_ENC_CORE
|
||||
bool "Encryption core"
|
||||
|
||||
endif
|
||||
|
||||
endchoice
|
||||
|
||||
config ACR_PIPE_DEP
|
||||
hex
|
||||
default 0x0 if ACR_PIPE_DEP_UNSET
|
||||
default 0x0 if ACR_PIPE_DEP_1
|
||||
default 0x10000 if ACR_PIPE_DEP_2
|
||||
default 0x20000 if ACR_PIPE_DEP_3
|
||||
default 0x30000 if ACR_PIPE_DEP_4
|
||||
|
||||
config ACR_RPTCNT
|
||||
hex
|
||||
default 0x0 if ACR_RPTCNT_UNSET
|
||||
default 0x0 if ACR_RPTCNT_1
|
||||
default 0x100 if ACR_RPTCNT_2
|
||||
default 0x200 if ACR_RPTCNT_3
|
||||
default 0x300 if ACR_RPTCNT_4
|
||||
default 0x400 if ACR_RPTCNT_5
|
||||
default 0x500 if ACR_RPTCNT_6
|
||||
default 0x600 if ACR_RPTCNT_7
|
||||
default 0x700 if ACR_RPTCNT_8
|
||||
|
||||
config ACR_APARK
|
||||
hex
|
||||
default 0x0 if ACR_APARK_UNSET
|
||||
default 0x0 if ACR_APARK_MASTER
|
||||
default 0x10 if ACR_APARK_LAST
|
||||
default 0x20 if ACR_APARK_DISABLE
|
||||
|
||||
config ACR_PARKM
|
||||
hex
|
||||
default 0x0 if ACR_PARKM_UNSET
|
||||
default 0x0 if ACR_PARKM_E300
|
||||
default 0x2 if ACR_PARKM_TSEC_1_2
|
||||
default 0x3 if ACR_PARKM_USB_I2C1_BOOT
|
||||
default 0x4 if ACR_PARKM_DMA_ESDHC_USB
|
||||
default 0x5 if ACR_PARKM_PEX
|
||||
default 0x5 if ACR_PARKM_ENC_CORE
|
||||
|
||||
endmenu
|
||||
28
arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
Normal file
28
arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
Normal file
@ -0,0 +1,28 @@
|
||||
const __be32 acr_mask =
|
||||
#ifndef CONFIG_ACR_PIPE_DEP_UNSET
|
||||
ACR_PIPE_DEP |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_RPTCNT_UNSET
|
||||
ACR_RPTCNT |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_APARK_UNSET
|
||||
ACR_APARK |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_PARKM_UNSET
|
||||
ACR_PARKM |
|
||||
#endif
|
||||
0;
|
||||
const __be32 acr_val =
|
||||
#ifndef CONFIG_ACR_PIPE_DEP_UNSET
|
||||
CONFIG_ACR_PIPE_DEP |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_RPTCNT_UNSET
|
||||
CONFIG_ACR_RPTCNT |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_APARK_UNSET
|
||||
CONFIG_ACR_APARK |
|
||||
#endif
|
||||
#ifndef CONFIG_ACR_PARKM_UNSET
|
||||
CONFIG_ACR_PARKM |
|
||||
#endif
|
||||
0;
|
||||
1311
arch/powerpc/cpu/mpc83xx/bats/Kconfig
Normal file
1311
arch/powerpc/cpu/mpc83xx/bats/Kconfig
Normal file
File diff suppressed because it is too large
Load Diff
223
arch/powerpc/cpu/mpc83xx/bats/bats.h
Normal file
223
arch/powerpc/cpu/mpc83xx/bats/bats.h
Normal file
@ -0,0 +1,223 @@
|
||||
#ifdef CONFIG_BAT0
|
||||
#define CONFIG_SYS_IBAT0L (\
|
||||
(CONFIG_BAT0_BASE) |\
|
||||
(CONFIG_BAT0_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT0_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT0U (\
|
||||
(CONFIG_BAT0_BASE) |\
|
||||
(CONFIG_BAT0_LENGTH) |\
|
||||
(CONFIG_BAT0_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT0L (\
|
||||
(CONFIG_BAT0_BASE) |\
|
||||
(CONFIG_BAT0_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT0_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT0U (\
|
||||
(CONFIG_BAT0_BASE) |\
|
||||
(CONFIG_BAT0_LENGTH) |\
|
||||
(CONFIG_BAT0_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT0L (0)
|
||||
#define CONFIG_SYS_IBAT0U (0)
|
||||
#define CONFIG_SYS_DBAT0L (0)
|
||||
#define CONFIG_SYS_DBAT0U (0)
|
||||
#endif /* CONFIG_BAT0 */
|
||||
|
||||
#ifdef CONFIG_BAT1
|
||||
#define CONFIG_SYS_IBAT1L (\
|
||||
(CONFIG_BAT1_BASE) |\
|
||||
(CONFIG_BAT1_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT1_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT1U (\
|
||||
(CONFIG_BAT1_BASE) |\
|
||||
(CONFIG_BAT1_LENGTH) |\
|
||||
(CONFIG_BAT1_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT1L (\
|
||||
(CONFIG_BAT1_BASE) |\
|
||||
(CONFIG_BAT1_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT1_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT1U (\
|
||||
(CONFIG_BAT1_BASE) |\
|
||||
(CONFIG_BAT1_LENGTH) |\
|
||||
(CONFIG_BAT1_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (0)
|
||||
#define CONFIG_SYS_IBAT1U (0)
|
||||
#define CONFIG_SYS_DBAT1L (0)
|
||||
#define CONFIG_SYS_DBAT1U (0)
|
||||
#endif /* CONFIG_BAT1 */
|
||||
|
||||
#ifdef CONFIG_BAT2
|
||||
#define CONFIG_SYS_IBAT2L (\
|
||||
(CONFIG_BAT2_BASE) |\
|
||||
(CONFIG_BAT2_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT2_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT2U (\
|
||||
(CONFIG_BAT2_BASE) |\
|
||||
(CONFIG_BAT2_LENGTH) |\
|
||||
(CONFIG_BAT2_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT2L (\
|
||||
(CONFIG_BAT2_BASE) |\
|
||||
(CONFIG_BAT2_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT2_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT2U (\
|
||||
(CONFIG_BAT2_BASE) |\
|
||||
(CONFIG_BAT2_LENGTH) |\
|
||||
(CONFIG_BAT2_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT2L (0)
|
||||
#define CONFIG_SYS_IBAT2U (0)
|
||||
#define CONFIG_SYS_DBAT2L (0)
|
||||
#define CONFIG_SYS_DBAT2U (0)
|
||||
#endif /* CONFIG_BAT2 */
|
||||
|
||||
#ifdef CONFIG_BAT3
|
||||
#define CONFIG_SYS_IBAT3L (\
|
||||
(CONFIG_BAT3_BASE) |\
|
||||
(CONFIG_BAT3_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT3_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT3U (\
|
||||
(CONFIG_BAT3_BASE) |\
|
||||
(CONFIG_BAT3_LENGTH) |\
|
||||
(CONFIG_BAT3_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT3L (\
|
||||
(CONFIG_BAT3_BASE) |\
|
||||
(CONFIG_BAT3_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT3_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT3U (\
|
||||
(CONFIG_BAT3_BASE) |\
|
||||
(CONFIG_BAT3_LENGTH) |\
|
||||
(CONFIG_BAT3_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT3L (0)
|
||||
#define CONFIG_SYS_IBAT3U (0)
|
||||
#define CONFIG_SYS_DBAT3L (0)
|
||||
#define CONFIG_SYS_DBAT3U (0)
|
||||
#endif /* CONFIG_BAT3 */
|
||||
|
||||
#ifdef CONFIG_BAT4
|
||||
#define CONFIG_SYS_IBAT4L (\
|
||||
(CONFIG_BAT4_BASE) |\
|
||||
(CONFIG_BAT4_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT4_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT4U (\
|
||||
(CONFIG_BAT4_BASE) |\
|
||||
(CONFIG_BAT4_LENGTH) |\
|
||||
(CONFIG_BAT4_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT4L (\
|
||||
(CONFIG_BAT4_BASE) |\
|
||||
(CONFIG_BAT4_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT4_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT4U (\
|
||||
(CONFIG_BAT4_BASE) |\
|
||||
(CONFIG_BAT4_LENGTH) |\
|
||||
(CONFIG_BAT4_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT4L (0)
|
||||
#define CONFIG_SYS_IBAT4U (0)
|
||||
#define CONFIG_SYS_DBAT4L (0)
|
||||
#define CONFIG_SYS_DBAT4U (0)
|
||||
#endif /* CONFIG_BAT4 */
|
||||
|
||||
#ifdef CONFIG_BAT5
|
||||
#define CONFIG_SYS_IBAT5L (\
|
||||
(CONFIG_BAT5_BASE) |\
|
||||
(CONFIG_BAT5_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT5_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT5U (\
|
||||
(CONFIG_BAT5_BASE) |\
|
||||
(CONFIG_BAT5_LENGTH) |\
|
||||
(CONFIG_BAT5_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT5L (\
|
||||
(CONFIG_BAT5_BASE) |\
|
||||
(CONFIG_BAT5_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT5_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT5U (\
|
||||
(CONFIG_BAT5_BASE) |\
|
||||
(CONFIG_BAT5_LENGTH) |\
|
||||
(CONFIG_BAT5_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT5L (0)
|
||||
#define CONFIG_SYS_IBAT5U (0)
|
||||
#define CONFIG_SYS_DBAT5L (0)
|
||||
#define CONFIG_SYS_DBAT5U (0)
|
||||
#endif /* CONFIG_BAT5 */
|
||||
|
||||
#ifdef CONFIG_BAT6
|
||||
#define CONFIG_SYS_IBAT6L (\
|
||||
(CONFIG_BAT6_BASE) |\
|
||||
(CONFIG_BAT6_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT6_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT6U (\
|
||||
(CONFIG_BAT6_BASE) |\
|
||||
(CONFIG_BAT6_LENGTH) |\
|
||||
(CONFIG_BAT6_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT6L (\
|
||||
(CONFIG_BAT6_BASE) |\
|
||||
(CONFIG_BAT6_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT6_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT6U (\
|
||||
(CONFIG_BAT6_BASE) |\
|
||||
(CONFIG_BAT6_LENGTH) |\
|
||||
(CONFIG_BAT6_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT6L (0)
|
||||
#define CONFIG_SYS_IBAT6U (0)
|
||||
#define CONFIG_SYS_DBAT6L (0)
|
||||
#define CONFIG_SYS_DBAT6U (0)
|
||||
#endif /* CONFIG_BAT6 */
|
||||
|
||||
#ifdef CONFIG_BAT7
|
||||
#define CONFIG_SYS_IBAT7L (\
|
||||
(CONFIG_BAT7_BASE) |\
|
||||
(CONFIG_BAT7_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT7_WIMG_ICACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_IBAT7U (\
|
||||
(CONFIG_BAT7_BASE) |\
|
||||
(CONFIG_BAT7_LENGTH) |\
|
||||
(CONFIG_BAT7_VALID_BITS) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT7L (\
|
||||
(CONFIG_BAT7_BASE) |\
|
||||
(CONFIG_BAT7_PAGE_PROTECTION) |\
|
||||
(CONFIG_BAT7_WIMG_DCACHE) \
|
||||
)
|
||||
#define CONFIG_SYS_DBAT7U (\
|
||||
(CONFIG_BAT7_BASE) |\
|
||||
(CONFIG_BAT7_LENGTH) |\
|
||||
(CONFIG_BAT7_VALID_BITS) \
|
||||
)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
#define CONFIG_SYS_DBAT7L (0)
|
||||
#define CONFIG_SYS_DBAT7U (0)
|
||||
#endif /* CONFIG_BAT7 */
|
||||
@ -18,7 +18,7 @@
|
||||
#include <tsec.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
|
||||
#include <linux/immap_qe.h>
|
||||
#include <asm/io.h>
|
||||
#endif
|
||||
@ -133,18 +133,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
#ifdef MPC83xx_RESET
|
||||
|
||||
/* Interrupts and MMU off */
|
||||
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
|
||||
|
||||
msr &= ~( MSR_EE | MSR_IR | MSR_DR);
|
||||
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
|
||||
msr = mfmsr();
|
||||
msr &= ~(MSR_EE | MSR_IR | MSR_DR);
|
||||
mtmsr(msr);
|
||||
|
||||
/* enable Reset Control Reg */
|
||||
immap->reset.rpr = 0x52535445;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* confirm Reset Control Reg is enabled */
|
||||
while(!((immap->reset.rcer) & RCER_CRE));
|
||||
while(!((immap->reset.rcer) & RCER_CRE))
|
||||
;
|
||||
|
||||
udelay(200);
|
||||
|
||||
@ -156,10 +156,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
|
||||
|
||||
/* Interrupts and MMU off */
|
||||
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
|
||||
|
||||
msr = mfmsr();
|
||||
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
|
||||
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
|
||||
mtmsr(msr);
|
||||
|
||||
/*
|
||||
* Trying to execute the next instruction at a non-existing address
|
||||
@ -199,6 +198,7 @@ void watchdog_reset (void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DM_ETH
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
@ -214,6 +214,7 @@ int cpu_eth_init(bd_t *bis)
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif /* !CONFIG_DM_ETH */
|
||||
|
||||
/*
|
||||
* Initializes on-chip MMC controllers.
|
||||
@ -227,3 +228,21 @@ int cpu_mmc_init(bd_t *bis)
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void ppcDWstore(unsigned int *addr, unsigned int *value)
|
||||
{
|
||||
asm("lfd 1, 0(%1)\n\t"
|
||||
"stfd 1, 0(%0)"
|
||||
:
|
||||
: "r" (addr), "r" (value)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
void ppcDWload(unsigned int *addr, unsigned int *ret)
|
||||
{
|
||||
asm("lfd 1, 0(%0)\n\t"
|
||||
"stfd 1, 0(%1)"
|
||||
:
|
||||
: "r" (addr), "r" (ret)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
@ -12,6 +12,12 @@
|
||||
#include <usb/ehci-ci.h>
|
||||
#endif
|
||||
|
||||
#include "lblaw/lblaw.h"
|
||||
#include "elbc/elbc.h"
|
||||
#include "sysio/sysio.h"
|
||||
#include "arbiter/arbiter.h"
|
||||
#include "initreg/initreg.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
@ -47,62 +53,6 @@ static void config_qe_ioports(void)
|
||||
*/
|
||||
void cpu_init_f (volatile immap_t * im)
|
||||
{
|
||||
__be32 acr_mask =
|
||||
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
|
||||
ACR_PIPE_DEP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
|
||||
ACR_RPTCNT |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
|
||||
ACR_APARK |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
|
||||
ACR_PARKM |
|
||||
#endif
|
||||
0;
|
||||
__be32 acr_val =
|
||||
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
|
||||
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
|
||||
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
|
||||
(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
|
||||
(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
|
||||
#endif
|
||||
0;
|
||||
__be32 spcr_mask =
|
||||
#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
|
||||
SPCR_OPT |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
|
||||
SPCR_TSECEP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
|
||||
SPCR_TSEC1EP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
|
||||
SPCR_TSEC2EP |
|
||||
#endif
|
||||
0;
|
||||
__be32 spcr_val =
|
||||
#ifdef CONFIG_SYS_SPCR_OPT
|
||||
(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
|
||||
(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
|
||||
(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
|
||||
(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
|
||||
#endif
|
||||
0;
|
||||
__be32 sccr_mask =
|
||||
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
|
||||
SCCR_ENCCM |
|
||||
@ -177,28 +127,6 @@ void cpu_init_f (volatile immap_t * im)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
|
||||
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
|
||||
#endif
|
||||
0;
|
||||
__be32 lcrr_mask =
|
||||
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
|
||||
LCRR_DBYP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
|
||||
LCRR_EADC |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
|
||||
LCRR_CLKDIV |
|
||||
#endif
|
||||
0;
|
||||
__be32 lcrr_val =
|
||||
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
|
||||
CONFIG_SYS_LCRR_DBYP |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_LCRR_EADC
|
||||
CONFIG_SYS_LCRR_EADC |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
|
||||
CONFIG_SYS_LCRR_CLKDIV |
|
||||
#endif
|
||||
0;
|
||||
|
||||
@ -240,7 +168,7 @@ void cpu_init_f (volatile immap_t * im)
|
||||
|
||||
/* System General Purpose Register */
|
||||
#ifdef CONFIG_SYS_SICRH
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
|
||||
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
|
||||
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
|
||||
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
|
||||
&im->sysconf.sicrh);
|
||||
@ -312,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
|
||||
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
|
||||
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
|
||||
#endif
|
||||
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
|
||||
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
|
||||
uint32_t temp;
|
||||
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
|
||||
|
||||
|
||||
@ -191,8 +191,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
}
|
||||
|
||||
ddr->err_disable = val;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) {
|
||||
val = ddr->err_detect;
|
||||
@ -249,8 +249,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
printf("Incorrect command\n");
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "mirror") == 0) {
|
||||
val = ddr->ecc_err_inject;
|
||||
@ -282,26 +282,26 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
/* enable injects */
|
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* write memory location injecting errors */
|
||||
ppcDWstore((u32 *) i, pattern);
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
|
||||
/* disable injects */
|
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* read data, this generates ECC error */
|
||||
ppcDWload((u32 *) i, ret);
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
|
||||
/* re-initialize memory, double word write the location again,
|
||||
* generates new ECC code this time */
|
||||
ppcDWstore((u32 *) i, writeback);
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
}
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
@ -321,29 +321,29 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
/* enable injects */
|
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* write memory location injecting errors */
|
||||
*(u32 *) i = 0xfedcba98UL;
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
|
||||
/* sub double word write,
|
||||
* bus will read-modify-write,
|
||||
* generates ECC error */
|
||||
*((u32 *) i + 1) = 0x76543210UL;
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
|
||||
/* disable injects */
|
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* re-initialize memory,
|
||||
* double word write the location again,
|
||||
* generates new ECC code this time */
|
||||
ppcDWstore((u32 *) i, writeback);
|
||||
__asm__ __volatile__("sync");
|
||||
sync();
|
||||
}
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
|
||||
32
arch/powerpc/cpu/mpc83xx/elbc/Kconfig
Normal file
32
arch/powerpc/cpu/mpc83xx/elbc/Kconfig
Normal file
@ -0,0 +1,32 @@
|
||||
menu "ELBC register setup"
|
||||
|
||||
choice
|
||||
prompt "OR/BR for NAND SPL"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_NONE
|
||||
bool "None"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_0
|
||||
bool "0"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_1
|
||||
bool "1"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_2
|
||||
bool "2"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_3
|
||||
bool "3"
|
||||
|
||||
config ELBC_BR_OR_NAND_PRELIM_4
|
||||
bool "4"
|
||||
|
||||
endchoice
|
||||
|
||||
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
|
||||
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
|
||||
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
|
||||
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
|
||||
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
|
||||
|
||||
endmenu
|
||||
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
Normal file
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
Normal file
@ -0,0 +1,733 @@
|
||||
menuconfig ELBC_BR0_OR0
|
||||
bool "ELBC BR0/OR0"
|
||||
|
||||
if ELBC_BR0_OR0
|
||||
|
||||
config BR0_OR0_NAME
|
||||
string "Identifier"
|
||||
|
||||
config BR0_OR0_BASE
|
||||
hex "Port base"
|
||||
|
||||
choice
|
||||
prompt "Port size"
|
||||
|
||||
config BR0_PORTSIZE_8BIT
|
||||
bool "8-bit"
|
||||
|
||||
config BR0_PORTSIZE_16BIT
|
||||
depends on !BR0_MACHINE_FCM
|
||||
bool "16-bit"
|
||||
|
||||
|
||||
config BR0_PORTSIZE_32BIT
|
||||
depends on !BR0_MACHINE_FCM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
bool "32-bit"
|
||||
|
||||
endchoice
|
||||
|
||||
if BR0_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Data Error Checking"
|
||||
|
||||
config BR0_ERRORCHECKING_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BR0_ERRORCHECKING_ECC_CHECKING
|
||||
bool "ECC checking / No ECC generation"
|
||||
|
||||
config BR0_ERRORCHECKING_BOTH
|
||||
bool "ECC checking and generation"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config BR0_WRITE_PROTECT
|
||||
bool "Write-protect"
|
||||
|
||||
config BR0_MACHINE_UPM
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Machine select"
|
||||
|
||||
config BR0_MACHINE_GPCM
|
||||
bool "GPCM"
|
||||
|
||||
config BR0_MACHINE_FCM
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "FCM"
|
||||
|
||||
config BR0_MACHINE_SDRAM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360
|
||||
bool "SDRAM"
|
||||
|
||||
config BR0_MACHINE_UPMA
|
||||
select BR0_MACHINE_UPM
|
||||
bool "UPM (A)"
|
||||
|
||||
config BR0_MACHINE_UPMB
|
||||
select BR0_MACHINE_UPM
|
||||
bool "UPM (B)"
|
||||
|
||||
config BR0_MACHINE_UPMC
|
||||
select BR0_MACHINE_UPM
|
||||
bool "UPM (C)"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Atomic operations"
|
||||
|
||||
config BR0_ATOMIC_NONE
|
||||
bool "No atomic operations"
|
||||
|
||||
config BR0_ATOMIC_RAWA
|
||||
bool "Read-after-write-atomic"
|
||||
|
||||
config BR0_ATOMIC_WARA
|
||||
bool "Write-after-read-atomic"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Address mask"
|
||||
|
||||
config OR0_AM_32_KBYTES
|
||||
depends on !BR0_MACHINE_SDRAM
|
||||
bool "32 kb"
|
||||
|
||||
config OR0_AM_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config OR0_AM_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config OR0_AM_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config OR0_AM_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config OR0_AM_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config OR0_AM_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config OR0_AM_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config OR0_AM_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config OR0_AM_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config OR0_AM_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config OR0_AM_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
# XXX: Some boards define 128MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR0_AM_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
# XXX: Some boards define 256MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR0_AM_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config OR0_AM_512_MBYTES
|
||||
depends on BR0_MACHINE_FCM
|
||||
bool "512 mb"
|
||||
|
||||
# XXX: Some boards define 1GB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR0_AM_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config OR0_AM_2_GBYTES
|
||||
depends on BR0_MACHINE_FCM
|
||||
bool "2 gb"
|
||||
|
||||
config OR0_AM_4_GBYTES
|
||||
depends on BR0_MACHINE_FCM
|
||||
bool "4 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
config OR0_XAM_SET
|
||||
bool "Set unused bytes after address mask"
|
||||
choice
|
||||
prompt "Buffer control disable"
|
||||
|
||||
config OR0_BCTLD_ASSERTED
|
||||
bool "Asserted"
|
||||
|
||||
config OR0_BCTLD_NOT_ASSERTED
|
||||
bool "Not asserted"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Cycle length in bus clocks"
|
||||
|
||||
config OR0_SCY_0
|
||||
bool "No wait states"
|
||||
|
||||
config OR0_SCY_1
|
||||
bool "1 wait state"
|
||||
|
||||
config OR0_SCY_2
|
||||
bool "2 wait states"
|
||||
|
||||
config OR0_SCY_3
|
||||
bool "3 wait states"
|
||||
|
||||
config OR0_SCY_4
|
||||
bool "4 wait states"
|
||||
|
||||
config OR0_SCY_5
|
||||
bool "5 wait states"
|
||||
|
||||
config OR0_SCY_6
|
||||
bool "6 wait states"
|
||||
|
||||
config OR0_SCY_7
|
||||
bool "7 wait states"
|
||||
|
||||
config OR0_SCY_8
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "8 wait states"
|
||||
|
||||
config OR0_SCY_9
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "9 wait states"
|
||||
|
||||
config OR0_SCY_10
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "10 wait states"
|
||||
|
||||
config OR0_SCY_11
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "11 wait states"
|
||||
|
||||
config OR0_SCY_12
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "12 wait states"
|
||||
|
||||
config OR0_SCY_13
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "13 wait states"
|
||||
|
||||
config OR0_SCY_14
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "14 wait states"
|
||||
|
||||
config OR0_SCY_15
|
||||
depends on BR0_MACHINE_GPCM
|
||||
bool "15 wait states"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
|
||||
|
||||
if BR0_MACHINE_GPCM
|
||||
|
||||
choice
|
||||
prompt "Chip select negotiation time"
|
||||
|
||||
config OR0_CSNT_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR0_CSNT_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address to chip-select setup"
|
||||
|
||||
config OR0_ACS_SAME_TIME
|
||||
bool "At the same time"
|
||||
|
||||
config OR0_ACS_HALF_CYCLE_EARLIER
|
||||
bool "Half of a bus clock cycle earlier"
|
||||
|
||||
config OR0_ACS_QUARTER_CYCLE_EARLIER
|
||||
bool "Half/Quarter of a bus clock cycle earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extra address to check-select setup"
|
||||
|
||||
config OR0_XACS_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR0_XACS_EXTENDED
|
||||
bool "Extended"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "External address termination"
|
||||
|
||||
config OR0_SETA_INTERNAL
|
||||
bool "Access is terminated internally"
|
||||
|
||||
config OR0_SETA_EXTERNAL
|
||||
bool "Access is terminated externally"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR0_MACHINE_GPCM
|
||||
|
||||
if BR0_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "NAND Flash EEPROM page size"
|
||||
|
||||
config OR0_PGS_SMALL
|
||||
bool "Small page device"
|
||||
|
||||
config OR0_PGS_LARGE
|
||||
bool "Large page device"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Chip select to command time"
|
||||
|
||||
config OR0_CSCT_1_CYCLE
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "1 cycle"
|
||||
|
||||
config OR0_CSCT_2_CYCLE
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "2 cycles"
|
||||
|
||||
config OR0_CSCT_4_CYCLE
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "4 cycles"
|
||||
|
||||
config OR0_CSCT_8_CYCLE
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "8 cycles"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command setup time"
|
||||
|
||||
config OR0_CST_COINCIDENT
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "Coincident with any command"
|
||||
|
||||
config OR0_CST_QUARTER_CLOCK
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "0.25 clocks after"
|
||||
|
||||
config OR0_CST_HALF_CLOCK
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "0.5 clocks after"
|
||||
|
||||
config OR0_CST_ONE_CLOCK
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "1 clock after"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command hold time"
|
||||
|
||||
config OR0_CHT_HALF_CLOCK
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "0.5 clocks before"
|
||||
|
||||
config OR0_CHT_ONE_CLOCK
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "1 clock before"
|
||||
|
||||
config OR0_CHT_ONE_HALF_CLOCK
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "1.5 clocks before"
|
||||
|
||||
config OR0_CHT_TWO_CLOCK
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "2 clocks before"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Reset setup time"
|
||||
|
||||
config OR0_RST_THREE_QUARTER_CLOCK
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "0.75 clocks prior"
|
||||
|
||||
config OR0_RST_ONE_HALF_CLOCK
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "0.5 clocks prior"
|
||||
|
||||
config OR0_RST_ONE_CLOCK
|
||||
bool "1 clock prior"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR0_MACHINE_FCM
|
||||
|
||||
if BR0_MACHINE_UPM
|
||||
|
||||
choice
|
||||
prompt "Burst inhibit"
|
||||
|
||||
config OR0_BI_BURSTSUPPORT
|
||||
bool "Support burst access"
|
||||
|
||||
config OR0_BI_BURSTINHIBIT
|
||||
bool "Inhibit burst access"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR0_MACHINE_UPM
|
||||
|
||||
if BR0_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Number of column address lines"
|
||||
|
||||
config OR0_COLS_7
|
||||
bool "7"
|
||||
|
||||
config OR0_COLS_8
|
||||
bool "8"
|
||||
|
||||
config OR0_COLS_9
|
||||
bool "9"
|
||||
|
||||
config OR0_COLS_10
|
||||
bool "10"
|
||||
|
||||
config OR0_COLS_11
|
||||
bool "11"
|
||||
|
||||
config OR0_COLS_12
|
||||
bool "12"
|
||||
|
||||
config OR0_COLS_13
|
||||
bool "13"
|
||||
|
||||
config OR0_COLS_14
|
||||
bool "14"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Number of rows address lines"
|
||||
|
||||
config OR0_ROWS_9
|
||||
bool "9"
|
||||
|
||||
config OR0_ROWS_10
|
||||
bool "10"
|
||||
|
||||
config OR0_ROWS_11
|
||||
bool "11"
|
||||
|
||||
config OR0_ROWS_12
|
||||
bool "12"
|
||||
|
||||
config OR0_ROWS_13
|
||||
bool "13"
|
||||
|
||||
config OR0_ROWS_14
|
||||
bool "14"
|
||||
|
||||
config OR0_ROWS_15
|
||||
bool "15"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Page mode select"
|
||||
|
||||
config OR0_PMSEL_BTB
|
||||
bool "Back-to-back"
|
||||
|
||||
config OR0_PMSEL_KEPT_OPEN
|
||||
bool "Page kept open until page miss or refresh"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR0_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Relaxed timing"
|
||||
|
||||
config OR0_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR0_TRLX_RELAXED
|
||||
bool "Relaxed"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended hold time"
|
||||
|
||||
config OR0_EHTR_NORMAL
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR0_EHTR_1_CYCLE
|
||||
depends on OR0_TRLX_NORMAL
|
||||
bool "1 idle clock cycle inserted"
|
||||
|
||||
config OR0_EHTR_4_CYCLE
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "4 idle clock cycles inserted"
|
||||
|
||||
config OR0_EHTR_8_CYCLE
|
||||
depends on OR0_TRLX_RELAXED
|
||||
bool "8 idle clock cycles inserted"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address latch delay"
|
||||
|
||||
config OR0_EAD_NONE
|
||||
bool "None"
|
||||
|
||||
config OR0_EAD_EXTRA
|
||||
bool "Extra"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
endif # ELBC_BR0_OR0
|
||||
|
||||
config BR0_PORTSIZE
|
||||
hex
|
||||
default 0x800 if BR0_PORTSIZE_8BIT
|
||||
default 0x1000 if BR0_PORTSIZE_16BIT
|
||||
default 0x1800 if BR0_PORTSIZE_32BIT
|
||||
|
||||
config BR0_ERRORCHECKING
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if BR0_ERRORCHECKING_DISABLED
|
||||
default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
|
||||
default 0x400 if BR0_ERRORCHECKING_BOTH
|
||||
|
||||
config BR0_WRITE_PROTECT_BIT
|
||||
hex
|
||||
default 0x0 if !BR0_WRITE_PROTECT
|
||||
default 0x100 if BR0_WRITE_PROTECT
|
||||
|
||||
config BR0_MACHINE
|
||||
hex
|
||||
default 0x0 if BR0_MACHINE_GPCM
|
||||
default 0x20 if BR0_MACHINE_FCM
|
||||
default 0x60 if BR0_MACHINE_SDRAM
|
||||
default 0x80 if BR0_MACHINE_UPMA
|
||||
default 0xa0 if BR0_MACHINE_UPMB
|
||||
default 0xc0 if BR0_MACHINE_UPMC
|
||||
|
||||
config BR0_ATOMIC
|
||||
hex
|
||||
default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
|
||||
default 0x0 if BR0_ATOMIC_NONE
|
||||
default 0x4 if BR0_ATOMIC_RAWA
|
||||
default 0x8 if BR0_ATOMIC_WARA
|
||||
|
||||
config BR0_VALID_BIT
|
||||
hex
|
||||
default 0x0 if !ELBC_BR0_OR0
|
||||
default 0x1 if ELBC_BR0_OR0
|
||||
|
||||
config OR0_AM
|
||||
hex
|
||||
default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
|
||||
default 0xffff0000 if OR0_AM_64_KBYTES
|
||||
default 0xfffe0000 if OR0_AM_128_KBYTES
|
||||
default 0xfffc0000 if OR0_AM_256_KBYTES
|
||||
default 0xfff80000 if OR0_AM_512_KBYTES
|
||||
default 0xfff00000 if OR0_AM_1_MBYTES
|
||||
default 0xffe00000 if OR0_AM_2_MBYTES
|
||||
default 0xffc00000 if OR0_AM_4_MBYTES
|
||||
default 0xff800000 if OR0_AM_8_MBYTES
|
||||
default 0xff000000 if OR0_AM_16_MBYTES
|
||||
default 0xfe000000 if OR0_AM_32_MBYTES
|
||||
default 0xfc000000 if OR0_AM_64_MBYTES
|
||||
default 0xf8000000 if OR0_AM_128_MBYTES
|
||||
default 0xf0000000 if OR0_AM_256_MBYTES
|
||||
default 0xe0000000 if OR0_AM_512_MBYTES
|
||||
default 0xc0000000 if OR0_AM_1_GBYTES
|
||||
default 0x80000000 if OR0_AM_2_GBYTES
|
||||
default 0x00000000 if OR0_AM_4_GBYTES
|
||||
|
||||
config OR0_XAM
|
||||
hex
|
||||
default 0x0 if !OR0_XAM_SET
|
||||
default 0x6000 if OR0_XAM_SET
|
||||
|
||||
config OR0_BCTLD
|
||||
hex
|
||||
default 0x0 if OR0_BCTLD_ASSERTED
|
||||
default 0x1000 if OR0_BCTLD_NOT_ASSERTED
|
||||
|
||||
config OR0_BI
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_UPM
|
||||
default 0x0 if OR0_BI_BURSTSUPPORT
|
||||
default 0x100 if OR0_BI_BURSTINHIBIT
|
||||
|
||||
config OR0_COLS
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_SDRAM
|
||||
default 0x0 if OR0_COLS_7
|
||||
default 0x400 if OR0_COLS_8
|
||||
default 0x800 if OR0_COLS_9
|
||||
default 0xc00 if OR0_COLS_10
|
||||
default 0x1000 if OR0_COLS_11
|
||||
default 0x1400 if OR0_COLS_12
|
||||
default 0x1800 if OR0_COLS_13
|
||||
default 0x1c00 if OR0_COLS_14
|
||||
|
||||
config OR0_ROWS
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_SDRAM
|
||||
default 0x0 if OR0_ROWS_9
|
||||
default 0x40 if OR0_ROWS_10
|
||||
default 0x80 if OR0_ROWS_11
|
||||
default 0xc0 if OR0_ROWS_12
|
||||
default 0x100 if OR0_ROWS_13
|
||||
default 0x140 if OR0_ROWS_14
|
||||
default 0x180 if OR0_ROWS_15
|
||||
|
||||
config OR0_PMSEL
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_SDRAM
|
||||
default 0x0 if OR0_PMSEL_BTB
|
||||
default 0x20 if OR0_PMSEL_KEPT_OPEN
|
||||
|
||||
config OR0_SCY
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_SCY_0
|
||||
default 0x10 if OR0_SCY_1
|
||||
default 0x20 if OR0_SCY_2
|
||||
default 0x30 if OR0_SCY_3
|
||||
default 0x40 if OR0_SCY_4
|
||||
default 0x50 if OR0_SCY_5
|
||||
default 0x60 if OR0_SCY_6
|
||||
default 0x70 if OR0_SCY_7
|
||||
default 0x80 if OR0_SCY_8
|
||||
default 0x90 if OR0_SCY_9
|
||||
default 0xa0 if OR0_SCY_10
|
||||
default 0xb0 if OR0_SCY_11
|
||||
default 0xc0 if OR0_SCY_12
|
||||
default 0xd0 if OR0_SCY_13
|
||||
default 0xe0 if OR0_SCY_14
|
||||
default 0xf0 if OR0_SCY_15
|
||||
|
||||
config OR0_PGS
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_PGS_SMALL
|
||||
default 0x400 if OR0_PGS_LARGE
|
||||
|
||||
config OR0_CSCT
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_CSCT_1_CYCLE
|
||||
default 0x0 if OR0_CSCT_2_CYCLE
|
||||
default 0x200 if OR0_CSCT_4_CYCLE
|
||||
default 0x200 if OR0_CSCT_8_CYCLE
|
||||
|
||||
config OR0_CST
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_CST_COINCIDENT
|
||||
default 0x100 if OR0_CST_QUARTER_CLOCK
|
||||
default 0x0 if OR0_CST_HALF_CLOCK
|
||||
default 0x100 if OR0_CST_ONE_CLOCK
|
||||
|
||||
config OR0_CHT
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_CHT_HALF_CLOCK
|
||||
default 0x80 if OR0_CHT_ONE_CLOCK
|
||||
default 0x0 if OR0_CHT_ONE_HALF_CLOCK
|
||||
default 0x80 if OR0_CHT_TWO_CLOCK
|
||||
|
||||
config OR0_RST
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_FCM
|
||||
default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
|
||||
default 0x8 if OR0_RST_ONE_CLOCK
|
||||
default 0x0 if OR0_RST_ONE_HALF_CLOCK
|
||||
|
||||
config OR0_CSNT
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_GPCM
|
||||
default 0x0 if OR0_CSNT_NORMAL
|
||||
default 0x800 if OR0_CSNT_EARLIER
|
||||
|
||||
config OR0_ACS
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_GPCM
|
||||
default 0x0 if OR0_ACS_SAME_TIME
|
||||
default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
|
||||
default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
|
||||
|
||||
config OR0_XACS
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_GPCM
|
||||
default 0x0 if OR0_XACS_NORMAL
|
||||
default 0x100 if OR0_XACS_EXTENDED
|
||||
|
||||
config OR0_SETA
|
||||
hex
|
||||
default 0x0 if !BR0_MACHINE_GPCM
|
||||
default 0x0 if OR0_SETA_INTERNAL
|
||||
default 0x8 if OR0_SETA_EXTERNAL
|
||||
|
||||
config OR0_TRLX
|
||||
hex
|
||||
default 0x0 if OR0_TRLX_NORMAL
|
||||
default 0x4 if OR0_TRLX_RELAXED
|
||||
|
||||
config OR0_EHTR
|
||||
hex
|
||||
default 0x0 if OR0_EHTR_NORMAL
|
||||
default 0x2 if OR0_EHTR_1_CYCLE
|
||||
default 0x0 if OR0_EHTR_4_CYCLE
|
||||
default 0x2 if OR0_EHTR_8_CYCLE
|
||||
|
||||
config OR0_EAD
|
||||
hex
|
||||
default 0x0 if ARCH_MPC8308
|
||||
default 0x0 if OR0_EAD_NONE
|
||||
default 0x1 if OR0_EAD_EXTRA
|
||||
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
Normal file
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
Normal file
@ -0,0 +1,733 @@
|
||||
menuconfig ELBC_BR1_OR1
|
||||
bool "ELBC BR1/OR1"
|
||||
|
||||
if ELBC_BR1_OR1
|
||||
|
||||
config BR1_OR1_NAME
|
||||
string "Identifier"
|
||||
|
||||
config BR1_OR1_BASE
|
||||
hex "Port base"
|
||||
|
||||
choice
|
||||
prompt "Port size"
|
||||
|
||||
config BR1_PORTSIZE_8BIT
|
||||
bool "8-bit"
|
||||
|
||||
config BR1_PORTSIZE_16BIT
|
||||
depends on !BR1_MACHINE_FCM
|
||||
bool "16-bit"
|
||||
|
||||
|
||||
config BR1_PORTSIZE_32BIT
|
||||
depends on !BR1_MACHINE_FCM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
bool "32-bit"
|
||||
|
||||
endchoice
|
||||
|
||||
if BR1_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Data Error Checking"
|
||||
|
||||
config BR1_ERRORCHECKING_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BR1_ERRORCHECKING_ECC_CHECKING
|
||||
bool "ECC checking / No ECC generation"
|
||||
|
||||
config BR1_ERRORCHECKING_BOTH
|
||||
bool "ECC checking and generation"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config BR1_WRITE_PROTECT
|
||||
bool "Write-protect"
|
||||
|
||||
config BR1_MACHINE_UPM
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Machine select"
|
||||
|
||||
config BR1_MACHINE_GPCM
|
||||
bool "GPCM"
|
||||
|
||||
config BR1_MACHINE_FCM
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "FCM"
|
||||
|
||||
config BR1_MACHINE_SDRAM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360
|
||||
bool "SDRAM"
|
||||
|
||||
config BR1_MACHINE_UPMA
|
||||
select BR1_MACHINE_UPM
|
||||
bool "UPM (A)"
|
||||
|
||||
config BR1_MACHINE_UPMB
|
||||
select BR1_MACHINE_UPM
|
||||
bool "UPM (B)"
|
||||
|
||||
config BR1_MACHINE_UPMC
|
||||
select BR1_MACHINE_UPM
|
||||
bool "UPM (C)"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Atomic operations"
|
||||
|
||||
config BR1_ATOMIC_NONE
|
||||
bool "No atomic operations"
|
||||
|
||||
config BR1_ATOMIC_RAWA
|
||||
bool "Read-after-write-atomic"
|
||||
|
||||
config BR1_ATOMIC_WARA
|
||||
bool "Write-after-read-atomic"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Address mask"
|
||||
|
||||
config OR1_AM_32_KBYTES
|
||||
depends on !BR1_MACHINE_SDRAM
|
||||
bool "32 kb"
|
||||
|
||||
config OR1_AM_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config OR1_AM_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config OR1_AM_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config OR1_AM_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config OR1_AM_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config OR1_AM_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config OR1_AM_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config OR1_AM_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config OR1_AM_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config OR1_AM_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config OR1_AM_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
# XXX: Some boards define 128MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR1_AM_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
# XXX: Some boards define 256MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR1_AM_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config OR1_AM_512_MBYTES
|
||||
depends on BR1_MACHINE_FCM
|
||||
bool "512 mb"
|
||||
|
||||
# XXX: Some boards define 1GB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR1_AM_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config OR1_AM_2_GBYTES
|
||||
depends on BR1_MACHINE_FCM
|
||||
bool "2 gb"
|
||||
|
||||
config OR1_AM_4_GBYTES
|
||||
depends on BR1_MACHINE_FCM
|
||||
bool "4 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
config OR1_XAM_SET
|
||||
bool "Set unused bytes after address mask"
|
||||
choice
|
||||
prompt "Buffer control disable"
|
||||
|
||||
config OR1_BCTLD_ASSERTED
|
||||
bool "Asserted"
|
||||
|
||||
config OR1_BCTLD_NOT_ASSERTED
|
||||
bool "Not asserted"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Cycle length in bus clocks"
|
||||
|
||||
config OR1_SCY_0
|
||||
bool "No wait states"
|
||||
|
||||
config OR1_SCY_1
|
||||
bool "1 wait state"
|
||||
|
||||
config OR1_SCY_2
|
||||
bool "2 wait states"
|
||||
|
||||
config OR1_SCY_3
|
||||
bool "3 wait states"
|
||||
|
||||
config OR1_SCY_4
|
||||
bool "4 wait states"
|
||||
|
||||
config OR1_SCY_5
|
||||
bool "5 wait states"
|
||||
|
||||
config OR1_SCY_6
|
||||
bool "6 wait states"
|
||||
|
||||
config OR1_SCY_7
|
||||
bool "7 wait states"
|
||||
|
||||
config OR1_SCY_8
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "8 wait states"
|
||||
|
||||
config OR1_SCY_9
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "9 wait states"
|
||||
|
||||
config OR1_SCY_10
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "10 wait states"
|
||||
|
||||
config OR1_SCY_11
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "11 wait states"
|
||||
|
||||
config OR1_SCY_12
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "12 wait states"
|
||||
|
||||
config OR1_SCY_13
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "13 wait states"
|
||||
|
||||
config OR1_SCY_14
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "14 wait states"
|
||||
|
||||
config OR1_SCY_15
|
||||
depends on BR1_MACHINE_GPCM
|
||||
bool "15 wait states"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
|
||||
|
||||
if BR1_MACHINE_GPCM
|
||||
|
||||
choice
|
||||
prompt "Chip select negotiation time"
|
||||
|
||||
config OR1_CSNT_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR1_CSNT_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address to chip-select setup"
|
||||
|
||||
config OR1_ACS_SAME_TIME
|
||||
bool "At the same time"
|
||||
|
||||
config OR1_ACS_HALF_CYCLE_EARLIER
|
||||
bool "Half of a bus clock cycle earlier"
|
||||
|
||||
config OR1_ACS_QUARTER_CYCLE_EARLIER
|
||||
bool "Half/Quarter of a bus clock cycle earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extra address to check-select setup"
|
||||
|
||||
config OR1_XACS_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR1_XACS_EXTENDED
|
||||
bool "Extended"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "External address termination"
|
||||
|
||||
config OR1_SETA_INTERNAL
|
||||
bool "Access is terminated internally"
|
||||
|
||||
config OR1_SETA_EXTERNAL
|
||||
bool "Access is terminated externally"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR1_MACHINE_GPCM
|
||||
|
||||
if BR1_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "NAND Flash EEPROM page size"
|
||||
|
||||
config OR1_PGS_SMALL
|
||||
bool "Small page device"
|
||||
|
||||
config OR1_PGS_LARGE
|
||||
bool "Large page device"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Chip select to command time"
|
||||
|
||||
config OR1_CSCT_1_CYCLE
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "1 cycle"
|
||||
|
||||
config OR1_CSCT_2_CYCLE
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "2 cycles"
|
||||
|
||||
config OR1_CSCT_4_CYCLE
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "4 cycles"
|
||||
|
||||
config OR1_CSCT_8_CYCLE
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "8 cycles"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command setup time"
|
||||
|
||||
config OR1_CST_COINCIDENT
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "Coincident with any command"
|
||||
|
||||
config OR1_CST_QUARTER_CLOCK
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "0.25 clocks after"
|
||||
|
||||
config OR1_CST_HALF_CLOCK
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "0.5 clocks after"
|
||||
|
||||
config OR1_CST_ONE_CLOCK
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "1 clock after"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command hold time"
|
||||
|
||||
config OR1_CHT_HALF_CLOCK
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "0.5 clocks before"
|
||||
|
||||
config OR1_CHT_ONE_CLOCK
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "1 clock before"
|
||||
|
||||
config OR1_CHT_ONE_HALF_CLOCK
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "1.5 clocks before"
|
||||
|
||||
config OR1_CHT_TWO_CLOCK
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "2 clocks before"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Reset setup time"
|
||||
|
||||
config OR1_RST_THREE_QUARTER_CLOCK
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "0.75 clocks prior"
|
||||
|
||||
config OR1_RST_ONE_HALF_CLOCK
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "0.5 clocks prior"
|
||||
|
||||
config OR1_RST_ONE_CLOCK
|
||||
bool "1 clock prior"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR1_MACHINE_FCM
|
||||
|
||||
if BR1_MACHINE_UPM
|
||||
|
||||
choice
|
||||
prompt "Burst inhibit"
|
||||
|
||||
config OR1_BI_BURSTSUPPORT
|
||||
bool "Support burst access"
|
||||
|
||||
config OR1_BI_BURSTINHIBIT
|
||||
bool "Inhibit burst access"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR1_MACHINE_UPM
|
||||
|
||||
if BR1_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Number of column address lines"
|
||||
|
||||
config OR1_COLS_7
|
||||
bool "7"
|
||||
|
||||
config OR1_COLS_8
|
||||
bool "8"
|
||||
|
||||
config OR1_COLS_9
|
||||
bool "9"
|
||||
|
||||
config OR1_COLS_10
|
||||
bool "10"
|
||||
|
||||
config OR1_COLS_11
|
||||
bool "11"
|
||||
|
||||
config OR1_COLS_12
|
||||
bool "12"
|
||||
|
||||
config OR1_COLS_13
|
||||
bool "13"
|
||||
|
||||
config OR1_COLS_14
|
||||
bool "14"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Number of rows address lines"
|
||||
|
||||
config OR1_ROWS_9
|
||||
bool "9"
|
||||
|
||||
config OR1_ROWS_10
|
||||
bool "10"
|
||||
|
||||
config OR1_ROWS_11
|
||||
bool "11"
|
||||
|
||||
config OR1_ROWS_12
|
||||
bool "12"
|
||||
|
||||
config OR1_ROWS_13
|
||||
bool "13"
|
||||
|
||||
config OR1_ROWS_14
|
||||
bool "14"
|
||||
|
||||
config OR1_ROWS_15
|
||||
bool "15"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Page mode select"
|
||||
|
||||
config OR1_PMSEL_BTB
|
||||
bool "Back-to-back"
|
||||
|
||||
config OR1_PMSEL_KEPT_OPEN
|
||||
bool "Page kept open until page miss or refresh"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR1_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Relaxed timing"
|
||||
|
||||
config OR1_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR1_TRLX_RELAXED
|
||||
bool "Relaxed"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended hold time"
|
||||
|
||||
config OR1_EHTR_NORMAL
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR1_EHTR_1_CYCLE
|
||||
depends on OR1_TRLX_NORMAL
|
||||
bool "1 idle clock cycle inserted"
|
||||
|
||||
config OR1_EHTR_4_CYCLE
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "4 idle clock cycles inserted"
|
||||
|
||||
config OR1_EHTR_8_CYCLE
|
||||
depends on OR1_TRLX_RELAXED
|
||||
bool "8 idle clock cycles inserted"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address latch delay"
|
||||
|
||||
config OR1_EAD_NONE
|
||||
bool "None"
|
||||
|
||||
config OR1_EAD_EXTRA
|
||||
bool "Extra"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
endif # ELBC_BR1_OR1
|
||||
|
||||
config BR1_PORTSIZE
|
||||
hex
|
||||
default 0x800 if BR1_PORTSIZE_8BIT
|
||||
default 0x1000 if BR1_PORTSIZE_16BIT
|
||||
default 0x1800 if BR1_PORTSIZE_32BIT
|
||||
|
||||
config BR1_ERRORCHECKING
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if BR1_ERRORCHECKING_DISABLED
|
||||
default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
|
||||
default 0x400 if BR1_ERRORCHECKING_BOTH
|
||||
|
||||
config BR1_WRITE_PROTECT_BIT
|
||||
hex
|
||||
default 0x0 if !BR1_WRITE_PROTECT
|
||||
default 0x100 if BR1_WRITE_PROTECT
|
||||
|
||||
config BR1_MACHINE
|
||||
hex
|
||||
default 0x0 if BR1_MACHINE_GPCM
|
||||
default 0x20 if BR1_MACHINE_FCM
|
||||
default 0x60 if BR1_MACHINE_SDRAM
|
||||
default 0x80 if BR1_MACHINE_UPMA
|
||||
default 0xa0 if BR1_MACHINE_UPMB
|
||||
default 0xc0 if BR1_MACHINE_UPMC
|
||||
|
||||
config BR1_ATOMIC
|
||||
hex
|
||||
default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
|
||||
default 0x0 if BR1_ATOMIC_NONE
|
||||
default 0x4 if BR1_ATOMIC_RAWA
|
||||
default 0x8 if BR1_ATOMIC_WARA
|
||||
|
||||
config BR1_VALID_BIT
|
||||
hex
|
||||
default 0x0 if !ELBC_BR1_OR1
|
||||
default 0x1 if ELBC_BR1_OR1
|
||||
|
||||
config OR1_AM
|
||||
hex
|
||||
default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
|
||||
default 0xffff0000 if OR1_AM_64_KBYTES
|
||||
default 0xfffe0000 if OR1_AM_128_KBYTES
|
||||
default 0xfffc0000 if OR1_AM_256_KBYTES
|
||||
default 0xfff80000 if OR1_AM_512_KBYTES
|
||||
default 0xfff00000 if OR1_AM_1_MBYTES
|
||||
default 0xffe00000 if OR1_AM_2_MBYTES
|
||||
default 0xffc00000 if OR1_AM_4_MBYTES
|
||||
default 0xff800000 if OR1_AM_8_MBYTES
|
||||
default 0xff000000 if OR1_AM_16_MBYTES
|
||||
default 0xfe000000 if OR1_AM_32_MBYTES
|
||||
default 0xfc000000 if OR1_AM_64_MBYTES
|
||||
default 0xf8000000 if OR1_AM_128_MBYTES
|
||||
default 0xf0000000 if OR1_AM_256_MBYTES
|
||||
default 0xe0000000 if OR1_AM_512_MBYTES
|
||||
default 0xc0000000 if OR1_AM_1_GBYTES
|
||||
default 0x80000000 if OR1_AM_2_GBYTES
|
||||
default 0x00000000 if OR1_AM_4_GBYTES
|
||||
|
||||
config OR1_XAM
|
||||
hex
|
||||
default 0x0 if !OR1_XAM_SET
|
||||
default 0x6000 if OR1_XAM_SET
|
||||
|
||||
config OR1_BCTLD
|
||||
hex
|
||||
default 0x0 if OR1_BCTLD_ASSERTED
|
||||
default 0x1000 if OR1_BCTLD_NOT_ASSERTED
|
||||
|
||||
config OR1_BI
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_UPM
|
||||
default 0x0 if OR1_BI_BURSTSUPPORT
|
||||
default 0x100 if OR1_BI_BURSTINHIBIT
|
||||
|
||||
config OR1_COLS
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_SDRAM
|
||||
default 0x0 if OR1_COLS_7
|
||||
default 0x400 if OR1_COLS_8
|
||||
default 0x800 if OR1_COLS_9
|
||||
default 0xc00 if OR1_COLS_10
|
||||
default 0x1000 if OR1_COLS_11
|
||||
default 0x1400 if OR1_COLS_12
|
||||
default 0x1800 if OR1_COLS_13
|
||||
default 0x1c00 if OR1_COLS_14
|
||||
|
||||
config OR1_ROWS
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_SDRAM
|
||||
default 0x0 if OR1_ROWS_9
|
||||
default 0x40 if OR1_ROWS_10
|
||||
default 0x80 if OR1_ROWS_11
|
||||
default 0xc0 if OR1_ROWS_12
|
||||
default 0x100 if OR1_ROWS_13
|
||||
default 0x140 if OR1_ROWS_14
|
||||
default 0x180 if OR1_ROWS_15
|
||||
|
||||
config OR1_PMSEL
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_SDRAM
|
||||
default 0x0 if OR1_PMSEL_BTB
|
||||
default 0x20 if OR1_PMSEL_KEPT_OPEN
|
||||
|
||||
config OR1_SCY
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_SCY_0
|
||||
default 0x10 if OR1_SCY_1
|
||||
default 0x20 if OR1_SCY_2
|
||||
default 0x30 if OR1_SCY_3
|
||||
default 0x40 if OR1_SCY_4
|
||||
default 0x50 if OR1_SCY_5
|
||||
default 0x60 if OR1_SCY_6
|
||||
default 0x70 if OR1_SCY_7
|
||||
default 0x80 if OR1_SCY_8
|
||||
default 0x90 if OR1_SCY_9
|
||||
default 0xa0 if OR1_SCY_10
|
||||
default 0xb0 if OR1_SCY_11
|
||||
default 0xc0 if OR1_SCY_12
|
||||
default 0xd0 if OR1_SCY_13
|
||||
default 0xe0 if OR1_SCY_14
|
||||
default 0xf0 if OR1_SCY_15
|
||||
|
||||
config OR1_PGS
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_PGS_SMALL
|
||||
default 0x400 if OR1_PGS_LARGE
|
||||
|
||||
config OR1_CSCT
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_CSCT_1_CYCLE
|
||||
default 0x0 if OR1_CSCT_2_CYCLE
|
||||
default 0x200 if OR1_CSCT_4_CYCLE
|
||||
default 0x200 if OR1_CSCT_8_CYCLE
|
||||
|
||||
config OR1_CST
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_CST_COINCIDENT
|
||||
default 0x100 if OR1_CST_QUARTER_CLOCK
|
||||
default 0x0 if OR1_CST_HALF_CLOCK
|
||||
default 0x100 if OR1_CST_ONE_CLOCK
|
||||
|
||||
config OR1_CHT
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_CHT_HALF_CLOCK
|
||||
default 0x80 if OR1_CHT_ONE_CLOCK
|
||||
default 0x0 if OR1_CHT_ONE_HALF_CLOCK
|
||||
default 0x80 if OR1_CHT_TWO_CLOCK
|
||||
|
||||
config OR1_RST
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_FCM
|
||||
default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
|
||||
default 0x8 if OR1_RST_ONE_CLOCK
|
||||
default 0x0 if OR1_RST_ONE_HALF_CLOCK
|
||||
|
||||
config OR1_CSNT
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_GPCM
|
||||
default 0x0 if OR1_CSNT_NORMAL
|
||||
default 0x800 if OR1_CSNT_EARLIER
|
||||
|
||||
config OR1_ACS
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_GPCM
|
||||
default 0x0 if OR1_ACS_SAME_TIME
|
||||
default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
|
||||
default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
|
||||
|
||||
config OR1_XACS
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_GPCM
|
||||
default 0x0 if OR1_XACS_NORMAL
|
||||
default 0x100 if OR1_XACS_EXTENDED
|
||||
|
||||
config OR1_SETA
|
||||
hex
|
||||
default 0x0 if !BR1_MACHINE_GPCM
|
||||
default 0x0 if OR1_SETA_INTERNAL
|
||||
default 0x8 if OR1_SETA_EXTERNAL
|
||||
|
||||
config OR1_TRLX
|
||||
hex
|
||||
default 0x0 if OR1_TRLX_NORMAL
|
||||
default 0x4 if OR1_TRLX_RELAXED
|
||||
|
||||
config OR1_EHTR
|
||||
hex
|
||||
default 0x0 if OR1_EHTR_NORMAL
|
||||
default 0x2 if OR1_EHTR_1_CYCLE
|
||||
default 0x0 if OR1_EHTR_4_CYCLE
|
||||
default 0x2 if OR1_EHTR_8_CYCLE
|
||||
|
||||
config OR1_EAD
|
||||
hex
|
||||
default 0x0 if ARCH_MPC8308
|
||||
default 0x0 if OR1_EAD_NONE
|
||||
default 0x1 if OR1_EAD_EXTRA
|
||||
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
Normal file
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
Normal file
@ -0,0 +1,733 @@
|
||||
menuconfig ELBC_BR2_OR2
|
||||
bool "ELBC BR2/OR2"
|
||||
|
||||
if ELBC_BR2_OR2
|
||||
|
||||
config BR2_OR2_NAME
|
||||
string "Identifier"
|
||||
|
||||
config BR2_OR2_BASE
|
||||
hex "Port base"
|
||||
|
||||
choice
|
||||
prompt "Port size"
|
||||
|
||||
config BR2_PORTSIZE_8BIT
|
||||
bool "8-bit"
|
||||
|
||||
config BR2_PORTSIZE_16BIT
|
||||
depends on !BR2_MACHINE_FCM
|
||||
bool "16-bit"
|
||||
|
||||
|
||||
config BR2_PORTSIZE_32BIT
|
||||
depends on !BR2_MACHINE_FCM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
bool "32-bit"
|
||||
|
||||
endchoice
|
||||
|
||||
if BR2_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Data Error Checking"
|
||||
|
||||
config BR2_ERRORCHECKING_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BR2_ERRORCHECKING_ECC_CHECKING
|
||||
bool "ECC checking / No ECC generation"
|
||||
|
||||
config BR2_ERRORCHECKING_BOTH
|
||||
bool "ECC checking and generation"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config BR2_WRITE_PROTECT
|
||||
bool "Write-protect"
|
||||
|
||||
config BR2_MACHINE_UPM
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Machine select"
|
||||
|
||||
config BR2_MACHINE_GPCM
|
||||
bool "GPCM"
|
||||
|
||||
config BR2_MACHINE_FCM
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "FCM"
|
||||
|
||||
config BR2_MACHINE_SDRAM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360
|
||||
bool "SDRAM"
|
||||
|
||||
config BR2_MACHINE_UPMA
|
||||
select BR2_MACHINE_UPM
|
||||
bool "UPM (A)"
|
||||
|
||||
config BR2_MACHINE_UPMB
|
||||
select BR2_MACHINE_UPM
|
||||
bool "UPM (B)"
|
||||
|
||||
config BR2_MACHINE_UPMC
|
||||
select BR2_MACHINE_UPM
|
||||
bool "UPM (C)"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Atomic operations"
|
||||
|
||||
config BR2_ATOMIC_NONE
|
||||
bool "No atomic operations"
|
||||
|
||||
config BR2_ATOMIC_RAWA
|
||||
bool "Read-after-write-atomic"
|
||||
|
||||
config BR2_ATOMIC_WARA
|
||||
bool "Write-after-read-atomic"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Address mask"
|
||||
|
||||
config OR2_AM_32_KBYTES
|
||||
depends on !BR2_MACHINE_SDRAM
|
||||
bool "32 kb"
|
||||
|
||||
config OR2_AM_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config OR2_AM_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config OR2_AM_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config OR2_AM_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config OR2_AM_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config OR2_AM_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config OR2_AM_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config OR2_AM_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config OR2_AM_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config OR2_AM_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config OR2_AM_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
# XXX: Some boards define 128MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR2_AM_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
# XXX: Some boards define 256MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR2_AM_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config OR2_AM_512_MBYTES
|
||||
depends on BR2_MACHINE_FCM
|
||||
bool "512 mb"
|
||||
|
||||
# XXX: Some boards define 1GB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR2_AM_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config OR2_AM_2_GBYTES
|
||||
depends on BR2_MACHINE_FCM
|
||||
bool "2 gb"
|
||||
|
||||
config OR2_AM_4_GBYTES
|
||||
depends on BR2_MACHINE_FCM
|
||||
bool "4 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
config OR2_XAM_SET
|
||||
bool "Set unused bytes after address mask"
|
||||
choice
|
||||
prompt "Buffer control disable"
|
||||
|
||||
config OR2_BCTLD_ASSERTED
|
||||
bool "Asserted"
|
||||
|
||||
config OR2_BCTLD_NOT_ASSERTED
|
||||
bool "Not asserted"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Cycle length in bus clocks"
|
||||
|
||||
config OR2_SCY_0
|
||||
bool "No wait states"
|
||||
|
||||
config OR2_SCY_1
|
||||
bool "1 wait state"
|
||||
|
||||
config OR2_SCY_2
|
||||
bool "2 wait states"
|
||||
|
||||
config OR2_SCY_3
|
||||
bool "3 wait states"
|
||||
|
||||
config OR2_SCY_4
|
||||
bool "4 wait states"
|
||||
|
||||
config OR2_SCY_5
|
||||
bool "5 wait states"
|
||||
|
||||
config OR2_SCY_6
|
||||
bool "6 wait states"
|
||||
|
||||
config OR2_SCY_7
|
||||
bool "7 wait states"
|
||||
|
||||
config OR2_SCY_8
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "8 wait states"
|
||||
|
||||
config OR2_SCY_9
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "9 wait states"
|
||||
|
||||
config OR2_SCY_10
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "10 wait states"
|
||||
|
||||
config OR2_SCY_11
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "11 wait states"
|
||||
|
||||
config OR2_SCY_12
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "12 wait states"
|
||||
|
||||
config OR2_SCY_13
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "13 wait states"
|
||||
|
||||
config OR2_SCY_14
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "14 wait states"
|
||||
|
||||
config OR2_SCY_15
|
||||
depends on BR2_MACHINE_GPCM
|
||||
bool "15 wait states"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
|
||||
|
||||
if BR2_MACHINE_GPCM
|
||||
|
||||
choice
|
||||
prompt "Chip select negotiation time"
|
||||
|
||||
config OR2_CSNT_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR2_CSNT_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address to chip-select setup"
|
||||
|
||||
config OR2_ACS_SAME_TIME
|
||||
bool "At the same time"
|
||||
|
||||
config OR2_ACS_HALF_CYCLE_EARLIER
|
||||
bool "Half of a bus clock cycle earlier"
|
||||
|
||||
config OR2_ACS_QUARTER_CYCLE_EARLIER
|
||||
bool "Half/Quarter of a bus clock cycle earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extra address to check-select setup"
|
||||
|
||||
config OR2_XACS_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR2_XACS_EXTENDED
|
||||
bool "Extended"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "External address termination"
|
||||
|
||||
config OR2_SETA_INTERNAL
|
||||
bool "Access is terminated internally"
|
||||
|
||||
config OR2_SETA_EXTERNAL
|
||||
bool "Access is terminated externally"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR2_MACHINE_GPCM
|
||||
|
||||
if BR2_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "NAND Flash EEPROM page size"
|
||||
|
||||
config OR2_PGS_SMALL
|
||||
bool "Small page device"
|
||||
|
||||
config OR2_PGS_LARGE
|
||||
bool "Large page device"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Chip select to command time"
|
||||
|
||||
config OR2_CSCT_1_CYCLE
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "1 cycle"
|
||||
|
||||
config OR2_CSCT_2_CYCLE
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "2 cycles"
|
||||
|
||||
config OR2_CSCT_4_CYCLE
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "4 cycles"
|
||||
|
||||
config OR2_CSCT_8_CYCLE
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "8 cycles"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command setup time"
|
||||
|
||||
config OR2_CST_COINCIDENT
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "Coincident with any command"
|
||||
|
||||
config OR2_CST_QUARTER_CLOCK
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "0.25 clocks after"
|
||||
|
||||
config OR2_CST_HALF_CLOCK
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "0.5 clocks after"
|
||||
|
||||
config OR2_CST_ONE_CLOCK
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "1 clock after"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command hold time"
|
||||
|
||||
config OR2_CHT_HALF_CLOCK
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "0.5 clocks before"
|
||||
|
||||
config OR2_CHT_ONE_CLOCK
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "1 clock before"
|
||||
|
||||
config OR2_CHT_ONE_HALF_CLOCK
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "1.5 clocks before"
|
||||
|
||||
config OR2_CHT_TWO_CLOCK
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "2 clocks before"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Reset setup time"
|
||||
|
||||
config OR2_RST_THREE_QUARTER_CLOCK
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "0.75 clocks prior"
|
||||
|
||||
config OR2_RST_ONE_HALF_CLOCK
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "0.5 clocks prior"
|
||||
|
||||
config OR2_RST_ONE_CLOCK
|
||||
bool "1 clock prior"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR2_MACHINE_FCM
|
||||
|
||||
if BR2_MACHINE_UPM
|
||||
|
||||
choice
|
||||
prompt "Burst inhibit"
|
||||
|
||||
config OR2_BI_BURSTSUPPORT
|
||||
bool "Support burst access"
|
||||
|
||||
config OR2_BI_BURSTINHIBIT
|
||||
bool "Inhibit burst access"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR2_MACHINE_UPM
|
||||
|
||||
if BR2_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Number of column address lines"
|
||||
|
||||
config OR2_COLS_7
|
||||
bool "7"
|
||||
|
||||
config OR2_COLS_8
|
||||
bool "8"
|
||||
|
||||
config OR2_COLS_9
|
||||
bool "9"
|
||||
|
||||
config OR2_COLS_10
|
||||
bool "10"
|
||||
|
||||
config OR2_COLS_11
|
||||
bool "11"
|
||||
|
||||
config OR2_COLS_12
|
||||
bool "12"
|
||||
|
||||
config OR2_COLS_13
|
||||
bool "13"
|
||||
|
||||
config OR2_COLS_14
|
||||
bool "14"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Number of rows address lines"
|
||||
|
||||
config OR2_ROWS_9
|
||||
bool "9"
|
||||
|
||||
config OR2_ROWS_10
|
||||
bool "10"
|
||||
|
||||
config OR2_ROWS_11
|
||||
bool "11"
|
||||
|
||||
config OR2_ROWS_12
|
||||
bool "12"
|
||||
|
||||
config OR2_ROWS_13
|
||||
bool "13"
|
||||
|
||||
config OR2_ROWS_14
|
||||
bool "14"
|
||||
|
||||
config OR2_ROWS_15
|
||||
bool "15"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Page mode select"
|
||||
|
||||
config OR2_PMSEL_BTB
|
||||
bool "Back-to-back"
|
||||
|
||||
config OR2_PMSEL_KEPT_OPEN
|
||||
bool "Page kept open until page miss or refresh"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR2_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Relaxed timing"
|
||||
|
||||
config OR2_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR2_TRLX_RELAXED
|
||||
bool "Relaxed"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended hold time"
|
||||
|
||||
config OR2_EHTR_NORMAL
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR2_EHTR_1_CYCLE
|
||||
depends on OR2_TRLX_NORMAL
|
||||
bool "1 idle clock cycle inserted"
|
||||
|
||||
config OR2_EHTR_4_CYCLE
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "4 idle clock cycles inserted"
|
||||
|
||||
config OR2_EHTR_8_CYCLE
|
||||
depends on OR2_TRLX_RELAXED
|
||||
bool "8 idle clock cycles inserted"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address latch delay"
|
||||
|
||||
config OR2_EAD_NONE
|
||||
bool "None"
|
||||
|
||||
config OR2_EAD_EXTRA
|
||||
bool "Extra"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
endif # ELBC_BR2_OR2
|
||||
|
||||
config BR2_PORTSIZE
|
||||
hex
|
||||
default 0x800 if BR2_PORTSIZE_8BIT
|
||||
default 0x1000 if BR2_PORTSIZE_16BIT
|
||||
default 0x1800 if BR2_PORTSIZE_32BIT
|
||||
|
||||
config BR2_ERRORCHECKING
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if BR2_ERRORCHECKING_DISABLED
|
||||
default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
|
||||
default 0x400 if BR2_ERRORCHECKING_BOTH
|
||||
|
||||
config BR2_WRITE_PROTECT_BIT
|
||||
hex
|
||||
default 0x0 if !BR2_WRITE_PROTECT
|
||||
default 0x100 if BR2_WRITE_PROTECT
|
||||
|
||||
config BR2_MACHINE
|
||||
hex
|
||||
default 0x0 if BR2_MACHINE_GPCM
|
||||
default 0x20 if BR2_MACHINE_FCM
|
||||
default 0x60 if BR2_MACHINE_SDRAM
|
||||
default 0x80 if BR2_MACHINE_UPMA
|
||||
default 0xa0 if BR2_MACHINE_UPMB
|
||||
default 0xc0 if BR2_MACHINE_UPMC
|
||||
|
||||
config BR2_ATOMIC
|
||||
hex
|
||||
default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
|
||||
default 0x0 if BR2_ATOMIC_NONE
|
||||
default 0x4 if BR2_ATOMIC_RAWA
|
||||
default 0x8 if BR2_ATOMIC_WARA
|
||||
|
||||
config BR2_VALID_BIT
|
||||
hex
|
||||
default 0x0 if !ELBC_BR2_OR2
|
||||
default 0x1 if ELBC_BR2_OR2
|
||||
|
||||
config OR2_AM
|
||||
hex
|
||||
default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
|
||||
default 0xffff0000 if OR2_AM_64_KBYTES
|
||||
default 0xfffe0000 if OR2_AM_128_KBYTES
|
||||
default 0xfffc0000 if OR2_AM_256_KBYTES
|
||||
default 0xfff80000 if OR2_AM_512_KBYTES
|
||||
default 0xfff00000 if OR2_AM_1_MBYTES
|
||||
default 0xffe00000 if OR2_AM_2_MBYTES
|
||||
default 0xffc00000 if OR2_AM_4_MBYTES
|
||||
default 0xff800000 if OR2_AM_8_MBYTES
|
||||
default 0xff000000 if OR2_AM_16_MBYTES
|
||||
default 0xfe000000 if OR2_AM_32_MBYTES
|
||||
default 0xfc000000 if OR2_AM_64_MBYTES
|
||||
default 0xf8000000 if OR2_AM_128_MBYTES
|
||||
default 0xf0000000 if OR2_AM_256_MBYTES
|
||||
default 0xe0000000 if OR2_AM_512_MBYTES
|
||||
default 0xc0000000 if OR2_AM_1_GBYTES
|
||||
default 0x80000000 if OR2_AM_2_GBYTES
|
||||
default 0x00000000 if OR2_AM_4_GBYTES
|
||||
|
||||
config OR2_XAM
|
||||
hex
|
||||
default 0x0 if !OR2_XAM_SET
|
||||
default 0x6000 if OR2_XAM_SET
|
||||
|
||||
config OR2_BCTLD
|
||||
hex
|
||||
default 0x0 if OR2_BCTLD_ASSERTED
|
||||
default 0x1000 if OR2_BCTLD_NOT_ASSERTED
|
||||
|
||||
config OR2_BI
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_UPM
|
||||
default 0x0 if OR2_BI_BURSTSUPPORT
|
||||
default 0x100 if OR2_BI_BURSTINHIBIT
|
||||
|
||||
config OR2_COLS
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_SDRAM
|
||||
default 0x0 if OR2_COLS_7
|
||||
default 0x400 if OR2_COLS_8
|
||||
default 0x800 if OR2_COLS_9
|
||||
default 0xc00 if OR2_COLS_10
|
||||
default 0x1000 if OR2_COLS_11
|
||||
default 0x1400 if OR2_COLS_12
|
||||
default 0x1800 if OR2_COLS_13
|
||||
default 0x1c00 if OR2_COLS_14
|
||||
|
||||
config OR2_ROWS
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_SDRAM
|
||||
default 0x0 if OR2_ROWS_9
|
||||
default 0x40 if OR2_ROWS_10
|
||||
default 0x80 if OR2_ROWS_11
|
||||
default 0xc0 if OR2_ROWS_12
|
||||
default 0x100 if OR2_ROWS_13
|
||||
default 0x140 if OR2_ROWS_14
|
||||
default 0x180 if OR2_ROWS_15
|
||||
|
||||
config OR2_PMSEL
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_SDRAM
|
||||
default 0x0 if OR2_PMSEL_BTB
|
||||
default 0x20 if OR2_PMSEL_KEPT_OPEN
|
||||
|
||||
config OR2_SCY
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_SCY_0
|
||||
default 0x10 if OR2_SCY_1
|
||||
default 0x20 if OR2_SCY_2
|
||||
default 0x30 if OR2_SCY_3
|
||||
default 0x40 if OR2_SCY_4
|
||||
default 0x50 if OR2_SCY_5
|
||||
default 0x60 if OR2_SCY_6
|
||||
default 0x70 if OR2_SCY_7
|
||||
default 0x80 if OR2_SCY_8
|
||||
default 0x90 if OR2_SCY_9
|
||||
default 0xa0 if OR2_SCY_10
|
||||
default 0xb0 if OR2_SCY_11
|
||||
default 0xc0 if OR2_SCY_12
|
||||
default 0xd0 if OR2_SCY_13
|
||||
default 0xe0 if OR2_SCY_14
|
||||
default 0xf0 if OR2_SCY_15
|
||||
|
||||
config OR2_PGS
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_PGS_SMALL
|
||||
default 0x400 if OR2_PGS_LARGE
|
||||
|
||||
config OR2_CSCT
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_CSCT_1_CYCLE
|
||||
default 0x0 if OR2_CSCT_2_CYCLE
|
||||
default 0x200 if OR2_CSCT_4_CYCLE
|
||||
default 0x200 if OR2_CSCT_8_CYCLE
|
||||
|
||||
config OR2_CST
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_CST_COINCIDENT
|
||||
default 0x100 if OR2_CST_QUARTER_CLOCK
|
||||
default 0x0 if OR2_CST_HALF_CLOCK
|
||||
default 0x100 if OR2_CST_ONE_CLOCK
|
||||
|
||||
config OR2_CHT
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_CHT_HALF_CLOCK
|
||||
default 0x80 if OR2_CHT_ONE_CLOCK
|
||||
default 0x0 if OR2_CHT_ONE_HALF_CLOCK
|
||||
default 0x80 if OR2_CHT_TWO_CLOCK
|
||||
|
||||
config OR2_RST
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_FCM
|
||||
default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
|
||||
default 0x8 if OR2_RST_ONE_CLOCK
|
||||
default 0x0 if OR2_RST_ONE_HALF_CLOCK
|
||||
|
||||
config OR2_CSNT
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_GPCM
|
||||
default 0x0 if OR2_CSNT_NORMAL
|
||||
default 0x800 if OR2_CSNT_EARLIER
|
||||
|
||||
config OR2_ACS
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_GPCM
|
||||
default 0x0 if OR2_ACS_SAME_TIME
|
||||
default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
|
||||
default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
|
||||
|
||||
config OR2_XACS
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_GPCM
|
||||
default 0x0 if OR2_XACS_NORMAL
|
||||
default 0x100 if OR2_XACS_EXTENDED
|
||||
|
||||
config OR2_SETA
|
||||
hex
|
||||
default 0x0 if !BR2_MACHINE_GPCM
|
||||
default 0x0 if OR2_SETA_INTERNAL
|
||||
default 0x8 if OR2_SETA_EXTERNAL
|
||||
|
||||
config OR2_TRLX
|
||||
hex
|
||||
default 0x0 if OR2_TRLX_NORMAL
|
||||
default 0x4 if OR2_TRLX_RELAXED
|
||||
|
||||
config OR2_EHTR
|
||||
hex
|
||||
default 0x0 if OR2_EHTR_NORMAL
|
||||
default 0x2 if OR2_EHTR_1_CYCLE
|
||||
default 0x0 if OR2_EHTR_4_CYCLE
|
||||
default 0x2 if OR2_EHTR_8_CYCLE
|
||||
|
||||
config OR2_EAD
|
||||
hex
|
||||
default 0x0 if ARCH_MPC8308
|
||||
default 0x0 if OR2_EAD_NONE
|
||||
default 0x1 if OR2_EAD_EXTRA
|
||||
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
Normal file
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
Normal file
@ -0,0 +1,733 @@
|
||||
menuconfig ELBC_BR3_OR3
|
||||
bool "ELBC BR3/OR3"
|
||||
|
||||
if ELBC_BR3_OR3
|
||||
|
||||
config BR3_OR3_NAME
|
||||
string "Identifier"
|
||||
|
||||
config BR3_OR3_BASE
|
||||
hex "Port base"
|
||||
|
||||
choice
|
||||
prompt "Port size"
|
||||
|
||||
config BR3_PORTSIZE_8BIT
|
||||
bool "8-bit"
|
||||
|
||||
config BR3_PORTSIZE_16BIT
|
||||
depends on !BR3_MACHINE_FCM
|
||||
bool "16-bit"
|
||||
|
||||
|
||||
config BR3_PORTSIZE_32BIT
|
||||
depends on !BR3_MACHINE_FCM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
bool "32-bit"
|
||||
|
||||
endchoice
|
||||
|
||||
if BR3_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Data Error Checking"
|
||||
|
||||
config BR3_ERRORCHECKING_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BR3_ERRORCHECKING_ECC_CHECKING
|
||||
bool "ECC checking / No ECC generation"
|
||||
|
||||
config BR3_ERRORCHECKING_BOTH
|
||||
bool "ECC checking and generation"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config BR3_WRITE_PROTECT
|
||||
bool "Write-protect"
|
||||
|
||||
config BR3_MACHINE_UPM
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Machine select"
|
||||
|
||||
config BR3_MACHINE_GPCM
|
||||
bool "GPCM"
|
||||
|
||||
config BR3_MACHINE_FCM
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "FCM"
|
||||
|
||||
config BR3_MACHINE_SDRAM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360
|
||||
bool "SDRAM"
|
||||
|
||||
config BR3_MACHINE_UPMA
|
||||
select BR3_MACHINE_UPM
|
||||
bool "UPM (A)"
|
||||
|
||||
config BR3_MACHINE_UPMB
|
||||
select BR3_MACHINE_UPM
|
||||
bool "UPM (B)"
|
||||
|
||||
config BR3_MACHINE_UPMC
|
||||
select BR3_MACHINE_UPM
|
||||
bool "UPM (C)"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Atomic operations"
|
||||
|
||||
config BR3_ATOMIC_NONE
|
||||
bool "No atomic operations"
|
||||
|
||||
config BR3_ATOMIC_RAWA
|
||||
bool "Read-after-write-atomic"
|
||||
|
||||
config BR3_ATOMIC_WARA
|
||||
bool "Write-after-read-atomic"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Address mask"
|
||||
|
||||
config OR3_AM_32_KBYTES
|
||||
depends on !BR3_MACHINE_SDRAM
|
||||
bool "32 kb"
|
||||
|
||||
config OR3_AM_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config OR3_AM_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config OR3_AM_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config OR3_AM_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config OR3_AM_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config OR3_AM_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config OR3_AM_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config OR3_AM_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config OR3_AM_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config OR3_AM_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config OR3_AM_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
# XXX: Some boards define 128MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR3_AM_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
# XXX: Some boards define 256MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR3_AM_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config OR3_AM_512_MBYTES
|
||||
depends on BR3_MACHINE_FCM
|
||||
bool "512 mb"
|
||||
|
||||
# XXX: Some boards define 1GB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR3_AM_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config OR3_AM_2_GBYTES
|
||||
depends on BR3_MACHINE_FCM
|
||||
bool "2 gb"
|
||||
|
||||
config OR3_AM_4_GBYTES
|
||||
depends on BR3_MACHINE_FCM
|
||||
bool "4 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
config OR3_XAM_SET
|
||||
bool "Set unused bytes after address mask"
|
||||
choice
|
||||
prompt "Buffer control disable"
|
||||
|
||||
config OR3_BCTLD_ASSERTED
|
||||
bool "Asserted"
|
||||
|
||||
config OR3_BCTLD_NOT_ASSERTED
|
||||
bool "Not asserted"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Cycle length in bus clocks"
|
||||
|
||||
config OR3_SCY_0
|
||||
bool "No wait states"
|
||||
|
||||
config OR3_SCY_1
|
||||
bool "1 wait state"
|
||||
|
||||
config OR3_SCY_2
|
||||
bool "2 wait states"
|
||||
|
||||
config OR3_SCY_3
|
||||
bool "3 wait states"
|
||||
|
||||
config OR3_SCY_4
|
||||
bool "4 wait states"
|
||||
|
||||
config OR3_SCY_5
|
||||
bool "5 wait states"
|
||||
|
||||
config OR3_SCY_6
|
||||
bool "6 wait states"
|
||||
|
||||
config OR3_SCY_7
|
||||
bool "7 wait states"
|
||||
|
||||
config OR3_SCY_8
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "8 wait states"
|
||||
|
||||
config OR3_SCY_9
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "9 wait states"
|
||||
|
||||
config OR3_SCY_10
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "10 wait states"
|
||||
|
||||
config OR3_SCY_11
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "11 wait states"
|
||||
|
||||
config OR3_SCY_12
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "12 wait states"
|
||||
|
||||
config OR3_SCY_13
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "13 wait states"
|
||||
|
||||
config OR3_SCY_14
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "14 wait states"
|
||||
|
||||
config OR3_SCY_15
|
||||
depends on BR3_MACHINE_GPCM
|
||||
bool "15 wait states"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
|
||||
|
||||
if BR3_MACHINE_GPCM
|
||||
|
||||
choice
|
||||
prompt "Chip select negotiation time"
|
||||
|
||||
config OR3_CSNT_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR3_CSNT_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address to chip-select setup"
|
||||
|
||||
config OR3_ACS_SAME_TIME
|
||||
bool "At the same time"
|
||||
|
||||
config OR3_ACS_HALF_CYCLE_EARLIER
|
||||
bool "Half of a bus clock cycle earlier"
|
||||
|
||||
config OR3_ACS_QUARTER_CYCLE_EARLIER
|
||||
bool "Half/Quarter of a bus clock cycle earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extra address to check-select setup"
|
||||
|
||||
config OR3_XACS_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR3_XACS_EXTENDED
|
||||
bool "Extended"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "External address termination"
|
||||
|
||||
config OR3_SETA_INTERNAL
|
||||
bool "Access is terminated internally"
|
||||
|
||||
config OR3_SETA_EXTERNAL
|
||||
bool "Access is terminated externally"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR3_MACHINE_GPCM
|
||||
|
||||
if BR3_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "NAND Flash EEPROM page size"
|
||||
|
||||
config OR3_PGS_SMALL
|
||||
bool "Small page device"
|
||||
|
||||
config OR3_PGS_LARGE
|
||||
bool "Large page device"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Chip select to command time"
|
||||
|
||||
config OR3_CSCT_1_CYCLE
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "1 cycle"
|
||||
|
||||
config OR3_CSCT_2_CYCLE
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "2 cycles"
|
||||
|
||||
config OR3_CSCT_4_CYCLE
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "4 cycles"
|
||||
|
||||
config OR3_CSCT_8_CYCLE
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "8 cycles"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command setup time"
|
||||
|
||||
config OR3_CST_COINCIDENT
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "Coincident with any command"
|
||||
|
||||
config OR3_CST_QUARTER_CLOCK
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "0.25 clocks after"
|
||||
|
||||
config OR3_CST_HALF_CLOCK
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "0.5 clocks after"
|
||||
|
||||
config OR3_CST_ONE_CLOCK
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "1 clock after"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command hold time"
|
||||
|
||||
config OR3_CHT_HALF_CLOCK
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "0.5 clocks before"
|
||||
|
||||
config OR3_CHT_ONE_CLOCK
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "1 clock before"
|
||||
|
||||
config OR3_CHT_ONE_HALF_CLOCK
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "1.5 clocks before"
|
||||
|
||||
config OR3_CHT_TWO_CLOCK
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "2 clocks before"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Reset setup time"
|
||||
|
||||
config OR3_RST_THREE_QUARTER_CLOCK
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "0.75 clocks prior"
|
||||
|
||||
config OR3_RST_ONE_HALF_CLOCK
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "0.5 clocks prior"
|
||||
|
||||
config OR3_RST_ONE_CLOCK
|
||||
bool "1 clock prior"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR3_MACHINE_FCM
|
||||
|
||||
if BR3_MACHINE_UPM
|
||||
|
||||
choice
|
||||
prompt "Burst inhibit"
|
||||
|
||||
config OR3_BI_BURSTSUPPORT
|
||||
bool "Support burst access"
|
||||
|
||||
config OR3_BI_BURSTINHIBIT
|
||||
bool "Inhibit burst access"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR3_MACHINE_UPM
|
||||
|
||||
if BR3_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Number of column address lines"
|
||||
|
||||
config OR3_COLS_7
|
||||
bool "7"
|
||||
|
||||
config OR3_COLS_8
|
||||
bool "8"
|
||||
|
||||
config OR3_COLS_9
|
||||
bool "9"
|
||||
|
||||
config OR3_COLS_10
|
||||
bool "10"
|
||||
|
||||
config OR3_COLS_11
|
||||
bool "11"
|
||||
|
||||
config OR3_COLS_12
|
||||
bool "12"
|
||||
|
||||
config OR3_COLS_13
|
||||
bool "13"
|
||||
|
||||
config OR3_COLS_14
|
||||
bool "14"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Number of rows address lines"
|
||||
|
||||
config OR3_ROWS_9
|
||||
bool "9"
|
||||
|
||||
config OR3_ROWS_10
|
||||
bool "10"
|
||||
|
||||
config OR3_ROWS_11
|
||||
bool "11"
|
||||
|
||||
config OR3_ROWS_12
|
||||
bool "12"
|
||||
|
||||
config OR3_ROWS_13
|
||||
bool "13"
|
||||
|
||||
config OR3_ROWS_14
|
||||
bool "14"
|
||||
|
||||
config OR3_ROWS_15
|
||||
bool "15"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Page mode select"
|
||||
|
||||
config OR3_PMSEL_BTB
|
||||
bool "Back-to-back"
|
||||
|
||||
config OR3_PMSEL_KEPT_OPEN
|
||||
bool "Page kept open until page miss or refresh"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR3_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Relaxed timing"
|
||||
|
||||
config OR3_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR3_TRLX_RELAXED
|
||||
bool "Relaxed"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended hold time"
|
||||
|
||||
config OR3_EHTR_NORMAL
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR3_EHTR_1_CYCLE
|
||||
depends on OR3_TRLX_NORMAL
|
||||
bool "1 idle clock cycle inserted"
|
||||
|
||||
config OR3_EHTR_4_CYCLE
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "4 idle clock cycles inserted"
|
||||
|
||||
config OR3_EHTR_8_CYCLE
|
||||
depends on OR3_TRLX_RELAXED
|
||||
bool "8 idle clock cycles inserted"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address latch delay"
|
||||
|
||||
config OR3_EAD_NONE
|
||||
bool "None"
|
||||
|
||||
config OR3_EAD_EXTRA
|
||||
bool "Extra"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
endif # ELBC_BR3_OR3
|
||||
|
||||
config BR3_PORTSIZE
|
||||
hex
|
||||
default 0x800 if BR3_PORTSIZE_8BIT
|
||||
default 0x1000 if BR3_PORTSIZE_16BIT
|
||||
default 0x1800 if BR3_PORTSIZE_32BIT
|
||||
|
||||
config BR3_ERRORCHECKING
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if BR3_ERRORCHECKING_DISABLED
|
||||
default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
|
||||
default 0x400 if BR3_ERRORCHECKING_BOTH
|
||||
|
||||
config BR3_WRITE_PROTECT_BIT
|
||||
hex
|
||||
default 0x0 if !BR3_WRITE_PROTECT
|
||||
default 0x100 if BR3_WRITE_PROTECT
|
||||
|
||||
config BR3_MACHINE
|
||||
hex
|
||||
default 0x0 if BR3_MACHINE_GPCM
|
||||
default 0x20 if BR3_MACHINE_FCM
|
||||
default 0x60 if BR3_MACHINE_SDRAM
|
||||
default 0x80 if BR3_MACHINE_UPMA
|
||||
default 0xa0 if BR3_MACHINE_UPMB
|
||||
default 0xc0 if BR3_MACHINE_UPMC
|
||||
|
||||
config BR3_ATOMIC
|
||||
hex
|
||||
default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
|
||||
default 0x0 if BR3_ATOMIC_NONE
|
||||
default 0x4 if BR3_ATOMIC_RAWA
|
||||
default 0x8 if BR3_ATOMIC_WARA
|
||||
|
||||
config BR3_VALID_BIT
|
||||
hex
|
||||
default 0x0 if !ELBC_BR3_OR3
|
||||
default 0x1 if ELBC_BR3_OR3
|
||||
|
||||
config OR3_AM
|
||||
hex
|
||||
default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
|
||||
default 0xffff0000 if OR3_AM_64_KBYTES
|
||||
default 0xfffe0000 if OR3_AM_128_KBYTES
|
||||
default 0xfffc0000 if OR3_AM_256_KBYTES
|
||||
default 0xfff80000 if OR3_AM_512_KBYTES
|
||||
default 0xfff00000 if OR3_AM_1_MBYTES
|
||||
default 0xffe00000 if OR3_AM_2_MBYTES
|
||||
default 0xffc00000 if OR3_AM_4_MBYTES
|
||||
default 0xff800000 if OR3_AM_8_MBYTES
|
||||
default 0xff000000 if OR3_AM_16_MBYTES
|
||||
default 0xfe000000 if OR3_AM_32_MBYTES
|
||||
default 0xfc000000 if OR3_AM_64_MBYTES
|
||||
default 0xf8000000 if OR3_AM_128_MBYTES
|
||||
default 0xf0000000 if OR3_AM_256_MBYTES
|
||||
default 0xe0000000 if OR3_AM_512_MBYTES
|
||||
default 0xc0000000 if OR3_AM_1_GBYTES
|
||||
default 0x80000000 if OR3_AM_2_GBYTES
|
||||
default 0x00000000 if OR3_AM_4_GBYTES
|
||||
|
||||
config OR3_XAM
|
||||
hex
|
||||
default 0x0 if !OR3_XAM_SET
|
||||
default 0x6000 if OR3_XAM_SET
|
||||
|
||||
config OR3_BCTLD
|
||||
hex
|
||||
default 0x0 if OR3_BCTLD_ASSERTED
|
||||
default 0x1000 if OR3_BCTLD_NOT_ASSERTED
|
||||
|
||||
config OR3_BI
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_UPM
|
||||
default 0x0 if OR3_BI_BURSTSUPPORT
|
||||
default 0x100 if OR3_BI_BURSTINHIBIT
|
||||
|
||||
config OR3_COLS
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_SDRAM
|
||||
default 0x0 if OR3_COLS_7
|
||||
default 0x400 if OR3_COLS_8
|
||||
default 0x800 if OR3_COLS_9
|
||||
default 0xc00 if OR3_COLS_10
|
||||
default 0x1000 if OR3_COLS_11
|
||||
default 0x1400 if OR3_COLS_12
|
||||
default 0x1800 if OR3_COLS_13
|
||||
default 0x1c00 if OR3_COLS_14
|
||||
|
||||
config OR3_ROWS
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_SDRAM
|
||||
default 0x0 if OR3_ROWS_9
|
||||
default 0x40 if OR3_ROWS_10
|
||||
default 0x80 if OR3_ROWS_11
|
||||
default 0xc0 if OR3_ROWS_12
|
||||
default 0x100 if OR3_ROWS_13
|
||||
default 0x140 if OR3_ROWS_14
|
||||
default 0x180 if OR3_ROWS_15
|
||||
|
||||
config OR3_PMSEL
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_SDRAM
|
||||
default 0x0 if OR3_PMSEL_BTB
|
||||
default 0x20 if OR3_PMSEL_KEPT_OPEN
|
||||
|
||||
config OR3_SCY
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_SCY_0
|
||||
default 0x10 if OR3_SCY_1
|
||||
default 0x20 if OR3_SCY_2
|
||||
default 0x30 if OR3_SCY_3
|
||||
default 0x40 if OR3_SCY_4
|
||||
default 0x50 if OR3_SCY_5
|
||||
default 0x60 if OR3_SCY_6
|
||||
default 0x70 if OR3_SCY_7
|
||||
default 0x80 if OR3_SCY_8
|
||||
default 0x90 if OR3_SCY_9
|
||||
default 0xa0 if OR3_SCY_10
|
||||
default 0xb0 if OR3_SCY_11
|
||||
default 0xc0 if OR3_SCY_12
|
||||
default 0xd0 if OR3_SCY_13
|
||||
default 0xe0 if OR3_SCY_14
|
||||
default 0xf0 if OR3_SCY_15
|
||||
|
||||
config OR3_PGS
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_PGS_SMALL
|
||||
default 0x400 if OR3_PGS_LARGE
|
||||
|
||||
config OR3_CSCT
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_CSCT_1_CYCLE
|
||||
default 0x0 if OR3_CSCT_2_CYCLE
|
||||
default 0x200 if OR3_CSCT_4_CYCLE
|
||||
default 0x200 if OR3_CSCT_8_CYCLE
|
||||
|
||||
config OR3_CST
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_CST_COINCIDENT
|
||||
default 0x100 if OR3_CST_QUARTER_CLOCK
|
||||
default 0x0 if OR3_CST_HALF_CLOCK
|
||||
default 0x100 if OR3_CST_ONE_CLOCK
|
||||
|
||||
config OR3_CHT
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_CHT_HALF_CLOCK
|
||||
default 0x80 if OR3_CHT_ONE_CLOCK
|
||||
default 0x0 if OR3_CHT_ONE_HALF_CLOCK
|
||||
default 0x80 if OR3_CHT_TWO_CLOCK
|
||||
|
||||
config OR3_RST
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_FCM
|
||||
default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
|
||||
default 0x8 if OR3_RST_ONE_CLOCK
|
||||
default 0x0 if OR3_RST_ONE_HALF_CLOCK
|
||||
|
||||
config OR3_CSNT
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_GPCM
|
||||
default 0x0 if OR3_CSNT_NORMAL
|
||||
default 0x800 if OR3_CSNT_EARLIER
|
||||
|
||||
config OR3_ACS
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_GPCM
|
||||
default 0x0 if OR3_ACS_SAME_TIME
|
||||
default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
|
||||
default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
|
||||
|
||||
config OR3_XACS
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_GPCM
|
||||
default 0x0 if OR3_XACS_NORMAL
|
||||
default 0x100 if OR3_XACS_EXTENDED
|
||||
|
||||
config OR3_SETA
|
||||
hex
|
||||
default 0x0 if !BR3_MACHINE_GPCM
|
||||
default 0x0 if OR3_SETA_INTERNAL
|
||||
default 0x8 if OR3_SETA_EXTERNAL
|
||||
|
||||
config OR3_TRLX
|
||||
hex
|
||||
default 0x0 if OR3_TRLX_NORMAL
|
||||
default 0x4 if OR3_TRLX_RELAXED
|
||||
|
||||
config OR3_EHTR
|
||||
hex
|
||||
default 0x0 if OR3_EHTR_NORMAL
|
||||
default 0x2 if OR3_EHTR_1_CYCLE
|
||||
default 0x0 if OR3_EHTR_4_CYCLE
|
||||
default 0x2 if OR3_EHTR_8_CYCLE
|
||||
|
||||
config OR3_EAD
|
||||
hex
|
||||
default 0x0 if ARCH_MPC8308
|
||||
default 0x0 if OR3_EAD_NONE
|
||||
default 0x1 if OR3_EAD_EXTRA
|
||||
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
Normal file
733
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
Normal file
@ -0,0 +1,733 @@
|
||||
menuconfig ELBC_BR4_OR4
|
||||
bool "ELBC BR4/OR4"
|
||||
|
||||
if ELBC_BR4_OR4
|
||||
|
||||
config BR4_OR4_NAME
|
||||
string "Identifier"
|
||||
|
||||
config BR4_OR4_BASE
|
||||
hex "Port base"
|
||||
|
||||
choice
|
||||
prompt "Port size"
|
||||
|
||||
config BR4_PORTSIZE_8BIT
|
||||
bool "8-bit"
|
||||
|
||||
config BR4_PORTSIZE_16BIT
|
||||
depends on !BR4_MACHINE_FCM
|
||||
bool "16-bit"
|
||||
|
||||
|
||||
config BR4_PORTSIZE_32BIT
|
||||
depends on !BR4_MACHINE_FCM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
bool "32-bit"
|
||||
|
||||
endchoice
|
||||
|
||||
if BR4_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Data Error Checking"
|
||||
|
||||
config BR4_ERRORCHECKING_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BR4_ERRORCHECKING_ECC_CHECKING
|
||||
bool "ECC checking / No ECC generation"
|
||||
|
||||
config BR4_ERRORCHECKING_BOTH
|
||||
bool "ECC checking and generation"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config BR4_WRITE_PROTECT
|
||||
bool "Write-protect"
|
||||
|
||||
config BR4_MACHINE_UPM
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Machine select"
|
||||
|
||||
config BR4_MACHINE_GPCM
|
||||
bool "GPCM"
|
||||
|
||||
config BR4_MACHINE_FCM
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "FCM"
|
||||
|
||||
config BR4_MACHINE_SDRAM
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360
|
||||
bool "SDRAM"
|
||||
|
||||
config BR4_MACHINE_UPMA
|
||||
select BR4_MACHINE_UPM
|
||||
bool "UPM (A)"
|
||||
|
||||
config BR4_MACHINE_UPMB
|
||||
select BR4_MACHINE_UPM
|
||||
bool "UPM (B)"
|
||||
|
||||
config BR4_MACHINE_UPMC
|
||||
select BR4_MACHINE_UPM
|
||||
bool "UPM (C)"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Atomic operations"
|
||||
|
||||
config BR4_ATOMIC_NONE
|
||||
bool "No atomic operations"
|
||||
|
||||
config BR4_ATOMIC_RAWA
|
||||
bool "Read-after-write-atomic"
|
||||
|
||||
config BR4_ATOMIC_WARA
|
||||
bool "Write-after-read-atomic"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Address mask"
|
||||
|
||||
config OR4_AM_32_KBYTES
|
||||
depends on !BR4_MACHINE_SDRAM
|
||||
bool "32 kb"
|
||||
|
||||
config OR4_AM_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config OR4_AM_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config OR4_AM_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config OR4_AM_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config OR4_AM_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config OR4_AM_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config OR4_AM_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config OR4_AM_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config OR4_AM_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config OR4_AM_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config OR4_AM_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
# XXX: Some boards define 128MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR4_AM_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
# XXX: Some boards define 256MB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR4_AM_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config OR4_AM_512_MBYTES
|
||||
depends on BR4_MACHINE_FCM
|
||||
bool "512 mb"
|
||||
|
||||
# XXX: Some boards define 1GB AM with GPCM, even though it should not be
|
||||
# possible according to the manuals
|
||||
config OR4_AM_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config OR4_AM_2_GBYTES
|
||||
depends on BR4_MACHINE_FCM
|
||||
bool "2 gb"
|
||||
|
||||
config OR4_AM_4_GBYTES
|
||||
depends on BR4_MACHINE_FCM
|
||||
bool "4 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
config OR4_XAM_SET
|
||||
bool "Set unused bytes after address mask"
|
||||
choice
|
||||
prompt "Buffer control disable"
|
||||
|
||||
config OR4_BCTLD_ASSERTED
|
||||
bool "Asserted"
|
||||
|
||||
config OR4_BCTLD_NOT_ASSERTED
|
||||
bool "Not asserted"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "Cycle length in bus clocks"
|
||||
|
||||
config OR4_SCY_0
|
||||
bool "No wait states"
|
||||
|
||||
config OR4_SCY_1
|
||||
bool "1 wait state"
|
||||
|
||||
config OR4_SCY_2
|
||||
bool "2 wait states"
|
||||
|
||||
config OR4_SCY_3
|
||||
bool "3 wait states"
|
||||
|
||||
config OR4_SCY_4
|
||||
bool "4 wait states"
|
||||
|
||||
config OR4_SCY_5
|
||||
bool "5 wait states"
|
||||
|
||||
config OR4_SCY_6
|
||||
bool "6 wait states"
|
||||
|
||||
config OR4_SCY_7
|
||||
bool "7 wait states"
|
||||
|
||||
config OR4_SCY_8
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "8 wait states"
|
||||
|
||||
config OR4_SCY_9
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "9 wait states"
|
||||
|
||||
config OR4_SCY_10
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "10 wait states"
|
||||
|
||||
config OR4_SCY_11
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "11 wait states"
|
||||
|
||||
config OR4_SCY_12
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "12 wait states"
|
||||
|
||||
config OR4_SCY_13
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "13 wait states"
|
||||
|
||||
config OR4_SCY_14
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "14 wait states"
|
||||
|
||||
config OR4_SCY_15
|
||||
depends on BR4_MACHINE_GPCM
|
||||
bool "15 wait states"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
|
||||
|
||||
if BR4_MACHINE_GPCM
|
||||
|
||||
choice
|
||||
prompt "Chip select negotiation time"
|
||||
|
||||
config OR4_CSNT_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR4_CSNT_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Address to chip-select setup"
|
||||
|
||||
config OR4_ACS_SAME_TIME
|
||||
bool "At the same time"
|
||||
|
||||
config OR4_ACS_HALF_CYCLE_EARLIER
|
||||
bool "Half of a bus clock cycle earlier"
|
||||
|
||||
config OR4_ACS_QUARTER_CYCLE_EARLIER
|
||||
bool "Half/Quarter of a bus clock cycle earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extra address to check-select setup"
|
||||
|
||||
config OR4_XACS_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR4_XACS_EXTENDED
|
||||
bool "Extended"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "External address termination"
|
||||
|
||||
config OR4_SETA_INTERNAL
|
||||
bool "Access is terminated internally"
|
||||
|
||||
config OR4_SETA_EXTERNAL
|
||||
bool "Access is terminated externally"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR4_MACHINE_GPCM
|
||||
|
||||
if BR4_MACHINE_FCM
|
||||
|
||||
choice
|
||||
prompt "NAND Flash EEPROM page size"
|
||||
|
||||
config OR4_PGS_SMALL
|
||||
bool "Small page device"
|
||||
|
||||
config OR4_PGS_LARGE
|
||||
bool "Large page device"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Chip select to command time"
|
||||
|
||||
config OR4_CSCT_1_CYCLE
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "1 cycle"
|
||||
|
||||
config OR4_CSCT_2_CYCLE
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "2 cycles"
|
||||
|
||||
config OR4_CSCT_4_CYCLE
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "4 cycles"
|
||||
|
||||
config OR4_CSCT_8_CYCLE
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "8 cycles"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command setup time"
|
||||
|
||||
config OR4_CST_COINCIDENT
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "Coincident with any command"
|
||||
|
||||
config OR4_CST_QUARTER_CLOCK
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "0.25 clocks after"
|
||||
|
||||
config OR4_CST_HALF_CLOCK
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "0.5 clocks after"
|
||||
|
||||
config OR4_CST_ONE_CLOCK
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "1 clock after"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Command hold time"
|
||||
|
||||
config OR4_CHT_HALF_CLOCK
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "0.5 clocks before"
|
||||
|
||||
config OR4_CHT_ONE_CLOCK
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "1 clock before"
|
||||
|
||||
config OR4_CHT_ONE_HALF_CLOCK
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "1.5 clocks before"
|
||||
|
||||
config OR4_CHT_TWO_CLOCK
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "2 clocks before"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Reset setup time"
|
||||
|
||||
config OR4_RST_THREE_QUARTER_CLOCK
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "0.75 clocks prior"
|
||||
|
||||
config OR4_RST_ONE_HALF_CLOCK
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "0.5 clocks prior"
|
||||
|
||||
config OR4_RST_ONE_CLOCK
|
||||
bool "1 clock prior"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR4_MACHINE_FCM
|
||||
|
||||
if BR4_MACHINE_UPM
|
||||
|
||||
choice
|
||||
prompt "Burst inhibit"
|
||||
|
||||
config OR4_BI_BURSTSUPPORT
|
||||
bool "Support burst access"
|
||||
|
||||
config OR4_BI_BURSTINHIBIT
|
||||
bool "Inhibit burst access"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR4_MACHINE_UPM
|
||||
|
||||
if BR4_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Number of column address lines"
|
||||
|
||||
config OR4_COLS_7
|
||||
bool "7"
|
||||
|
||||
config OR4_COLS_8
|
||||
bool "8"
|
||||
|
||||
config OR4_COLS_9
|
||||
bool "9"
|
||||
|
||||
config OR4_COLS_10
|
||||
bool "10"
|
||||
|
||||
config OR4_COLS_11
|
||||
bool "11"
|
||||
|
||||
config OR4_COLS_12
|
||||
bool "12"
|
||||
|
||||
config OR4_COLS_13
|
||||
bool "13"
|
||||
|
||||
config OR4_COLS_14
|
||||
bool "14"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Number of rows address lines"
|
||||
|
||||
config OR4_ROWS_9
|
||||
bool "9"
|
||||
|
||||
config OR4_ROWS_10
|
||||
bool "10"
|
||||
|
||||
config OR4_ROWS_11
|
||||
bool "11"
|
||||
|
||||
config OR4_ROWS_12
|
||||
bool "12"
|
||||
|
||||
config OR4_ROWS_13
|
||||
bool "13"
|
||||
|
||||
config OR4_ROWS_14
|
||||
bool "14"
|
||||
|
||||
config OR4_ROWS_15
|
||||
bool "15"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Page mode select"
|
||||
|
||||
config OR4_PMSEL_BTB
|
||||
bool "Back-to-back"
|
||||
|
||||
config OR4_PMSEL_KEPT_OPEN
|
||||
bool "Page kept open until page miss or refresh"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # BR4_MACHINE_SDRAM
|
||||
|
||||
choice
|
||||
prompt "Relaxed timing"
|
||||
|
||||
config OR4_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR4_TRLX_RELAXED
|
||||
bool "Relaxed"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended hold time"
|
||||
|
||||
config OR4_EHTR_NORMAL
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config OR4_EHTR_1_CYCLE
|
||||
depends on OR4_TRLX_NORMAL
|
||||
bool "1 idle clock cycle inserted"
|
||||
|
||||
config OR4_EHTR_4_CYCLE
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "4 idle clock cycles inserted"
|
||||
|
||||
config OR4_EHTR_8_CYCLE
|
||||
depends on OR4_TRLX_RELAXED
|
||||
bool "8 idle clock cycles inserted"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address latch delay"
|
||||
|
||||
config OR4_EAD_NONE
|
||||
bool "None"
|
||||
|
||||
config OR4_EAD_EXTRA
|
||||
bool "Extra"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
endif # ELBC_BR4_OR4
|
||||
|
||||
config BR4_PORTSIZE
|
||||
hex
|
||||
default 0x800 if BR4_PORTSIZE_8BIT
|
||||
default 0x1000 if BR4_PORTSIZE_16BIT
|
||||
default 0x1800 if BR4_PORTSIZE_32BIT
|
||||
|
||||
config BR4_ERRORCHECKING
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if BR4_ERRORCHECKING_DISABLED
|
||||
default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
|
||||
default 0x400 if BR4_ERRORCHECKING_BOTH
|
||||
|
||||
config BR4_WRITE_PROTECT_BIT
|
||||
hex
|
||||
default 0x0 if !BR4_WRITE_PROTECT
|
||||
default 0x100 if BR4_WRITE_PROTECT
|
||||
|
||||
config BR4_MACHINE
|
||||
hex
|
||||
default 0x0 if BR4_MACHINE_GPCM
|
||||
default 0x20 if BR4_MACHINE_FCM
|
||||
default 0x60 if BR4_MACHINE_SDRAM
|
||||
default 0x80 if BR4_MACHINE_UPMA
|
||||
default 0xa0 if BR4_MACHINE_UPMB
|
||||
default 0xc0 if BR4_MACHINE_UPMC
|
||||
|
||||
config BR4_ATOMIC
|
||||
hex
|
||||
default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
|
||||
default 0x0 if BR4_ATOMIC_NONE
|
||||
default 0x4 if BR4_ATOMIC_RAWA
|
||||
default 0x8 if BR4_ATOMIC_WARA
|
||||
|
||||
config BR4_VALID_BIT
|
||||
hex
|
||||
default 0x0 if !ELBC_BR4_OR4
|
||||
default 0x1 if ELBC_BR4_OR4
|
||||
|
||||
config OR4_AM
|
||||
hex
|
||||
default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
|
||||
default 0xffff0000 if OR4_AM_64_KBYTES
|
||||
default 0xfffe0000 if OR4_AM_128_KBYTES
|
||||
default 0xfffc0000 if OR4_AM_256_KBYTES
|
||||
default 0xfff80000 if OR4_AM_512_KBYTES
|
||||
default 0xfff00000 if OR4_AM_1_MBYTES
|
||||
default 0xffe00000 if OR4_AM_2_MBYTES
|
||||
default 0xffc00000 if OR4_AM_4_MBYTES
|
||||
default 0xff800000 if OR4_AM_8_MBYTES
|
||||
default 0xff000000 if OR4_AM_16_MBYTES
|
||||
default 0xfe000000 if OR4_AM_32_MBYTES
|
||||
default 0xfc000000 if OR4_AM_64_MBYTES
|
||||
default 0xf8000000 if OR4_AM_128_MBYTES
|
||||
default 0xf0000000 if OR4_AM_256_MBYTES
|
||||
default 0xe0000000 if OR4_AM_512_MBYTES
|
||||
default 0xc0000000 if OR4_AM_1_GBYTES
|
||||
default 0x80000000 if OR4_AM_2_GBYTES
|
||||
default 0x00000000 if OR4_AM_4_GBYTES
|
||||
|
||||
config OR4_XAM
|
||||
hex
|
||||
default 0x0 if !OR4_XAM_SET
|
||||
default 0x6000 if OR4_XAM_SET
|
||||
|
||||
config OR4_BCTLD
|
||||
hex
|
||||
default 0x0 if OR4_BCTLD_ASSERTED
|
||||
default 0x1000 if OR4_BCTLD_NOT_ASSERTED
|
||||
|
||||
config OR4_BI
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_UPM
|
||||
default 0x0 if OR4_BI_BURSTSUPPORT
|
||||
default 0x100 if OR4_BI_BURSTINHIBIT
|
||||
|
||||
config OR4_COLS
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_SDRAM
|
||||
default 0x0 if OR4_COLS_7
|
||||
default 0x400 if OR4_COLS_8
|
||||
default 0x800 if OR4_COLS_9
|
||||
default 0xc00 if OR4_COLS_10
|
||||
default 0x1000 if OR4_COLS_11
|
||||
default 0x1400 if OR4_COLS_12
|
||||
default 0x1800 if OR4_COLS_13
|
||||
default 0x1c00 if OR4_COLS_14
|
||||
|
||||
config OR4_ROWS
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_SDRAM
|
||||
default 0x0 if OR4_ROWS_9
|
||||
default 0x40 if OR4_ROWS_10
|
||||
default 0x80 if OR4_ROWS_11
|
||||
default 0xc0 if OR4_ROWS_12
|
||||
default 0x100 if OR4_ROWS_13
|
||||
default 0x140 if OR4_ROWS_14
|
||||
default 0x180 if OR4_ROWS_15
|
||||
|
||||
config OR4_PMSEL
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_SDRAM
|
||||
default 0x0 if OR4_PMSEL_BTB
|
||||
default 0x20 if OR4_PMSEL_KEPT_OPEN
|
||||
|
||||
config OR4_SCY
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_SCY_0
|
||||
default 0x10 if OR4_SCY_1
|
||||
default 0x20 if OR4_SCY_2
|
||||
default 0x30 if OR4_SCY_3
|
||||
default 0x40 if OR4_SCY_4
|
||||
default 0x50 if OR4_SCY_5
|
||||
default 0x60 if OR4_SCY_6
|
||||
default 0x70 if OR4_SCY_7
|
||||
default 0x80 if OR4_SCY_8
|
||||
default 0x90 if OR4_SCY_9
|
||||
default 0xa0 if OR4_SCY_10
|
||||
default 0xb0 if OR4_SCY_11
|
||||
default 0xc0 if OR4_SCY_12
|
||||
default 0xd0 if OR4_SCY_13
|
||||
default 0xe0 if OR4_SCY_14
|
||||
default 0xf0 if OR4_SCY_15
|
||||
|
||||
config OR4_PGS
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_PGS_SMALL
|
||||
default 0x400 if OR4_PGS_LARGE
|
||||
|
||||
config OR4_CSCT
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_CSCT_1_CYCLE
|
||||
default 0x0 if OR4_CSCT_2_CYCLE
|
||||
default 0x200 if OR4_CSCT_4_CYCLE
|
||||
default 0x200 if OR4_CSCT_8_CYCLE
|
||||
|
||||
config OR4_CST
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_CST_COINCIDENT
|
||||
default 0x100 if OR4_CST_QUARTER_CLOCK
|
||||
default 0x0 if OR4_CST_HALF_CLOCK
|
||||
default 0x100 if OR4_CST_ONE_CLOCK
|
||||
|
||||
config OR4_CHT
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_CHT_HALF_CLOCK
|
||||
default 0x80 if OR4_CHT_ONE_CLOCK
|
||||
default 0x0 if OR4_CHT_ONE_HALF_CLOCK
|
||||
default 0x80 if OR4_CHT_TWO_CLOCK
|
||||
|
||||
config OR4_RST
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_FCM
|
||||
default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
|
||||
default 0x8 if OR4_RST_ONE_CLOCK
|
||||
default 0x0 if OR4_RST_ONE_HALF_CLOCK
|
||||
|
||||
config OR4_CSNT
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_GPCM
|
||||
default 0x0 if OR4_CSNT_NORMAL
|
||||
default 0x800 if OR4_CSNT_EARLIER
|
||||
|
||||
config OR4_ACS
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_GPCM
|
||||
default 0x0 if OR4_ACS_SAME_TIME
|
||||
default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
|
||||
default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
|
||||
|
||||
config OR4_XACS
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_GPCM
|
||||
default 0x0 if OR4_XACS_NORMAL
|
||||
default 0x100 if OR4_XACS_EXTENDED
|
||||
|
||||
config OR4_SETA
|
||||
hex
|
||||
default 0x0 if !BR4_MACHINE_GPCM
|
||||
default 0x0 if OR4_SETA_INTERNAL
|
||||
default 0x8 if OR4_SETA_EXTERNAL
|
||||
|
||||
config OR4_TRLX
|
||||
hex
|
||||
default 0x0 if OR4_TRLX_NORMAL
|
||||
default 0x4 if OR4_TRLX_RELAXED
|
||||
|
||||
config OR4_EHTR
|
||||
hex
|
||||
default 0x0 if OR4_EHTR_NORMAL
|
||||
default 0x2 if OR4_EHTR_1_CYCLE
|
||||
default 0x0 if OR4_EHTR_4_CYCLE
|
||||
default 0x2 if OR4_EHTR_8_CYCLE
|
||||
|
||||
config OR4_EAD
|
||||
hex
|
||||
default 0x0 if ARCH_MPC8308
|
||||
default 0x0 if OR4_EAD_NONE
|
||||
default 0x1 if OR4_EAD_EXTRA
|
||||
186
arch/powerpc/cpu/mpc83xx/elbc/elbc.h
Normal file
186
arch/powerpc/cpu/mpc83xx/elbc/elbc.h
Normal file
@ -0,0 +1,186 @@
|
||||
#ifdef CONFIG_ELBC_BR0_OR0
|
||||
#define CONFIG_SYS_BR0_PRELIM (\
|
||||
CONFIG_BR0_OR0_BASE |\
|
||||
CONFIG_BR0_PORTSIZE |\
|
||||
CONFIG_BR0_ERRORCHECKING |\
|
||||
CONFIG_BR0_WRITE_PROTECT_BIT |\
|
||||
CONFIG_BR0_MACHINE |\
|
||||
CONFIG_BR0_ATOMIC |\
|
||||
CONFIG_BR0_VALID_BIT \
|
||||
)
|
||||
#define CONFIG_SYS_OR0_PRELIM (\
|
||||
CONFIG_OR0_AM |\
|
||||
CONFIG_OR0_XAM |\
|
||||
CONFIG_OR0_BCTLD |\
|
||||
CONFIG_OR0_BI |\
|
||||
CONFIG_OR0_COLS |\
|
||||
CONFIG_OR0_ROWS |\
|
||||
CONFIG_OR0_PMSEL |\
|
||||
CONFIG_OR0_SCY |\
|
||||
CONFIG_OR0_PGS |\
|
||||
CONFIG_OR0_CSCT |\
|
||||
CONFIG_OR0_CST |\
|
||||
CONFIG_OR0_CHT |\
|
||||
CONFIG_OR0_RST |\
|
||||
CONFIG_OR0_CSNT |\
|
||||
CONFIG_OR0_ACS |\
|
||||
CONFIG_OR0_XACS |\
|
||||
CONFIG_OR0_SETA |\
|
||||
CONFIG_OR0_TRLX |\
|
||||
CONFIG_OR0_EHTR |\
|
||||
CONFIG_OR0_EAD \
|
||||
)
|
||||
#endif /* CONFIG_ELBC_BR0_OR0 */
|
||||
|
||||
#ifdef CONFIG_ELBC_BR1_OR1
|
||||
#define CONFIG_SYS_BR1_PRELIM (\
|
||||
CONFIG_BR1_OR1_BASE |\
|
||||
CONFIG_BR1_PORTSIZE |\
|
||||
CONFIG_BR1_ERRORCHECKING |\
|
||||
CONFIG_BR1_WRITE_PROTECT_BIT |\
|
||||
CONFIG_BR1_MACHINE |\
|
||||
CONFIG_BR1_ATOMIC |\
|
||||
CONFIG_BR1_VALID_BIT \
|
||||
)
|
||||
#define CONFIG_SYS_OR1_PRELIM (\
|
||||
CONFIG_OR1_AM |\
|
||||
CONFIG_OR1_XAM |\
|
||||
CONFIG_OR1_BCTLD |\
|
||||
CONFIG_OR1_BI |\
|
||||
CONFIG_OR1_COLS |\
|
||||
CONFIG_OR1_ROWS |\
|
||||
CONFIG_OR1_PMSEL |\
|
||||
CONFIG_OR1_SCY |\
|
||||
CONFIG_OR1_PGS |\
|
||||
CONFIG_OR1_CSCT |\
|
||||
CONFIG_OR1_CST |\
|
||||
CONFIG_OR1_CHT |\
|
||||
CONFIG_OR1_RST |\
|
||||
CONFIG_OR1_CSNT |\
|
||||
CONFIG_OR1_ACS |\
|
||||
CONFIG_OR1_XACS |\
|
||||
CONFIG_OR1_SETA |\
|
||||
CONFIG_OR1_TRLX |\
|
||||
CONFIG_OR1_EHTR |\
|
||||
CONFIG_OR1_EAD \
|
||||
)
|
||||
#endif /* CONFIG_ELBC_BR1_OR1 */
|
||||
|
||||
#ifdef CONFIG_ELBC_BR2_OR2
|
||||
#define CONFIG_SYS_BR2_PRELIM (\
|
||||
CONFIG_BR2_OR2_BASE |\
|
||||
CONFIG_BR2_PORTSIZE |\
|
||||
CONFIG_BR2_ERRORCHECKING |\
|
||||
CONFIG_BR2_WRITE_PROTECT_BIT |\
|
||||
CONFIG_BR2_MACHINE |\
|
||||
CONFIG_BR2_ATOMIC |\
|
||||
CONFIG_BR2_VALID_BIT \
|
||||
)
|
||||
#define CONFIG_SYS_OR2_PRELIM (\
|
||||
CONFIG_OR2_AM |\
|
||||
CONFIG_OR2_XAM |\
|
||||
CONFIG_OR2_BCTLD |\
|
||||
CONFIG_OR2_BI |\
|
||||
CONFIG_OR2_COLS |\
|
||||
CONFIG_OR2_ROWS |\
|
||||
CONFIG_OR2_PMSEL |\
|
||||
CONFIG_OR2_SCY |\
|
||||
CONFIG_OR2_PGS |\
|
||||
CONFIG_OR2_CSCT |\
|
||||
CONFIG_OR2_CST |\
|
||||
CONFIG_OR2_CHT |\
|
||||
CONFIG_OR2_RST |\
|
||||
CONFIG_OR2_CSNT |\
|
||||
CONFIG_OR2_ACS |\
|
||||
CONFIG_OR2_XACS |\
|
||||
CONFIG_OR2_SETA |\
|
||||
CONFIG_OR2_TRLX |\
|
||||
CONFIG_OR2_EHTR |\
|
||||
CONFIG_OR2_EAD \
|
||||
)
|
||||
#endif /* CONFIG_ELBC_BR2_OR2 */
|
||||
|
||||
#ifdef CONFIG_ELBC_BR3_OR3
|
||||
#define CONFIG_SYS_BR3_PRELIM (\
|
||||
CONFIG_BR3_OR3_BASE |\
|
||||
CONFIG_BR3_PORTSIZE |\
|
||||
CONFIG_BR3_ERRORCHECKING |\
|
||||
CONFIG_BR3_WRITE_PROTECT_BIT |\
|
||||
CONFIG_BR3_MACHINE |\
|
||||
CONFIG_BR3_ATOMIC |\
|
||||
CONFIG_BR3_VALID_BIT \
|
||||
)
|
||||
#define CONFIG_SYS_OR3_PRELIM (\
|
||||
CONFIG_OR3_AM |\
|
||||
CONFIG_OR3_XAM |\
|
||||
CONFIG_OR3_BCTLD |\
|
||||
CONFIG_OR3_BI |\
|
||||
CONFIG_OR3_COLS |\
|
||||
CONFIG_OR3_ROWS |\
|
||||
CONFIG_OR3_PMSEL |\
|
||||
CONFIG_OR3_SCY |\
|
||||
CONFIG_OR3_PGS |\
|
||||
CONFIG_OR3_CSCT |\
|
||||
CONFIG_OR3_CST |\
|
||||
CONFIG_OR3_CHT |\
|
||||
CONFIG_OR3_RST |\
|
||||
CONFIG_OR3_CSNT |\
|
||||
CONFIG_OR3_ACS |\
|
||||
CONFIG_OR3_XACS |\
|
||||
CONFIG_OR3_SETA |\
|
||||
CONFIG_OR3_TRLX |\
|
||||
CONFIG_OR3_EHTR |\
|
||||
CONFIG_OR3_EAD \
|
||||
)
|
||||
#endif /* CONFIG_ELBC_BR3_OR3 */
|
||||
|
||||
#ifdef CONFIG_ELBC_BR4_OR4
|
||||
#define CONFIG_SYS_BR4_PRELIM (\
|
||||
CONFIG_BR4_OR4_BASE |\
|
||||
CONFIG_BR4_PORTSIZE |\
|
||||
CONFIG_BR4_ERRORCHECKING |\
|
||||
CONFIG_BR4_WRITE_PROTECT_BIT |\
|
||||
CONFIG_BR4_MACHINE |\
|
||||
CONFIG_BR4_ATOMIC |\
|
||||
CONFIG_BR4_VALID_BIT \
|
||||
)
|
||||
#define CONFIG_SYS_OR4_PRELIM (\
|
||||
CONFIG_OR4_AM |\
|
||||
CONFIG_OR4_XAM |\
|
||||
CONFIG_OR4_BCTLD |\
|
||||
CONFIG_OR4_BI |\
|
||||
CONFIG_OR4_COLS |\
|
||||
CONFIG_OR4_ROWS |\
|
||||
CONFIG_OR4_PMSEL |\
|
||||
CONFIG_OR4_SCY |\
|
||||
CONFIG_OR4_PGS |\
|
||||
CONFIG_OR4_CSCT |\
|
||||
CONFIG_OR4_CST |\
|
||||
CONFIG_OR4_CHT |\
|
||||
CONFIG_OR4_RST |\
|
||||
CONFIG_OR4_CSNT |\
|
||||
CONFIG_OR4_ACS |\
|
||||
CONFIG_OR4_XACS |\
|
||||
CONFIG_OR4_SETA |\
|
||||
CONFIG_OR4_TRLX |\
|
||||
CONFIG_OR4_EHTR |\
|
||||
CONFIG_OR4_EAD \
|
||||
)
|
||||
#endif /* CONFIG_ELBC_BR4_OR4 */
|
||||
|
||||
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
|
||||
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
|
||||
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
|
||||
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
|
||||
#endif
|
||||
@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob);
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
|
||||
#include <linux/immap_qe.h>
|
||||
|
||||
void fdt_fixup_muram (void *blob)
|
||||
@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
|
||||
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
|
||||
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
|
||||
#ifdef CONFIG_MPC8313
|
||||
#ifdef CONFIG_ARCH_MPC8313
|
||||
/*
|
||||
* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
|
||||
* h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
|
||||
@ -116,14 +116,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_NS16550
|
||||
do_fixup_by_compat_u32(blob, "ns16550",
|
||||
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
|
||||
do_fixup_by_compat_u32(blob, "ns16550",
|
||||
"clock-frequency", get_serial_clock(), 1);
|
||||
#endif
|
||||
|
||||
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
|
||||
fdt_fixup_muram (blob);
|
||||
#endif
|
||||
}
|
||||
|
||||
565
arch/powerpc/cpu/mpc83xx/hid/Kconfig
Normal file
565
arch/powerpc/cpu/mpc83xx/hid/Kconfig
Normal file
@ -0,0 +1,565 @@
|
||||
menu "HID setup"
|
||||
|
||||
menu "HID0 initial"
|
||||
|
||||
config HID0_INIT_EMCP
|
||||
bool "Enable machine check int on mcp"
|
||||
|
||||
config HID0_INIT_ECPE
|
||||
bool "Enable cache parity errors"
|
||||
|
||||
config HID0_INIT_EBA
|
||||
bool "Enable address parity checking"
|
||||
|
||||
config HID0_INIT_EBD
|
||||
bool "Enable data parity checking"
|
||||
|
||||
choice
|
||||
prompt "HID0 clock configuration"
|
||||
|
||||
config HID0_INIT_CLKOUT_OFF
|
||||
bool "Clock output off"
|
||||
|
||||
config HID0_INIT_CLKOUT_CORE_HALF
|
||||
bool "Core clock / 2"
|
||||
|
||||
config HID0_INIT_CLKOUT_CORE
|
||||
bool "Core clock"
|
||||
|
||||
config HID0_INIT_CLKOUT_BUS
|
||||
bool "Bus clock"
|
||||
|
||||
endchoice
|
||||
|
||||
config HID0_INIT_PAR
|
||||
bool "Disable precharge of artry_out"
|
||||
|
||||
config HID0_INIT_DOZE
|
||||
bool "Enable doze mode"
|
||||
|
||||
config HID0_INIT_NAP
|
||||
bool "Enable nap mode"
|
||||
|
||||
config HID0_INIT_SLEEP
|
||||
bool "Enable sleep mode"
|
||||
|
||||
config HID0_INIT_DPM
|
||||
bool "Enable dynamic power management"
|
||||
|
||||
config HID0_INIT_ICE
|
||||
bool "Enable instruction cache"
|
||||
|
||||
config HID0_INIT_DCE
|
||||
bool "Enable data cache"
|
||||
|
||||
config HID0_INIT_ILOCK
|
||||
bool "Lock instruction cache"
|
||||
|
||||
config HID0_INIT_DLOCK
|
||||
bool "Lock data cache"
|
||||
|
||||
config HID0_INIT_ICFI
|
||||
bool "Flash invalidate instruction cache"
|
||||
|
||||
config HID0_INIT_DCFI
|
||||
bool "Flash invalidate data cache"
|
||||
|
||||
config HID0_INIT_IFEM
|
||||
bool "Enable m bit on bus for instruction fetches"
|
||||
|
||||
config HID0_INIT_DECAREN
|
||||
bool "Decrementer auto reload"
|
||||
|
||||
config HID0_INIT_FBIOB
|
||||
bool "Force indirect branch on the bus"
|
||||
|
||||
config HID0_INIT_ABE
|
||||
bool "Enable address broadcast"
|
||||
|
||||
config HID0_INIT_NOOPTI
|
||||
bool "No-op data cache touch intructions"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "HID0 final"
|
||||
|
||||
config HID0_FINAL_EMCP
|
||||
bool "Enable machine check int on mcp"
|
||||
|
||||
config HID0_FINAL_ECPE
|
||||
bool "Enable cache parity errors"
|
||||
|
||||
config HID0_FINAL_EBA
|
||||
bool "Enable address parity checking"
|
||||
|
||||
config HID0_FINAL_EBD
|
||||
bool "Enable data parity checking"
|
||||
|
||||
choice
|
||||
prompt "HID0 clock configuration"
|
||||
|
||||
config HID0_FINAL_CLKOUT_OFF
|
||||
bool "Clock output off"
|
||||
|
||||
config HID0_FINAL_CLKOUT_CORE_HALF
|
||||
bool "Core clock / 2"
|
||||
|
||||
config HID0_FINAL_CLKOUT_CORE
|
||||
bool "Core clock"
|
||||
|
||||
config HID0_FINAL_CLKOUT_BUS
|
||||
bool "Bus clock"
|
||||
|
||||
endchoice
|
||||
|
||||
config HID0_FINAL_PAR
|
||||
bool "Disable precharge of artry_out"
|
||||
|
||||
config HID0_FINAL_DOZE
|
||||
bool "Enable doze mode"
|
||||
|
||||
config HID0_FINAL_NAP
|
||||
bool "Enable nap mode"
|
||||
|
||||
config HID0_FINAL_SLEEP
|
||||
bool "Enable sleep mode"
|
||||
|
||||
config HID0_FINAL_DPM
|
||||
bool "Enable dynamic power management"
|
||||
|
||||
config HID0_FINAL_ICE
|
||||
bool "Enable instruction cache"
|
||||
|
||||
config HID0_FINAL_DCE
|
||||
bool "Enable data cache"
|
||||
|
||||
config HID0_FINAL_ILOCK
|
||||
bool "Lock instruction cache"
|
||||
|
||||
config HID0_FINAL_DLOCK
|
||||
bool "Lock data cache"
|
||||
|
||||
config HID0_FINAL_ICFI
|
||||
bool "Flash invalidate instruction cache"
|
||||
|
||||
config HID0_FINAL_DCFI
|
||||
bool "Flash invalidate data cache"
|
||||
|
||||
config HID0_FINAL_IFEM
|
||||
bool "Enable m bit on bus for instruction fetches"
|
||||
|
||||
config HID0_FINAL_DECAREN
|
||||
bool "Decrementer auto reload"
|
||||
|
||||
config HID0_FINAL_FBIOB
|
||||
bool "Force indirect branch on the bus"
|
||||
|
||||
config HID0_FINAL_ABE
|
||||
bool "Enable address broadcast"
|
||||
|
||||
config HID0_FINAL_NOOPTI
|
||||
bool "No-op data cache touch intructions"
|
||||
|
||||
endmenu
|
||||
|
||||
config HID0_INIT_EMCP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_EMCP
|
||||
default 0x80000000 if HID0_INIT_EMCP
|
||||
|
||||
config HID0_INIT_ECPE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_ECPE
|
||||
default 0x40000000 if HID0_INIT_ECPE
|
||||
|
||||
config HID0_INIT_EBA_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_EBA
|
||||
default 0x20000000 if HID0_INIT_EBA
|
||||
|
||||
config HID0_INIT_EBD_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_EBD
|
||||
default 0x10000000 if HID0_INIT_EBD
|
||||
|
||||
config HID0_INIT_CLKOUT
|
||||
hex
|
||||
default 0x0 if HID0_INIT_CLKOUT_OFF
|
||||
default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF
|
||||
default 0x2000000 if HID0_INIT_CLKOUT_CORE
|
||||
default 0xa000000 if HID0_INIT_CLKOUT_BUS
|
||||
|
||||
config HID0_INIT_PAR_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_PAR
|
||||
default 0x1000000 if HID0_INIT_PAR
|
||||
|
||||
config HID0_INIT_DOZE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DOZE
|
||||
default 0x800000 if HID0_INIT_DOZE
|
||||
|
||||
config HID0_INIT_NAP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_NAP
|
||||
default 0x400000 if HID0_INIT_NAP
|
||||
|
||||
config HID0_INIT_SLEEP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_SLEEP
|
||||
default 0x200000 if HID0_INIT_SLEEP
|
||||
|
||||
config HID0_INIT_DPM_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DPM
|
||||
default 0x100000 if HID0_INIT_DPM
|
||||
|
||||
config HID0_INIT_ICE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_ICE
|
||||
default 0x8000 if HID0_INIT_ICE
|
||||
|
||||
config HID0_INIT_DCE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DCE
|
||||
default 0x4000 if HID0_INIT_DCE
|
||||
|
||||
config HID0_INIT_ILOCK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_ILOCK
|
||||
default 0x2000 if HID0_INIT_ILOCK
|
||||
|
||||
config HID0_INIT_DLOCK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DLOCK
|
||||
default 0x1000 if HID0_INIT_DLOCK
|
||||
|
||||
config HID0_INIT_ICFI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_ICFI
|
||||
default 0x800 if HID0_INIT_ICFI
|
||||
|
||||
config HID0_INIT_DCFI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DCFI
|
||||
default 0x400 if HID0_INIT_DCFI
|
||||
|
||||
config HID0_INIT_IFEM_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_IFEM
|
||||
default 0x80 if HID0_INIT_IFEM
|
||||
|
||||
config HID0_INIT_DECAREN_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_DECAREN
|
||||
default 0x40 if HID0_INIT_DECAREN
|
||||
|
||||
config HID0_INIT_FBIOB_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_FBIOB
|
||||
default 0x10 if HID0_INIT_FBIOB
|
||||
|
||||
config HID0_INIT_ABE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_ABE
|
||||
default 0x8 if HID0_INIT_ABE
|
||||
|
||||
config HID0_INIT_NOOPTI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_INIT_NOOPTI
|
||||
default 0x1 if HID0_INIT_NOOPTI
|
||||
|
||||
config HID0_FINAL_EMCP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_EMCP
|
||||
default 0x80000000 if HID0_FINAL_EMCP
|
||||
|
||||
config HID0_FINAL_ECPE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ECPE
|
||||
default 0x40000000 if HID0_FINAL_ECPE
|
||||
|
||||
config HID0_FINAL_EBA_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_EBA
|
||||
default 0x20000000 if HID0_FINAL_EBA
|
||||
|
||||
config HID0_FINAL_EBD_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_EBD
|
||||
default 0x10000000 if HID0_FINAL_EBD
|
||||
|
||||
config HID0_FINAL_CLKOUT
|
||||
hex
|
||||
default 0x0 if HID0_FINAL_CLKOUT_OFF
|
||||
default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF
|
||||
default 0x2000000 if HID0_FINAL_CLKOUT_CORE
|
||||
default 0xa000000 if HID0_FINAL_CLKOUT_BUS
|
||||
|
||||
config HID0_FINAL_SBCLK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_SBCLK
|
||||
default 0x8000000 if HID0_FINAL_SBCLK
|
||||
|
||||
config HID0_FINAL_ECLK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ECLK
|
||||
default 0x2000000 if HID0_FINAL_ECLK
|
||||
|
||||
config HID0_FINAL_PAR_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_PAR
|
||||
default 0x1000000 if HID0_FINAL_PAR
|
||||
|
||||
config HID0_FINAL_DOZE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DOZE
|
||||
default 0x800000 if HID0_FINAL_DOZE
|
||||
|
||||
config HID0_FINAL_NAP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_NAP
|
||||
default 0x400000 if HID0_FINAL_NAP
|
||||
|
||||
config HID0_FINAL_SLEEP_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_SLEEP
|
||||
default 0x200000 if HID0_FINAL_SLEEP
|
||||
|
||||
config HID0_FINAL_DPM_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DPM
|
||||
default 0x100000 if HID0_FINAL_DPM
|
||||
|
||||
config HID0_FINAL_ICE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ICE
|
||||
default 0x8000 if HID0_FINAL_ICE
|
||||
|
||||
config HID0_FINAL_DCE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DCE
|
||||
default 0x4000 if HID0_FINAL_DCE
|
||||
|
||||
config HID0_FINAL_ILOCK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ILOCK
|
||||
default 0x2000 if HID0_FINAL_ILOCK
|
||||
|
||||
config HID0_FINAL_DLOCK_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DLOCK
|
||||
default 0x1000 if HID0_FINAL_DLOCK
|
||||
|
||||
config HID0_FINAL_ICFI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ICFI
|
||||
default 0x800 if HID0_FINAL_ICFI
|
||||
|
||||
config HID0_FINAL_DCFI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DCFI
|
||||
default 0x400 if HID0_FINAL_DCFI
|
||||
|
||||
config HID0_FINAL_IFEM_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_IFEM
|
||||
default 0x80 if HID0_FINAL_IFEM
|
||||
|
||||
config HID0_FINAL_DECAREN_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_DECAREN
|
||||
default 0x40 if HID0_FINAL_DECAREN
|
||||
|
||||
config HID0_FINAL_FBIOB_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_FBIOB
|
||||
default 0x10 if HID0_FINAL_FBIOB
|
||||
|
||||
config HID0_FINAL_ABE_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_ABE
|
||||
default 0x8 if HID0_FINAL_ABE
|
||||
|
||||
config HID0_FINAL_NOOPTI_BIT
|
||||
hex
|
||||
default 0x0 if !HID0_FINAL_NOOPTI
|
||||
default 0x1 if HID0_FINAL_NOOPTI
|
||||
|
||||
menu "HID2"
|
||||
|
||||
config HID2_LET
|
||||
bool "True little-endian mode"
|
||||
|
||||
config HID2_IFEB
|
||||
bool "Instruction fetch burst extension"
|
||||
|
||||
config HID2_MESISTATE
|
||||
bool "MESI state enable"
|
||||
|
||||
config HID2_IFEC
|
||||
bool "Instruction fetch cancel extension"
|
||||
|
||||
config HID2_EBQS
|
||||
bool "BIU queue sharing"
|
||||
|
||||
config HID2_EBPX
|
||||
bool "BIU pipeline extension"
|
||||
|
||||
if !ARCH_MPC8360
|
||||
|
||||
config HID2_ELRW
|
||||
bool "Weighted LRU"
|
||||
|
||||
config HID2_NOKS
|
||||
bool "No kill for snoop"
|
||||
|
||||
endif
|
||||
|
||||
config HID2_HBE
|
||||
bool "High bat enable"
|
||||
|
||||
choice
|
||||
prompt "Instruction cache way-lock"
|
||||
|
||||
config HID2_IWLCK_NONE
|
||||
bool "No ways locked"
|
||||
|
||||
config HID2_IWLCK_0
|
||||
bool "Way 0 locked"
|
||||
|
||||
config HID2_IWLCK_1
|
||||
bool "Way 0 through 1 locked"
|
||||
|
||||
config HID2_IWLCK_2
|
||||
bool "Way 0 through 2 locked"
|
||||
|
||||
if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
|
||||
config HID2_IWLCK_3
|
||||
bool "Way 0 through 3 locked"
|
||||
|
||||
config HID2_IWLCK_4
|
||||
bool "Way 0 through 4 locked"
|
||||
|
||||
config HID2_IWLCK_5
|
||||
bool "Way 0 through 5 locked"
|
||||
|
||||
config HID2_IWLCK_6
|
||||
bool "Way 0 through 6 locked"
|
||||
|
||||
endif
|
||||
|
||||
endchoice
|
||||
|
||||
config HID2_ICWP
|
||||
bool "Instruction cache way protection"
|
||||
|
||||
choice
|
||||
prompt "Data cache way-lock"
|
||||
|
||||
config HID2_DWLCK_NONE
|
||||
bool "No ways locked"
|
||||
|
||||
config HID2_DWLCK_0
|
||||
bool "Way 0 locked"
|
||||
|
||||
config HID2_DWLCK_1
|
||||
bool "Way 0 through 1 locked"
|
||||
|
||||
config HID2_DWLCK_2
|
||||
bool "Way 0 through 2 locked"
|
||||
|
||||
if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
|
||||
|
||||
config HID2_DWLCK_3
|
||||
bool "Way 0 through 3 locked"
|
||||
|
||||
config HID2_DWLCK_4
|
||||
bool "Way 0 through 4 locked"
|
||||
|
||||
config HID2_DWLCK_5
|
||||
bool "Way 0 through 5 locked"
|
||||
|
||||
config HID2_DWLCK_6
|
||||
bool "Way 0 through 6 locked"
|
||||
|
||||
endif
|
||||
|
||||
endchoice
|
||||
|
||||
config HID2_LET_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_LET
|
||||
default 0x8000000 if HID2_LET
|
||||
|
||||
config HID2_IFEB_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_IFEB
|
||||
default 0x4000000 if HID2_IFEB
|
||||
|
||||
config HID2_MESISTATE_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_MESISTATE
|
||||
default 0x1000000 if HID2_MESISTATE
|
||||
|
||||
config HID2_IFEC_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_IFEC
|
||||
default 0x800000 if HID2_IFEC
|
||||
|
||||
config HID2_EBQS_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_EBQS
|
||||
default 0x400000 if HID2_EBQS
|
||||
|
||||
config HID2_EBPX_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_EBPX
|
||||
default 0x200000 if HID2_EBPX
|
||||
|
||||
config HID2_ELRW_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_ELRW
|
||||
default 0x100000 if HID2_ELRW
|
||||
|
||||
config HID2_NOKS_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_NOKS
|
||||
default 0x80000 if HID2_NOKS
|
||||
|
||||
config HID2_HBE_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_HBE
|
||||
default 0x40000 if HID2_HBE
|
||||
|
||||
config HID2_IWLCK
|
||||
hex
|
||||
default 0x0 if HID2_IWLCK_NONE
|
||||
default 0x2000 if HID2_IWLCK_0
|
||||
default 0x4000 if HID2_IWLCK_1
|
||||
default 0x6000 if HID2_IWLCK_2
|
||||
default 0x8000 if HID2_IWLCK_3
|
||||
default 0xA000 if HID2_IWLCK_4
|
||||
default 0xC000 if HID2_IWLCK_5
|
||||
default 0xE000 if HID2_IWLCK_6
|
||||
|
||||
config HID2_ICWP_BIT
|
||||
hex
|
||||
default 0x0 if !HID2_ICWP
|
||||
default 0x1000 if HID2_ICWP
|
||||
|
||||
config HID2_DWLCK
|
||||
hex
|
||||
default 0x0 if HID2_DWLCK_NONE
|
||||
default 0x20 if HID2_DWLCK_0
|
||||
default 0x40 if HID2_DWLCK_1
|
||||
default 0x60 if HID2_DWLCK_2
|
||||
default 0x80 if HID2_DWLCK_3
|
||||
default 0xA0 if HID2_DWLCK_4
|
||||
default 0xC0 if HID2_DWLCK_5
|
||||
default 0xE0 if HID2_DWLCK_6
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
72
arch/powerpc/cpu/mpc83xx/hid/hid.h
Normal file
72
arch/powerpc/cpu/mpc83xx/hid/hid.h
Normal file
@ -0,0 +1,72 @@
|
||||
#define CONFIG_SYS_HID0_FINAL ( \
|
||||
CONFIG_HID0_FINAL_ABE_BIT |\
|
||||
CONFIG_HID0_FINAL_CLKOUT |\
|
||||
CONFIG_HID0_FINAL_DCE_BIT |\
|
||||
CONFIG_HID0_FINAL_DCFI_BIT |\
|
||||
CONFIG_HID0_FINAL_DECAREN_BIT |\
|
||||
CONFIG_HID0_FINAL_DLOCK_BIT |\
|
||||
CONFIG_HID0_FINAL_DOZE_BIT |\
|
||||
CONFIG_HID0_FINAL_DPM_BIT |\
|
||||
CONFIG_HID0_FINAL_EBA_BIT |\
|
||||
CONFIG_HID0_FINAL_EBD_BIT |\
|
||||
CONFIG_HID0_FINAL_ECLK_BIT |\
|
||||
CONFIG_HID0_FINAL_ECPE_BIT |\
|
||||
CONFIG_HID0_FINAL_EMCP_BIT |\
|
||||
CONFIG_HID0_FINAL_FBIOB_BIT |\
|
||||
CONFIG_HID0_FINAL_ICE_BIT |\
|
||||
CONFIG_HID0_FINAL_ICFI_BIT |\
|
||||
CONFIG_HID0_FINAL_IFEM_BIT |\
|
||||
CONFIG_HID0_FINAL_ILOCK_BIT |\
|
||||
CONFIG_HID0_FINAL_NAP_BIT |\
|
||||
CONFIG_HID0_FINAL_NOOPTI_BIT |\
|
||||
CONFIG_HID0_FINAL_PAR_BIT |\
|
||||
CONFIG_HID0_FINAL_SBCLK_BIT |\
|
||||
CONFIG_HID0_FINAL_SLEEP_BIT \
|
||||
)
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT ( \
|
||||
CONFIG_HID0_INIT_ABE_BIT |\
|
||||
CONFIG_HID0_INIT_CLKOUT |\
|
||||
CONFIG_HID0_INIT_DCE_BIT |\
|
||||
CONFIG_HID0_INIT_DCFI_BIT |\
|
||||
CONFIG_HID0_INIT_DECAREN_BIT |\
|
||||
CONFIG_HID0_INIT_DLOCK_BIT |\
|
||||
CONFIG_HID0_INIT_DOZE_BIT |\
|
||||
CONFIG_HID0_INIT_DPM_BIT |\
|
||||
CONFIG_HID0_INIT_EBA_BIT |\
|
||||
CONFIG_HID0_INIT_EBD_BIT |\
|
||||
CONFIG_HID0_INIT_ECPE_BIT |\
|
||||
CONFIG_HID0_INIT_EMCP_BIT |\
|
||||
CONFIG_HID0_INIT_FBIOB_BIT |\
|
||||
CONFIG_HID0_INIT_ICE_BIT |\
|
||||
CONFIG_HID0_INIT_ICFI_BIT |\
|
||||
CONFIG_HID0_INIT_IFEM_BIT |\
|
||||
CONFIG_HID0_INIT_ILOCK_BIT |\
|
||||
CONFIG_HID0_INIT_NAP_BIT |\
|
||||
CONFIG_HID0_INIT_NOOPTI_BIT |\
|
||||
CONFIG_HID0_INIT_PAR_BIT |\
|
||||
CONFIG_HID0_INIT_SLEEP_BIT \
|
||||
)
|
||||
|
||||
#ifdef CONFIG_TARGET_IDS8313
|
||||
/* IDS8313 defines a reserved bit; keep to not break compatibility */
|
||||
#define CONFIG_HID2_SPECIAL 0x00020000
|
||||
#else
|
||||
#define CONFIG_HID2_SPECIAL 0x0
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID2 ( \
|
||||
CONFIG_HID2_LET_BIT |\
|
||||
CONFIG_HID2_IFEB_BIT |\
|
||||
CONFIG_HID2_MESISTATE_BIT |\
|
||||
CONFIG_HID2_IFEC_BIT |\
|
||||
CONFIG_HID2_EBQS_BIT |\
|
||||
CONFIG_HID2_EBPX_BIT |\
|
||||
CONFIG_HID2_ELRW_BIT |\
|
||||
CONFIG_HID2_NOKS_BIT |\
|
||||
CONFIG_HID2_HBE_BIT |\
|
||||
CONFIG_HID2_IWLCK |\
|
||||
CONFIG_HID2_ICWP_BIT |\
|
||||
CONFIG_HID2_DWLCK |\
|
||||
CONFIG_HID2_SPECIAL \
|
||||
)
|
||||
816
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
Normal file
816
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
Normal file
@ -0,0 +1,816 @@
|
||||
menu "Reset Configuration Word"
|
||||
|
||||
choice
|
||||
prompt "Local bus memory controller clock mode"
|
||||
|
||||
config LBMC_CLOCK_MODE_1_1
|
||||
bool "1 : 1"
|
||||
|
||||
config LBMC_CLOCK_MODE_1_2
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
|
||||
bool "1 : 2"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "DDR SDRAM memory controller clock mode"
|
||||
|
||||
config DDR_MC_CLOCK_MODE_1_2
|
||||
bool "1 : 2"
|
||||
|
||||
config DDR_MC_CLOCK_MODE_1_1
|
||||
depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
|
||||
bool "1 : 1"
|
||||
|
||||
endchoice
|
||||
|
||||
if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
|
||||
|
||||
choice
|
||||
prompt "System PLL VCO division"
|
||||
|
||||
config SYSTEM_PLL_VCO_DIV_1
|
||||
depends on !ARCH_MPC837X
|
||||
bool "1"
|
||||
|
||||
config SYSTEM_PLL_VCO_DIV_2
|
||||
bool "2"
|
||||
|
||||
config SYSTEM_PLL_VCO_DIV_4
|
||||
depends on !ARCH_MPC831X
|
||||
bool "4"
|
||||
|
||||
config SYSTEM_PLL_VCO_DIV_8
|
||||
depends on !ARCH_MPC831X
|
||||
bool "8"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
choice
|
||||
prompt "System PLL multiplication factor"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_2_1
|
||||
bool "2 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_3_1
|
||||
bool "3 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_4_1
|
||||
bool "4 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_5_1
|
||||
bool "5 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_6_1
|
||||
bool "6 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_7_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "7 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_8_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "8 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_9_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "9 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_10_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "10 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_11_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "11 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_12_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "12 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_13_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "13 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_14_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "14 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_15_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
|
||||
bool "15 : 1"
|
||||
|
||||
config SYSTEM_PLL_FACTOR_16_1
|
||||
depends on ARCH_MPC8349 || ARCH_MPV8360
|
||||
bool "16 : 1"
|
||||
|
||||
endchoice
|
||||
|
||||
config CORE_PLL_BYPASS
|
||||
bool "Core PLL bypassed"
|
||||
|
||||
if !CORE_PLL_BYPASS
|
||||
|
||||
choice
|
||||
prompt "Core PLL Ratio"
|
||||
|
||||
config CORE_PLL_RATIO_1_1
|
||||
bool "1 : 1"
|
||||
|
||||
config CORE_PLL_RATIO_15_1
|
||||
bool "1.5 : 1"
|
||||
|
||||
config CORE_PLL_RATIO_2_1
|
||||
bool "2 : 1"
|
||||
|
||||
config CORE_PLL_RATIO_25_1
|
||||
bool "2.5 : 1"
|
||||
|
||||
config CORE_PLL_RATIO_3_1
|
||||
bool "3 : 1"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Core PLL VCO Divider"
|
||||
|
||||
config CORE_PLL_VCO_DIVIDER_2
|
||||
bool "2"
|
||||
|
||||
config CORE_PLL_VCO_DIVIDER_4
|
||||
bool "4"
|
||||
|
||||
config CORE_PLL_VCO_DIVIDER_8
|
||||
depends on !ARCH_MPC8315
|
||||
bool "8"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if MPC83XX_QUICC_ENGINE
|
||||
|
||||
choice
|
||||
prompt "QUICC Engine PLL VCO Divider"
|
||||
|
||||
config QUICC_VCO_DIVIDER_2
|
||||
bool "2"
|
||||
|
||||
config QUICC_VCO_DIVIDER_4
|
||||
bool "4"
|
||||
|
||||
config QUICC_VCO_DIVIDER_8
|
||||
depends on ARCH_MPC8309
|
||||
bool "8"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "QUICC Engine PLL division factor"
|
||||
|
||||
config QUICC_DIV_FACTOR_1
|
||||
bool "1"
|
||||
|
||||
config QUICC_DIV_FACTOR_2
|
||||
bool "2"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "QUICC Engine PLL multiplication factor"
|
||||
|
||||
config QUICC_MULT_FACTOR_2
|
||||
bool "2"
|
||||
|
||||
config QUICC_MULT_FACTOR_3
|
||||
bool "3"
|
||||
|
||||
config QUICC_MULT_FACTOR_4
|
||||
bool "4"
|
||||
|
||||
config QUICC_MULT_FACTOR_5
|
||||
bool "5"
|
||||
|
||||
config QUICC_MULT_FACTOR_6
|
||||
bool "6"
|
||||
|
||||
config QUICC_MULT_FACTOR_7
|
||||
bool "7"
|
||||
|
||||
config QUICC_MULT_FACTOR_8
|
||||
bool "8"
|
||||
|
||||
config QUICC_MULT_FACTOR_9
|
||||
depends on ARCH_MPC8360
|
||||
bool "9"
|
||||
|
||||
config QUICC_MULT_FACTOR_10
|
||||
depends on ARCH_MPC8360
|
||||
bool "10"
|
||||
|
||||
config QUICC_MULT_FACTOR_11
|
||||
depends on ARCH_MPC8360
|
||||
bool "11"
|
||||
|
||||
config QUICC_MULT_FACTOR_12
|
||||
depends on ARCH_MPC8360
|
||||
bool "12"
|
||||
|
||||
config QUICC_MULT_FACTOR_13
|
||||
depends on ARCH_MPC8360
|
||||
bool "13"
|
||||
|
||||
config QUICC_MULT_FACTOR_14
|
||||
depends on ARCH_MPC8360
|
||||
bool "14"
|
||||
|
||||
config QUICC_MULT_FACTOR_15
|
||||
depends on ARCH_MPC8360
|
||||
bool "15"
|
||||
|
||||
config QUICC_MULT_FACTOR_16
|
||||
depends on ARCH_MPC8360
|
||||
bool "16"
|
||||
|
||||
config QUICC_MULT_FACTOR_17
|
||||
depends on ARCH_MPC8360
|
||||
bool "17"
|
||||
|
||||
config QUICC_MULT_FACTOR_18
|
||||
depends on ARCH_MPC8360
|
||||
bool "18"
|
||||
|
||||
config QUICC_MULT_FACTOR_19
|
||||
depends on ARCH_MPC8360
|
||||
bool "19"
|
||||
|
||||
config QUICC_MULT_FACTOR_20
|
||||
depends on ARCH_MPC8360
|
||||
bool "20"
|
||||
|
||||
config QUICC_MULT_FACTOR_21
|
||||
depends on ARCH_MPC8360
|
||||
bool "21"
|
||||
|
||||
config QUICC_MULT_FACTOR_22
|
||||
depends on ARCH_MPC8360
|
||||
bool "22"
|
||||
|
||||
config QUICC_MULT_FACTOR_23
|
||||
depends on ARCH_MPC8360
|
||||
bool "23"
|
||||
|
||||
config QUICC_MULT_FACTOR_24
|
||||
depends on ARCH_MPC8360
|
||||
bool "24"
|
||||
|
||||
config QUICC_MULT_FACTOR_25
|
||||
depends on ARCH_MPC8360
|
||||
bool "25"
|
||||
|
||||
config QUICC_MULT_FACTOR_26
|
||||
depends on ARCH_MPC8360
|
||||
bool "26"
|
||||
|
||||
config QUICC_MULT_FACTOR_27
|
||||
depends on ARCH_MPC8360
|
||||
bool "27"
|
||||
|
||||
config QUICC_MULT_FACTOR_28
|
||||
depends on ARCH_MPC8360
|
||||
bool "28"
|
||||
|
||||
config QUICC_MULT_FACTOR_29
|
||||
depends on ARCH_MPC8360
|
||||
bool "29"
|
||||
|
||||
config QUICC_MULT_FACTOR_30
|
||||
depends on ARCH_MPC8360
|
||||
bool "30"
|
||||
|
||||
config QUICC_MULT_FACTOR_31
|
||||
depends on ARCH_MPC8360
|
||||
bool "31"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if MPC83XX_PCI_SUPPORT
|
||||
|
||||
choice
|
||||
prompt "PCI host mode"
|
||||
|
||||
config PCI_HOST_MODE_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
config PCI_HOST_MODE_ENABLE
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8349
|
||||
|
||||
choice
|
||||
prompt "PCI 64-bit mode"
|
||||
|
||||
config PCI_64BIT_MODE_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
config PCI_64BIT_MODE_ENABLE
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
choice
|
||||
prompt "PCI internal arbiter 1 mode"
|
||||
|
||||
config PCI_INT_ARBITER1_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
config PCI_INT_ARBITER1_ENABLE
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8349
|
||||
|
||||
choice
|
||||
prompt "PCI internal arbiter 2 mode"
|
||||
|
||||
config PCI_INT_ARBITER2_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
config PCI_INT_ARBITER2_ENABLE
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "PCI clock output drive"
|
||||
|
||||
config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
|
||||
bool "Disabled"
|
||||
|
||||
config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
choice
|
||||
prompt "Core disable mode"
|
||||
|
||||
config CORE_DISABLE_MODE_OFF
|
||||
bool "Off"
|
||||
|
||||
config CORE_DISABLE_MODE_ON
|
||||
bool "On"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Boot Memory Space"
|
||||
|
||||
config BOOT_MEMORY_SPACE_HIGH
|
||||
bool "High"
|
||||
|
||||
config BOOT_MEMORY_SPACE_LOW
|
||||
bool "Low"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Boot Sequencer Configuration"
|
||||
|
||||
config BOOT_SEQUENCER_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config BOOT_SEQUENCER_NORMAL_I2C
|
||||
bool "Normal I2C"
|
||||
|
||||
config BOOT_SEQUENCER_EXTENDED_I2C
|
||||
bool "Extended I2C"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Software Watchdog"
|
||||
|
||||
config SOFTWARE_WATCHDOG_DISABLED
|
||||
bool "Disabled"
|
||||
|
||||
config SOFTWARE_WATCHDOG_ENABLED
|
||||
bool "Enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Boot ROM interface location"
|
||||
|
||||
config BOOT_ROM_INTERFACE_DDR_SDRAM
|
||||
bool "DDR_SDRAM"
|
||||
|
||||
config BOOT_ROM_INTERFACE_PCI1
|
||||
depends on MPC83XX_PCI_SUPPORT
|
||||
bool "PCI1"
|
||||
|
||||
config BOOT_ROM_INTERFACE_PCI2
|
||||
depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
|
||||
bool "PCI2"
|
||||
|
||||
config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
||||
depends on ARCH_MPC837X
|
||||
bool "PCI2"
|
||||
|
||||
config BOOT_ROM_INTERFACE_ESDHC
|
||||
depends on ARCH_MPC8309
|
||||
bool "eSDHC"
|
||||
|
||||
config BOOT_ROM_INTERFACE_SPI
|
||||
depends on ARCH_MPC8309
|
||||
bool "SPI"
|
||||
|
||||
config BOOT_ROM_INTERFACE_GPCM_8BIT
|
||||
bool "Local bus GPCM - 8-bit ROM"
|
||||
|
||||
config BOOT_ROM_INTERFACE_GPCM_16BIT
|
||||
bool "Local bus GPCM - 16-bit ROM"
|
||||
|
||||
config BOOT_ROM_INTERFACE_GPCM_32BIT
|
||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
|
||||
bool "Local bus GPCM - 32-bit ROM"
|
||||
|
||||
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "Local bus NAND Flash- 8-bit small page ROM"
|
||||
|
||||
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
|
||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
||||
bool "Local bus NAND Flash- 8-bit large page ROM"
|
||||
|
||||
endchoice
|
||||
|
||||
if MPC83XX_TSEC1_SUPPORT
|
||||
|
||||
choice
|
||||
prompt "TSEC1 mode"
|
||||
|
||||
config TSEC1_MODE_MII
|
||||
depends on !ARCH_MPC8349
|
||||
bool "MII"
|
||||
|
||||
config TSEC1_MODE_RMII
|
||||
depends on ARCH_MPC831X && !ARCH_MPC8349
|
||||
bool "RMII"
|
||||
|
||||
config TSEC1_MODE_RGMII
|
||||
bool "RGMII"
|
||||
|
||||
config TSEC1_MODE_RTBI
|
||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||
bool "RTBI"
|
||||
|
||||
config TSEC1_MODE_GMII
|
||||
depends on ARCH_MPC8349
|
||||
bool "GMII"
|
||||
|
||||
config TSEC1_MODE_TBI
|
||||
depends on ARCH_MPC8349
|
||||
bool "TBI"
|
||||
|
||||
config TSEC1_MODE_SGMII
|
||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||
bool "SGMII"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if MPC83XX_TSEC2_SUPPORT
|
||||
|
||||
choice
|
||||
prompt "TSEC2 mode"
|
||||
|
||||
config TSEC2_MODE_MII
|
||||
depends on !ARCH_MPC8349
|
||||
bool "MII"
|
||||
|
||||
config TSEC2_MODE_RMII
|
||||
depends on ARCH_MPC831X && !ARCH_MPC8349
|
||||
bool "RMII"
|
||||
|
||||
config TSEC2_MODE_RGMII
|
||||
bool "RGMII"
|
||||
|
||||
config TSEC2_MODE_RTBI
|
||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||
bool "RTBI"
|
||||
|
||||
config TSEC2_MODE_GMII
|
||||
depends on ARCH_MPC8349
|
||||
bool "GMII"
|
||||
|
||||
config TSEC2_MODE_TBI
|
||||
depends on ARCH_MPC8349
|
||||
bool "TBI"
|
||||
|
||||
config TSEC2_MODE_SGMII
|
||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||
bool "SGMII"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
choice
|
||||
prompt "True litle-endian mode"
|
||||
|
||||
config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
|
||||
bool "Big-endian"
|
||||
|
||||
config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
|
||||
bool "Little-endian"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Secondary DDR IO"
|
||||
|
||||
config SECONDARY_DDR_IO_DISABLE
|
||||
bool "Disable"
|
||||
|
||||
config SECONDARY_DDR_IO_ENABLE
|
||||
bool "Enable"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "LALE timing"
|
||||
|
||||
config LALE_TIMING_NORMAL
|
||||
bool "Normal"
|
||||
|
||||
config LALE_TIMING_EARLIER
|
||||
bool "Earlier"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if MPC83XX_LDP_PIN
|
||||
|
||||
choice
|
||||
prompt "LDP pin mux state"
|
||||
|
||||
config LDP_PIN_MUX_STATE_1
|
||||
bool "Inital value 1"
|
||||
|
||||
config LDP_PIN_MUX_STATE_0
|
||||
bool "Inital value 0"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
config LBMC_CLOCK_MODE
|
||||
int
|
||||
default 0 if LBMC_CLOCK_MODE_1_1
|
||||
default 1 if LBMC_CLOCK_MODE_1_2
|
||||
|
||||
config DDR_MC_CLOCK_MODE
|
||||
int
|
||||
default 1 if DDR_MC_CLOCK_MODE_1_2
|
||||
default 0 if DDR_MC_CLOCK_MODE_1_1
|
||||
|
||||
config SYSTEM_PLL_VCO_DIV
|
||||
int
|
||||
default 0 if ARCH_MPC8349 || ARCH_MPC832X
|
||||
default 2 if ARCH_MPC8313
|
||||
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
|
||||
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
|
||||
default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
|
||||
default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
|
||||
default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
|
||||
default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
|
||||
default 3 if SYSTEM_PLL_VCO_DIV_1
|
||||
|
||||
config SYSTEM_PLL_FACTOR
|
||||
int
|
||||
default 2 if SYSTEM_PLL_FACTOR_2_1
|
||||
default 3 if SYSTEM_PLL_FACTOR_3_1
|
||||
default 4 if SYSTEM_PLL_FACTOR_4_1
|
||||
default 5 if SYSTEM_PLL_FACTOR_5_1
|
||||
default 6 if SYSTEM_PLL_FACTOR_6_1
|
||||
default 7 if SYSTEM_PLL_FACTOR_7_1
|
||||
default 8 if SYSTEM_PLL_FACTOR_8_1
|
||||
default 9 if SYSTEM_PLL_FACTOR_9_1
|
||||
default 10 if SYSTEM_PLL_FACTOR_10_1
|
||||
default 11 if SYSTEM_PLL_FACTOR_11_1
|
||||
default 12 if SYSTEM_PLL_FACTOR_12_1
|
||||
default 13 if SYSTEM_PLL_FACTOR_13_1
|
||||
default 14 if SYSTEM_PLL_FACTOR_14_1
|
||||
default 15 if SYSTEM_PLL_FACTOR_15_1
|
||||
default 0 if SYSTEM_PLL_FACTOR_16_1
|
||||
|
||||
config CORE_PLL_RATIO
|
||||
hex
|
||||
default 0x0 if CORE_PLL_BYPASS
|
||||
default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
|
||||
default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
|
||||
default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
|
||||
default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
|
||||
default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
|
||||
default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
|
||||
default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
|
||||
default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
|
||||
default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
|
||||
default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
|
||||
default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
|
||||
default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
|
||||
default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
|
||||
default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
|
||||
default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
|
||||
|
||||
config CORE_DISABLE_MODE
|
||||
int
|
||||
default 0 if CORE_DISABLE_MODE_OFF
|
||||
default 1 if CORE_DISABLE_MODE_ON
|
||||
|
||||
config BOOT_MEMORY_SPACE
|
||||
int
|
||||
default 0 if BOOT_MEMORY_SPACE_LOW
|
||||
default 1 if BOOT_MEMORY_SPACE_HIGH
|
||||
|
||||
config BOOT_SEQUENCER
|
||||
int
|
||||
default 0 if BOOT_SEQUENCER_DISABLED
|
||||
default 1 if BOOT_SEQUENCER_NORMAL_I2C
|
||||
default 2 if BOOT_SEQUENCER_EXTENDED_I2C
|
||||
|
||||
config SOFTWARE_WATCHDOG
|
||||
int
|
||||
default 0 if SOFTWARE_WATCHDOG_DISABLED
|
||||
default 1 if SOFTWARE_WATCHDOG_ENABLED
|
||||
|
||||
config BOOT_ROM_INTERFACE
|
||||
hex
|
||||
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
|
||||
default 0x4 if BOOT_ROM_INTERFACE_PCI1
|
||||
default 0x8 if BOOT_ROM_INTERFACE_PCI2
|
||||
default 0x8 if BOOT_ROM_INTERFACE_ESDHC
|
||||
default 0xc if BOOT_ROM_INTERFACE_SPI
|
||||
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
||||
default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
|
||||
default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
|
||||
default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
|
||||
default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
|
||||
default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
|
||||
|
||||
config TSEC1_MODE
|
||||
hex
|
||||
default 0x0 if !MPC83XX_TSEC1_SUPPORT
|
||||
default 0x0 if TSEC1_MODE_MII
|
||||
default 0x1 if TSEC1_MODE_RMII
|
||||
default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
|
||||
default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
|
||||
default 0x6 if TSEC1_MODE_SGMII
|
||||
default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
|
||||
default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
|
||||
default 0x2 if TSEC1_MODE_GMII
|
||||
default 0x3 if TSEC1_MODE_TBI
|
||||
|
||||
config TSEC2_MODE
|
||||
hex
|
||||
default 0x0 if !MPC83XX_TSEC2_SUPPORT
|
||||
default 0x0 if TSEC2_MODE_MII
|
||||
default 0x1 if TSEC2_MODE_RMII
|
||||
default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
|
||||
default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
|
||||
default 0x6 if TSEC2_MODE_SGMII
|
||||
default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
|
||||
default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
|
||||
default 0x2 if TSEC2_MODE_GMII
|
||||
default 0x3 if TSEC2_MODE_TBI
|
||||
|
||||
config SECONDARY_DDR_IO
|
||||
int
|
||||
default 0 if !ARCH_MPC8360
|
||||
default 0 if SECONDARY_DDR_IO_DISABLE
|
||||
default 1 if SECONDARY_DDR_IO_ENABLE
|
||||
|
||||
config TRUE_LITTLE_ENDIAN
|
||||
int
|
||||
default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
|
||||
default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
|
||||
|
||||
config LALE_TIMING
|
||||
int
|
||||
default 0 if ARCH_MPC830X || ARCH_MPC837X
|
||||
default 0 if LALE_TIMING_NORMAL
|
||||
default 1 if LALE_TIMING_EARLIER
|
||||
|
||||
config LDP_PIN_MUX_STATE
|
||||
int
|
||||
default 0 if !MPC83XX_LDP_PIN
|
||||
default 0 if LDP_PIN_MUX_STATE_1
|
||||
default 1 if LDP_PIN_MUX_STATE_0
|
||||
|
||||
config QUICC_VCO_DIVIDER
|
||||
int
|
||||
default 0 if !MPC83XX_QUICC_ENGINE
|
||||
default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
|
||||
default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
|
||||
default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
|
||||
default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
|
||||
default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
|
||||
default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
|
||||
|
||||
config QUICC_DIV_FACTOR
|
||||
int
|
||||
default 0 if !MPC83XX_QUICC_ENGINE
|
||||
default 0 if QUICC_DIV_FACTOR_1
|
||||
default 1 if QUICC_DIV_FACTOR_2
|
||||
|
||||
config QUICC_MULT_FACTOR
|
||||
int
|
||||
default 0 if !MPC83XX_QUICC_ENGINE
|
||||
default 2 if QUICC_MULT_FACTOR_2
|
||||
default 3 if QUICC_MULT_FACTOR_3
|
||||
default 4 if QUICC_MULT_FACTOR_4
|
||||
default 5 if QUICC_MULT_FACTOR_5
|
||||
default 6 if QUICC_MULT_FACTOR_6
|
||||
default 7 if QUICC_MULT_FACTOR_7
|
||||
default 8 if QUICC_MULT_FACTOR_8
|
||||
default 9 if QUICC_MULT_FACTOR_9
|
||||
default 10 if QUICC_MULT_FACTOR_10
|
||||
default 11 if QUICC_MULT_FACTOR_11
|
||||
default 12 if QUICC_MULT_FACTOR_12
|
||||
default 13 if QUICC_MULT_FACTOR_13
|
||||
default 14 if QUICC_MULT_FACTOR_14
|
||||
default 15 if QUICC_MULT_FACTOR_15
|
||||
default 16 if QUICC_MULT_FACTOR_16
|
||||
default 17 if QUICC_MULT_FACTOR_17
|
||||
default 18 if QUICC_MULT_FACTOR_18
|
||||
default 19 if QUICC_MULT_FACTOR_19
|
||||
default 20 if QUICC_MULT_FACTOR_20
|
||||
default 21 if QUICC_MULT_FACTOR_21
|
||||
default 22 if QUICC_MULT_FACTOR_22
|
||||
default 23 if QUICC_MULT_FACTOR_23
|
||||
default 24 if QUICC_MULT_FACTOR_24
|
||||
default 25 if QUICC_MULT_FACTOR_25
|
||||
default 26 if QUICC_MULT_FACTOR_26
|
||||
default 27 if QUICC_MULT_FACTOR_27
|
||||
default 28 if QUICC_MULT_FACTOR_28
|
||||
default 29 if QUICC_MULT_FACTOR_29
|
||||
default 30 if QUICC_MULT_FACTOR_30
|
||||
default 31 if QUICC_MULT_FACTOR_31
|
||||
|
||||
config PCI_HOST_MODE
|
||||
int
|
||||
default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
|
||||
default 0 if PCI_HOST_MODE_DISABLE
|
||||
default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
|
||||
|
||||
config PCI_64BIT_MODE
|
||||
int
|
||||
default 0 if !ARCH_MPC8349
|
||||
default 0 if PCI_64BIT_MODE_DISABLE
|
||||
default 1 if PCI_64BIT_MODE_ENABLE
|
||||
|
||||
config PCI_INT_ARBITER1
|
||||
int
|
||||
default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
|
||||
default 0 if PCI_INT_ARBITER1_DISABLE
|
||||
default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
|
||||
|
||||
config PCI_INT_ARBITER2
|
||||
int
|
||||
default 0 if !ARCH_MPC8349
|
||||
default 0 if PCI_INT_ARBITER2_DISABLE
|
||||
default 1 if PCI_INT_ARBITER2_ENABLE
|
||||
|
||||
config PCI_CLOCK_OUTPUT_DRIVE
|
||||
int
|
||||
default 0 if !ARCH_MPC8360
|
||||
default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
|
||||
default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE
|
||||
37
arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
Normal file
37
arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
Normal file
@ -0,0 +1,37 @@
|
||||
#ifdef CONFIG_ARCH_MPC8349
|
||||
#define TSEC1_MODE_SHIFT 17
|
||||
#define TSEC2_MODE_SHIFT 19
|
||||
#else
|
||||
#define TSEC1_MODE_SHIFT 18
|
||||
#define TSEC2_MODE_SHIFT 21
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
|
||||
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
|
||||
(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
|
||||
(CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
|
||||
(CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
|
||||
(CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
|
||||
(CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
|
||||
(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
|
||||
)
|
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
|
||||
(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
|
||||
(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
|
||||
(CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
|
||||
(CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
|
||||
(CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
|
||||
(CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
|
||||
(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
|
||||
(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
|
||||
(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
|
||||
(CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
|
||||
(CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
|
||||
(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
|
||||
(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
|
||||
(CONFIG_LALE_TIMING << (31 - 29)) |\
|
||||
(CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
|
||||
)
|
||||
6
arch/powerpc/cpu/mpc83xx/initreg/Kconfig
Normal file
6
arch/powerpc/cpu/mpc83xx/initreg/Kconfig
Normal file
@ -0,0 +1,6 @@
|
||||
menu "Initial register configuration"
|
||||
|
||||
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
|
||||
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
|
||||
|
||||
endmenu
|
||||
139
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
Normal file
139
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
Normal file
@ -0,0 +1,139 @@
|
||||
menu "LCRR - Clock Ratio Register register"
|
||||
|
||||
if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
|
||||
|
||||
choice
|
||||
prompt "DLL bypass"
|
||||
|
||||
config LCRR_DBYP_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config LCRR_DBYP_PLL_ENABLED
|
||||
bool "PLL enabled"
|
||||
|
||||
config LCRR_DBYP_PLL_BYPASSED
|
||||
bool "PLL bypassed"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if ARCH_MPC834X || ARCH_MPC8360
|
||||
|
||||
choice
|
||||
prompt "Additional delay cycles for SDRAM control signals"
|
||||
|
||||
config LCRR_BUFCMDC_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config LCRR_BUFCMDC_4
|
||||
bool "4"
|
||||
|
||||
config LCRR_BUFCMDC_1
|
||||
bool "1"
|
||||
|
||||
config LCRR_BUFCMDC_2
|
||||
bool "2"
|
||||
|
||||
config LCRR_BUFCMDC_3
|
||||
bool "3"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Extended CAS latency"
|
||||
|
||||
config LCRR_ECL_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config LCRR_ECL_4
|
||||
bool "4"
|
||||
|
||||
config LCRR_ECL_5
|
||||
bool "5"
|
||||
|
||||
config LCRR_ECL_6
|
||||
bool "6"
|
||||
|
||||
config LCRR_ECL_7
|
||||
bool "7"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # ARCH_MPC834X || ARCH_MPC8360
|
||||
|
||||
if !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "External address delay cycles"
|
||||
|
||||
config LCRR_EADC_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config LCRR_EADC_4
|
||||
bool "4"
|
||||
|
||||
config LCRR_EADC_1
|
||||
bool "1"
|
||||
|
||||
config LCRR_EADC_2
|
||||
bool "2"
|
||||
|
||||
config LCRR_EADC_3
|
||||
bool "3"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # !ARCH_MPC8308
|
||||
|
||||
choice
|
||||
prompt "System clock divider"
|
||||
|
||||
config LCRR_CLKDIV_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config LCRR_CLKDIV_2
|
||||
bool "2"
|
||||
|
||||
config LCRR_CLKDIV_4
|
||||
bool "4"
|
||||
|
||||
config LCRR_CLKDIV_8
|
||||
bool "8"
|
||||
|
||||
endchoice
|
||||
|
||||
config LCRR_DBYP
|
||||
hex
|
||||
default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
|
||||
default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
|
||||
|
||||
config LCRR_BUFCMDC
|
||||
hex
|
||||
default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
|
||||
default 0x10000000 if LCRR_BUFCMDC_1
|
||||
default 0x20000000 if LCRR_BUFCMDC_2
|
||||
default 0x30000000 if LCRR_BUFCMDC_3
|
||||
|
||||
config LCRR_ECL
|
||||
hex
|
||||
default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
|
||||
default 0x1000000 if LCRR_ECL_5
|
||||
default 0x2000000 if LCRR_ECL_6
|
||||
default 0x3000000 if LCRR_ECL_7
|
||||
|
||||
config LCRR_EADC
|
||||
hex
|
||||
default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
|
||||
default 0x10000 if LCRR_EADC_1
|
||||
default 0x20000 if LCRR_EADC_2
|
||||
default 0x30000 if LCRR_EADC_3
|
||||
|
||||
config LCRR_CLKDIV
|
||||
hex
|
||||
default 0x0 if LCRR_CLKDIV_UNSET
|
||||
default 0x2 if LCRR_CLKDIV_2
|
||||
default 0x4 if LCRR_CLKDIV_4
|
||||
default 0x8 if LCRR_CLKDIV_8
|
||||
|
||||
endmenu
|
||||
115
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
Normal file
115
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
Normal file
@ -0,0 +1,115 @@
|
||||
menu "SPCR - System priority and configuration register"
|
||||
|
||||
choice
|
||||
prompt "Optimize"
|
||||
|
||||
config SPCR_OPT_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config SPCR_OPT_NONE
|
||||
bool "No performance enhancement"
|
||||
|
||||
config SPCR_OPT_SPEC_READ
|
||||
bool "Performance enhancement by speculative read"
|
||||
|
||||
endchoice
|
||||
|
||||
if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
|
||||
|
||||
choice
|
||||
prompt "TSEC emergency priority"
|
||||
|
||||
config SPCR_TSECEP_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config SPCR_TSECEP_0
|
||||
bool "Level 0 (lowest priority)"
|
||||
|
||||
config SPCR_TSECEP_1
|
||||
bool "Level 1"
|
||||
|
||||
config SPCR_TSECEP_2
|
||||
bool "Level 2"
|
||||
|
||||
config SPCR_TSECEP_3
|
||||
bool "Level 3 (highest priority)"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
if ARCH_MPC8349
|
||||
|
||||
choice
|
||||
prompt "TSEC1 emergency priority"
|
||||
|
||||
config SPCR_TSEC1EP_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config SPCR_TSEC1EP_0
|
||||
bool "Level 0 (lowest priority)"
|
||||
|
||||
config SPCR_TSEC1EP_1
|
||||
bool "Level 1"
|
||||
|
||||
config SPCR_TSEC1EP_2
|
||||
bool "Level 2"
|
||||
|
||||
config SPCR_TSEC1EP_3
|
||||
bool "Level 3 (highest priority)"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "TSEC2 emergency priority"
|
||||
|
||||
config SPCR_TSEC2EP_UNSET
|
||||
bool "Don't set value"
|
||||
|
||||
config SPCR_TSEC2EP_0
|
||||
bool "Level 0 (lowest priority)"
|
||||
|
||||
config SPCR_TSEC2EP_1
|
||||
bool "Level 1"
|
||||
|
||||
config SPCR_TSEC2EP_2
|
||||
bool "Level 2"
|
||||
|
||||
config SPCR_TSEC2EP_3
|
||||
bool "Level 3 (highest priority)"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
config SPCR_OPT
|
||||
hex
|
||||
default 0x0 if SPCR_OPT_UNSET
|
||||
default 0x0 if SPCR_OPT_NONE
|
||||
default 0x800000 if SPCR_OPT_SPEC_READ
|
||||
|
||||
config SPCR_TSECEP
|
||||
hex
|
||||
default 0x0 if SPCR_TSECEP_UNSET
|
||||
default 0x0 if SPCR_TSECEP_0
|
||||
default 0x100 if SPCR_TSECEP_1
|
||||
default 0x200 if SPCR_TSECEP_2
|
||||
default 0x300 if SPCR_TSECEP_3
|
||||
|
||||
config SPCR_TSEC1EP
|
||||
hex
|
||||
default 0x0 if SPCR_TSEC1EP_UNSET
|
||||
default 0x0 if SPCR_TSEC1EP_0
|
||||
default 0x100 if SPCR_TSEC1EP_1
|
||||
default 0x200 if SPCR_TSEC1EP_2
|
||||
default 0x300 if SPCR_TSEC1EP_3
|
||||
|
||||
config SPCR_TSEC2EP
|
||||
hex
|
||||
default 0x0 if SPCR_TSEC2EP_UNSET
|
||||
default 0x0 if SPCR_TSEC2EP_0
|
||||
default 0x1 if SPCR_TSEC2EP_1
|
||||
default 0x2 if SPCR_TSEC2EP_2
|
||||
default 0x3 if SPCR_TSEC2EP_3
|
||||
|
||||
endmenu
|
||||
79
arch/powerpc/cpu/mpc83xx/initreg/initreg.h
Normal file
79
arch/powerpc/cpu/mpc83xx/initreg/initreg.h
Normal file
@ -0,0 +1,79 @@
|
||||
#define SPCR_PCIHPE_MASK 0x10000000
|
||||
#define SPCR_PCIPR_MASK 0x03000000
|
||||
#define SPCR_OPT_MASK 0x00800000
|
||||
#define SPCR_TBEN_MASK 0x00400000
|
||||
#define SPCR_COREPR_MASK 0x00300000
|
||||
#define SPCR_TSEC1DP_MASK 0x00003000
|
||||
#define SPCR_TSEC1BDP_MASK 0x00000C00
|
||||
#define SPCR_TSEC1EP_MASK 0x00000300
|
||||
#define SPCR_TSEC2DP_MASK 0x00000030
|
||||
#define SPCR_TSEC2BDP_MASK 0x0000000C
|
||||
#define SPCR_TSEC2EP_MASK 0x00000003
|
||||
#define SPCR_TSECDP_MASK 0x00003000
|
||||
#define SPCR_TSECBDP_MASK 0x00000C00
|
||||
#define SPCR_TSECEP_MASK 0x00000300
|
||||
|
||||
const __be32 spcr_mask =
|
||||
#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
|
||||
SPCR_OPT_MASK |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
|
||||
SPCR_TSECEP_MASK |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
|
||||
SPCR_TSEC1EP_MASK |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
|
||||
SPCR_TSEC2EP_MASK |
|
||||
#endif
|
||||
0;
|
||||
const __be32 spcr_val =
|
||||
#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
|
||||
CONFIG_SPCR_OPT |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
|
||||
CONFIG_SPCR_TSECEP |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
|
||||
CONFIG_SPCR_TSEC1EP |
|
||||
#endif
|
||||
#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
|
||||
CONFIG_SPCR_TSEC2EP |
|
||||
#endif
|
||||
0;
|
||||
|
||||
const __be32 lcrr_mask =
|
||||
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
|
||||
LCRR_DBYP |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
|
||||
LCRR_BUFCMDC |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
|
||||
LCRR_ECL |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
|
||||
LCRR_EADC |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
|
||||
LCRR_CLKDIV |
|
||||
#endif
|
||||
0;
|
||||
|
||||
const __be32 lcrr_val =
|
||||
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
|
||||
CONFIG_LCRR_DBYP |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
|
||||
CONFIG_LCRR_BUFCMDC |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
|
||||
CONFIG_LCRR_ECL |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
|
||||
CONFIG_LCRR_EADC |
|
||||
#endif
|
||||
#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
|
||||
CONFIG_LCRR_CLKDIV |
|
||||
#endif
|
||||
0;
|
||||
519
arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
Normal file
519
arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
Normal file
@ -0,0 +1,519 @@
|
||||
menu "LBLAW setup"
|
||||
|
||||
choice
|
||||
prompt "NAND LAWBAR for NAND SPL"
|
||||
|
||||
config NAND_LBLAWBAR_PRELIM_NONE
|
||||
bool "None"
|
||||
|
||||
config NAND_LBLAWBAR_PRELIM_0
|
||||
bool "0"
|
||||
depends on LBLAW0
|
||||
|
||||
config NAND_LBLAWBAR_PRELIM_1
|
||||
bool "1"
|
||||
depends on LBLAW1
|
||||
|
||||
config NAND_LBLAWBAR_PRELIM_2
|
||||
bool "2"
|
||||
depends on LBLAW2
|
||||
|
||||
config NAND_LBLAWBAR_PRELIM_3
|
||||
bool "3"
|
||||
depends on LBLAW3
|
||||
|
||||
endchoice
|
||||
|
||||
menuconfig LBLAW0
|
||||
bool "LBLAW0"
|
||||
|
||||
if LBLAW0
|
||||
|
||||
config LBLAW0_ENABLE
|
||||
bool "Window enable"
|
||||
default "y"
|
||||
|
||||
if !LBLAW0_ENABLE
|
||||
|
||||
config LBLAW0_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
endif
|
||||
|
||||
if LBLAW0_ENABLE
|
||||
|
||||
config LBLAW0_NAME
|
||||
string "Identifier"
|
||||
|
||||
config LBLAW0_BASE
|
||||
hex "Window base"
|
||||
|
||||
choice
|
||||
prompt "Window size"
|
||||
|
||||
config LBLAW0_LENGTH_4_KBYTES
|
||||
bool "4 kb"
|
||||
|
||||
config LBLAW0_LENGTH_8_KBYTES
|
||||
bool "8 kb"
|
||||
|
||||
config LBLAW0_LENGTH_16_KBYTES
|
||||
bool "16 kb"
|
||||
|
||||
config LBLAW0_LENGTH_32_KBYTES
|
||||
bool "32 kb"
|
||||
|
||||
config LBLAW0_LENGTH_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config LBLAW0_LENGTH_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config LBLAW0_LENGTH_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config LBLAW0_LENGTH_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config LBLAW0_LENGTH_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config LBLAW0_LENGTH_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config LBLAW0_LENGTH_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config LBLAW0_LENGTH_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config LBLAW0_LENGTH_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config LBLAW0_LENGTH_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config LBLAW0_LENGTH_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
config LBLAW0_LENGTH_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
config LBLAW0_LENGTH_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config LBLAW0_LENGTH_512_MBYTES
|
||||
bool "512 mb"
|
||||
|
||||
config LBLAW0_LENGTH_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config LBLAW0_LENGTH_2_GBYTES
|
||||
bool "2 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # LBLAW0_ENABLE
|
||||
|
||||
endif # LBLAW0
|
||||
|
||||
config LBLAW0_ENABLE_BIT
|
||||
hex
|
||||
default 0x0 if !LBLAW0_ENABLE
|
||||
default 0x80000000 if LBLAW0_ENABLE
|
||||
|
||||
config LBLAW0_LENGTH
|
||||
hex
|
||||
default 0x0 if !LBLAW0_ENABLE
|
||||
default 0x0000000B if LBLAW0_LENGTH_4_KBYTES
|
||||
default 0x0000000C if LBLAW0_LENGTH_8_KBYTES
|
||||
default 0x0000000D if LBLAW0_LENGTH_16_KBYTES
|
||||
default 0x0000000E if LBLAW0_LENGTH_32_KBYTES
|
||||
default 0x0000000F if LBLAW0_LENGTH_64_KBYTES
|
||||
default 0x00000010 if LBLAW0_LENGTH_128_KBYTES
|
||||
default 0x00000011 if LBLAW0_LENGTH_256_KBYTES
|
||||
default 0x00000012 if LBLAW0_LENGTH_512_KBYTES
|
||||
default 0x00000013 if LBLAW0_LENGTH_1_MBYTES
|
||||
default 0x00000014 if LBLAW0_LENGTH_2_MBYTES
|
||||
default 0x00000015 if LBLAW0_LENGTH_4_MBYTES
|
||||
default 0x00000016 if LBLAW0_LENGTH_8_MBYTES
|
||||
default 0x00000017 if LBLAW0_LENGTH_16_MBYTES
|
||||
default 0x00000018 if LBLAW0_LENGTH_32_MBYTES
|
||||
default 0x00000019 if LBLAW0_LENGTH_64_MBYTES
|
||||
default 0x0000001A if LBLAW0_LENGTH_128_MBYTES
|
||||
default 0x0000001B if LBLAW0_LENGTH_256_MBYTES
|
||||
default 0x0000001C if LBLAW0_LENGTH_512_MBYTES
|
||||
default 0x0000001D if LBLAW0_LENGTH_1_GBYTES
|
||||
default 0x0000001E if LBLAW0_LENGTH_2_GBYTES
|
||||
|
||||
menuconfig LBLAW1
|
||||
bool "LBLAW1"
|
||||
|
||||
if LBLAW1
|
||||
|
||||
config LBLAW1_ENABLE
|
||||
bool "Window enable"
|
||||
default "y"
|
||||
|
||||
if !LBLAW1_ENABLE
|
||||
|
||||
config LBLAW1_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
endif
|
||||
|
||||
if LBLAW1_ENABLE
|
||||
|
||||
config LBLAW1_NAME
|
||||
string "Identifier"
|
||||
|
||||
config LBLAW1_BASE
|
||||
hex "Window base"
|
||||
|
||||
choice
|
||||
prompt "Window size"
|
||||
|
||||
config LBLAW1_LENGTH_4_KBYTES
|
||||
bool "4 kb"
|
||||
|
||||
config LBLAW1_LENGTH_8_KBYTES
|
||||
bool "8 kb"
|
||||
|
||||
config LBLAW1_LENGTH_16_KBYTES
|
||||
bool "16 kb"
|
||||
|
||||
config LBLAW1_LENGTH_32_KBYTES
|
||||
bool "32 kb"
|
||||
|
||||
config LBLAW1_LENGTH_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config LBLAW1_LENGTH_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config LBLAW1_LENGTH_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config LBLAW1_LENGTH_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config LBLAW1_LENGTH_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config LBLAW1_LENGTH_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config LBLAW1_LENGTH_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config LBLAW1_LENGTH_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config LBLAW1_LENGTH_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config LBLAW1_LENGTH_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config LBLAW1_LENGTH_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
config LBLAW1_LENGTH_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
config LBLAW1_LENGTH_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config LBLAW1_LENGTH_512_MBYTES
|
||||
bool "512 mb"
|
||||
|
||||
config LBLAW1_LENGTH_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config LBLAW1_LENGTH_2_GBYTES
|
||||
bool "2 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # LBLAW1_ENABLE
|
||||
|
||||
endif # LBLAW1
|
||||
|
||||
config LBLAW1_ENABLE_BIT
|
||||
hex
|
||||
default 0x0 if !LBLAW1_ENABLE
|
||||
default 0x80000000 if LBLAW1_ENABLE
|
||||
|
||||
config LBLAW1_LENGTH
|
||||
hex
|
||||
default 0x0 if !LBLAW1_ENABLE
|
||||
default 0x0000000B if LBLAW1_LENGTH_4_KBYTES
|
||||
default 0x0000000C if LBLAW1_LENGTH_8_KBYTES
|
||||
default 0x0000000D if LBLAW1_LENGTH_16_KBYTES
|
||||
default 0x0000000E if LBLAW1_LENGTH_32_KBYTES
|
||||
default 0x0000000F if LBLAW1_LENGTH_64_KBYTES
|
||||
default 0x00000010 if LBLAW1_LENGTH_128_KBYTES
|
||||
default 0x00000011 if LBLAW1_LENGTH_256_KBYTES
|
||||
default 0x00000012 if LBLAW1_LENGTH_512_KBYTES
|
||||
default 0x00000013 if LBLAW1_LENGTH_1_MBYTES
|
||||
default 0x00000014 if LBLAW1_LENGTH_2_MBYTES
|
||||
default 0x00000015 if LBLAW1_LENGTH_4_MBYTES
|
||||
default 0x00000016 if LBLAW1_LENGTH_8_MBYTES
|
||||
default 0x00000017 if LBLAW1_LENGTH_16_MBYTES
|
||||
default 0x00000018 if LBLAW1_LENGTH_32_MBYTES
|
||||
default 0x00000019 if LBLAW1_LENGTH_64_MBYTES
|
||||
default 0x0000001A if LBLAW1_LENGTH_128_MBYTES
|
||||
default 0x0000001B if LBLAW1_LENGTH_256_MBYTES
|
||||
default 0x0000001C if LBLAW1_LENGTH_512_MBYTES
|
||||
default 0x0000001D if LBLAW1_LENGTH_1_GBYTES
|
||||
default 0x0000001E if LBLAW1_LENGTH_2_GBYTES
|
||||
|
||||
menuconfig LBLAW2
|
||||
bool "LBLAW2"
|
||||
|
||||
if LBLAW2
|
||||
|
||||
config LBLAW2_ENABLE
|
||||
bool "Window enable"
|
||||
default "y"
|
||||
|
||||
if !LBLAW2_ENABLE
|
||||
|
||||
config LBLAW2_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
endif
|
||||
|
||||
if LBLAW2_ENABLE
|
||||
|
||||
config LBLAW2_NAME
|
||||
string "Identifier"
|
||||
|
||||
config LBLAW2_BASE
|
||||
hex "Window base"
|
||||
|
||||
choice
|
||||
prompt "Window size"
|
||||
|
||||
config LBLAW2_LENGTH_4_KBYTES
|
||||
bool "4 kb"
|
||||
|
||||
config LBLAW2_LENGTH_8_KBYTES
|
||||
bool "8 kb"
|
||||
|
||||
config LBLAW2_LENGTH_16_KBYTES
|
||||
bool "16 kb"
|
||||
|
||||
config LBLAW2_LENGTH_32_KBYTES
|
||||
bool "32 kb"
|
||||
|
||||
config LBLAW2_LENGTH_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config LBLAW2_LENGTH_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config LBLAW2_LENGTH_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config LBLAW2_LENGTH_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config LBLAW2_LENGTH_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config LBLAW2_LENGTH_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config LBLAW2_LENGTH_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config LBLAW2_LENGTH_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config LBLAW2_LENGTH_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config LBLAW2_LENGTH_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config LBLAW2_LENGTH_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
config LBLAW2_LENGTH_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
config LBLAW2_LENGTH_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config LBLAW2_LENGTH_512_MBYTES
|
||||
bool "512 mb"
|
||||
|
||||
config LBLAW2_LENGTH_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config LBLAW2_LENGTH_2_GBYTES
|
||||
bool "2 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # LBLAW2_ENABLE
|
||||
|
||||
endif # LBLAW2
|
||||
|
||||
config LBLAW2_ENABLE_BIT
|
||||
hex
|
||||
default 0x0 if !LBLAW2_ENABLE
|
||||
default 0x80000000 if LBLAW2_ENABLE
|
||||
|
||||
config LBLAW2_LENGTH
|
||||
hex
|
||||
default 0x0 if !LBLAW2_ENABLE
|
||||
default 0x0000000B if LBLAW2_LENGTH_4_KBYTES
|
||||
default 0x0000000C if LBLAW2_LENGTH_8_KBYTES
|
||||
default 0x0000000D if LBLAW2_LENGTH_16_KBYTES
|
||||
default 0x0000000E if LBLAW2_LENGTH_32_KBYTES
|
||||
default 0x0000000F if LBLAW2_LENGTH_64_KBYTES
|
||||
default 0x00000010 if LBLAW2_LENGTH_128_KBYTES
|
||||
default 0x00000011 if LBLAW2_LENGTH_256_KBYTES
|
||||
default 0x00000012 if LBLAW2_LENGTH_512_KBYTES
|
||||
default 0x00000013 if LBLAW2_LENGTH_1_MBYTES
|
||||
default 0x00000014 if LBLAW2_LENGTH_2_MBYTES
|
||||
default 0x00000015 if LBLAW2_LENGTH_4_MBYTES
|
||||
default 0x00000016 if LBLAW2_LENGTH_8_MBYTES
|
||||
default 0x00000017 if LBLAW2_LENGTH_16_MBYTES
|
||||
default 0x00000018 if LBLAW2_LENGTH_32_MBYTES
|
||||
default 0x00000019 if LBLAW2_LENGTH_64_MBYTES
|
||||
default 0x0000001A if LBLAW2_LENGTH_128_MBYTES
|
||||
default 0x0000001B if LBLAW2_LENGTH_256_MBYTES
|
||||
default 0x0000001C if LBLAW2_LENGTH_512_MBYTES
|
||||
default 0x0000001D if LBLAW2_LENGTH_1_GBYTES
|
||||
default 0x0000001E if LBLAW2_LENGTH_2_GBYTES
|
||||
|
||||
menuconfig LBLAW3
|
||||
bool "LBLAW3"
|
||||
|
||||
if LBLAW3
|
||||
|
||||
config LBLAW3_ENABLE
|
||||
bool "Window enable"
|
||||
default "y"
|
||||
|
||||
if !LBLAW3_ENABLE
|
||||
|
||||
config LBLAW3_BASE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
endif
|
||||
|
||||
if LBLAW3_ENABLE
|
||||
|
||||
config LBLAW3_NAME
|
||||
string "Identifier"
|
||||
|
||||
config LBLAW3_BASE
|
||||
hex "Window base"
|
||||
|
||||
choice
|
||||
prompt "Window size"
|
||||
|
||||
config LBLAW3_LENGTH_4_KBYTES
|
||||
bool "4 kb"
|
||||
|
||||
config LBLAW3_LENGTH_8_KBYTES
|
||||
bool "8 kb"
|
||||
|
||||
config LBLAW3_LENGTH_16_KBYTES
|
||||
bool "16 kb"
|
||||
|
||||
config LBLAW3_LENGTH_32_KBYTES
|
||||
bool "32 kb"
|
||||
|
||||
config LBLAW3_LENGTH_64_KBYTES
|
||||
bool "64 kb"
|
||||
|
||||
config LBLAW3_LENGTH_128_KBYTES
|
||||
bool "128 kb"
|
||||
|
||||
config LBLAW3_LENGTH_256_KBYTES
|
||||
bool "256 kb"
|
||||
|
||||
config LBLAW3_LENGTH_512_KBYTES
|
||||
bool "512 kb"
|
||||
|
||||
config LBLAW3_LENGTH_1_MBYTES
|
||||
bool "1 mb"
|
||||
|
||||
config LBLAW3_LENGTH_2_MBYTES
|
||||
bool "2 mb"
|
||||
|
||||
config LBLAW3_LENGTH_4_MBYTES
|
||||
bool "4 mb"
|
||||
|
||||
config LBLAW3_LENGTH_8_MBYTES
|
||||
bool "8 mb"
|
||||
|
||||
config LBLAW3_LENGTH_16_MBYTES
|
||||
bool "16 mb"
|
||||
|
||||
config LBLAW3_LENGTH_32_MBYTES
|
||||
bool "32 mb"
|
||||
|
||||
config LBLAW3_LENGTH_64_MBYTES
|
||||
bool "64 mb"
|
||||
|
||||
config LBLAW3_LENGTH_128_MBYTES
|
||||
bool "128 mb"
|
||||
|
||||
config LBLAW3_LENGTH_256_MBYTES
|
||||
bool "256 mb"
|
||||
|
||||
config LBLAW3_LENGTH_512_MBYTES
|
||||
bool "512 mb"
|
||||
|
||||
config LBLAW3_LENGTH_1_GBYTES
|
||||
bool "1 gb"
|
||||
|
||||
config LBLAW3_LENGTH_2_GBYTES
|
||||
bool "2 gb"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # LBLAW3_ENABLE
|
||||
|
||||
endif # LBLAW3
|
||||
|
||||
config LBLAW3_ENABLE_BIT
|
||||
hex
|
||||
default 0x0 if !LBLAW3_ENABLE
|
||||
default 0x80000000 if LBLAW3_ENABLE
|
||||
|
||||
config LBLAW3_LENGTH
|
||||
hex
|
||||
default 0x0 if !LBLAW3_ENABLE
|
||||
default 0x0000000B if LBLAW3_LENGTH_4_KBYTES
|
||||
default 0x0000000C if LBLAW3_LENGTH_8_KBYTES
|
||||
default 0x0000000D if LBLAW3_LENGTH_16_KBYTES
|
||||
default 0x0000000E if LBLAW3_LENGTH_32_KBYTES
|
||||
default 0x0000000F if LBLAW3_LENGTH_64_KBYTES
|
||||
default 0x00000010 if LBLAW3_LENGTH_128_KBYTES
|
||||
default 0x00000011 if LBLAW3_LENGTH_256_KBYTES
|
||||
default 0x00000012 if LBLAW3_LENGTH_512_KBYTES
|
||||
default 0x00000013 if LBLAW3_LENGTH_1_MBYTES
|
||||
default 0x00000014 if LBLAW3_LENGTH_2_MBYTES
|
||||
default 0x00000015 if LBLAW3_LENGTH_4_MBYTES
|
||||
default 0x00000016 if LBLAW3_LENGTH_8_MBYTES
|
||||
default 0x00000017 if LBLAW3_LENGTH_16_MBYTES
|
||||
default 0x00000018 if LBLAW3_LENGTH_32_MBYTES
|
||||
default 0x00000019 if LBLAW3_LENGTH_64_MBYTES
|
||||
default 0x0000001A if LBLAW3_LENGTH_128_MBYTES
|
||||
default 0x0000001B if LBLAW3_LENGTH_256_MBYTES
|
||||
default 0x0000001C if LBLAW3_LENGTH_512_MBYTES
|
||||
default 0x0000001D if LBLAW3_LENGTH_1_GBYTES
|
||||
default 0x0000001E if LBLAW3_LENGTH_2_GBYTES
|
||||
|
||||
endmenu
|
||||
55
arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
Normal file
55
arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
Normal file
@ -0,0 +1,55 @@
|
||||
#if defined(CONFIG_LBLAW0)
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM \
|
||||
CONFIG_LBLAW0_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (\
|
||||
CONFIG_LBLAW0_ENABLE_BIT |\
|
||||
CONFIG_LBLAW0_LENGTH \
|
||||
)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LBLAW1)
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM \
|
||||
CONFIG_LBLAW1_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (\
|
||||
CONFIG_LBLAW1_ENABLE_BIT |\
|
||||
CONFIG_LBLAW1_LENGTH \
|
||||
)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LBLAW2)
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM \
|
||||
CONFIG_LBLAW2_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (\
|
||||
CONFIG_LBLAW2_ENABLE_BIT |\
|
||||
CONFIG_LBLAW2_LENGTH \
|
||||
)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LBLAW3)
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM \
|
||||
CONFIG_LBLAW3_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (\
|
||||
CONFIG_LBLAW3_ENABLE_BIT |\
|
||||
CONFIG_LBLAW3_LENGTH \
|
||||
)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
|
||||
#endif
|
||||
@ -174,6 +174,41 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
|
||||
|
||||
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
|
||||
|
||||
int get_pcie_clk(int index)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
u32 pci_sync_in;
|
||||
u8 spmf;
|
||||
u8 clkin_div;
|
||||
u32 sccr;
|
||||
u32 csb_clk;
|
||||
u32 testval;
|
||||
|
||||
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
|
||||
sccr = im->clk.sccr;
|
||||
pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
|
||||
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
|
||||
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
|
||||
|
||||
if (index)
|
||||
testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
|
||||
else
|
||||
testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
|
||||
|
||||
switch (testval) {
|
||||
case 0:
|
||||
return 0;
|
||||
case 1:
|
||||
return csb_clk;
|
||||
case 2:
|
||||
return csb_clk / 2;
|
||||
case 3:
|
||||
return csb_clk / 3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
|
||||
{
|
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
||||
@ -269,11 +304,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
|
||||
/* Hose configure header is memory-mapped */
|
||||
hose_cfg_base = (void *)pex;
|
||||
|
||||
get_clocks();
|
||||
/* Configure the PCIE controller core clock ratio */
|
||||
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
|
||||
(((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
|
||||
/ 1000000) * 16) / 333);
|
||||
((get_pcie_clk(bus) / 1000000) * 16) / 333);
|
||||
udelay(1000000);
|
||||
|
||||
/* Do Type 1 bridge configuration */
|
||||
|
||||
@ -31,7 +31,7 @@ void board_add_ram_info(int use_default)
|
||||
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
|
||||
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
|
||||
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
|
||||
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
|
||||
puts(", 16-bit");
|
||||
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
|
||||
@ -281,7 +281,7 @@ long int spd_sdram()
|
||||
/*
|
||||
* Set up LAWBAR for all of DDR.
|
||||
*/
|
||||
ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
|
||||
debug("DDR:bar=0x%08x\n", ecm->bar);
|
||||
debug("DDR:ar=0x%08x\n", ecm->ar);
|
||||
@ -426,7 +426,7 @@ long int spd_sdram()
|
||||
|
||||
/*
|
||||
* Errata DDR6 work around: input enable 2 cycles earlier.
|
||||
* including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
|
||||
* including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
|
||||
*/
|
||||
if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
|
||||
if (caslat == 2)
|
||||
@ -436,7 +436,7 @@ long int spd_sdram()
|
||||
else if (caslat == 4)
|
||||
ddr->debug_reg = 0x202c0000; /* CL=3.0 */
|
||||
|
||||
__asm__ __volatile__ ("sync");
|
||||
sync();
|
||||
|
||||
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
|
||||
}
|
||||
@ -765,7 +765,8 @@ long int spd_sdram()
|
||||
#endif
|
||||
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
|
||||
|
||||
asm("sync;isync");
|
||||
sync();
|
||||
isync();
|
||||
|
||||
udelay(600);
|
||||
|
||||
@ -834,7 +835,8 @@ long int spd_sdram()
|
||||
#endif
|
||||
/* Enable controller, and GO! */
|
||||
ddr->sdram_cfg = sdram_cfg;
|
||||
asm("sync;isync");
|
||||
sync();
|
||||
isync();
|
||||
udelay(500);
|
||||
|
||||
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
|
||||
@ -843,6 +845,22 @@ long int spd_sdram()
|
||||
#endif /* CONFIG_SPD_EEPROM */
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
static inline u32 mftbu(void)
|
||||
{
|
||||
u32 rval;
|
||||
|
||||
asm volatile("mftbu %0" : "=r" (rval));
|
||||
return rval;
|
||||
}
|
||||
|
||||
static inline u32 mftb(void)
|
||||
{
|
||||
u32 rval;
|
||||
|
||||
asm volatile("mftb %0" : "=r" (rval));
|
||||
return rval;
|
||||
}
|
||||
|
||||
/*
|
||||
* Use timebase counter, get_timer() is not available
|
||||
* at this point of initialization yet.
|
||||
@ -858,9 +876,9 @@ static __inline__ unsigned long get_tbms (void)
|
||||
|
||||
/* get the timebase ticks */
|
||||
do {
|
||||
asm volatile ("mftbu %0":"=r" (tbu1):);
|
||||
asm volatile ("mftb %0":"=r" (tbl):);
|
||||
asm volatile ("mftbu %0":"=r" (tbu2):);
|
||||
tbu1 = mftbu();
|
||||
tbl = mftb();
|
||||
tbu2 = mftbu();
|
||||
} while (tbu1 != tbu2);
|
||||
|
||||
/* convert ticks to ms */
|
||||
@ -897,7 +915,7 @@ void ddr_enable_ecc(unsigned int dram_size)
|
||||
for (p = 0; p < (u64*)(size); p++) {
|
||||
ppcDWstore((u32*)p, pattern);
|
||||
}
|
||||
__asm__ __volatile__ ("sync");
|
||||
sync();
|
||||
#endif
|
||||
|
||||
t_end = get_tbms();
|
||||
@ -922,8 +940,8 @@ void ddr_enable_ecc(unsigned int dram_size)
|
||||
/* Enable errors for ECC */
|
||||
ddr->err_disable &= ECC_ERROR_ENABLE;
|
||||
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
sync();
|
||||
isync();
|
||||
}
|
||||
#endif /* CONFIG_DDR_ECC */
|
||||
|
||||
|
||||
@ -85,35 +85,35 @@ int get_clocks(void)
|
||||
u32 lcrr;
|
||||
|
||||
u32 csb_clk;
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
u32 tsec1_clk;
|
||||
u32 tsec2_clk;
|
||||
u32 usbdr_clk;
|
||||
#elif defined(CONFIG_MPC8309)
|
||||
#elif defined(CONFIG_ARCH_MPC8309)
|
||||
u32 usbdr_clk;
|
||||
#endif
|
||||
#ifdef CONFIG_MPC834x
|
||||
#ifdef CONFIG_ARCH_MPC834X
|
||||
u32 usbmph_clk;
|
||||
#endif
|
||||
u32 core_clk;
|
||||
u32 i2c1_clk;
|
||||
#if !defined(CONFIG_MPC832x)
|
||||
#if !defined(CONFIG_ARCH_MPC832X)
|
||||
u32 i2c2_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC8315)
|
||||
u32 tdm_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
u32 sdhc_clk;
|
||||
#endif
|
||||
#if !defined(CONFIG_MPC8309)
|
||||
#if !defined(CONFIG_ARCH_MPC8309)
|
||||
u32 enc_clk;
|
||||
#endif
|
||||
u32 lbiu_clk;
|
||||
u32 lclk_clk;
|
||||
u32 mem_clk;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_ARCH_MPC8360)
|
||||
u32 mem_sec_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_QE)
|
||||
@ -122,12 +122,12 @@ int get_clocks(void)
|
||||
u32 qe_clk;
|
||||
u32 brg_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
u32 pciexp1_clk;
|
||||
u32 pciexp2_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
|
||||
u32 sata_clk;
|
||||
#endif
|
||||
|
||||
@ -137,8 +137,8 @@ int get_clocks(void)
|
||||
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
|
||||
|
||||
if (im->reset.rcwh & HRCWH_PCI_HOST) {
|
||||
#if defined(CONFIG_83XX_CLKIN)
|
||||
pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
|
||||
#if defined(CONFIG_SYS_CLK_FREQ)
|
||||
pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
|
||||
#else
|
||||
pci_sync_in = 0xDEADBEEF;
|
||||
#endif
|
||||
@ -155,8 +155,8 @@ int get_clocks(void)
|
||||
|
||||
sccr = im->clk.sccr;
|
||||
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
|
||||
case 0:
|
||||
tsec1_clk = 0;
|
||||
@ -176,8 +176,8 @@ int get_clocks(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
|
||||
case 0:
|
||||
usbdr_clk = 0;
|
||||
@ -197,8 +197,8 @@ int get_clocks(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
|
||||
case 0:
|
||||
tsec2_clk = 0;
|
||||
@ -216,7 +216,7 @@ int get_clocks(void)
|
||||
/* unknown SCCR_TSEC2CM value */
|
||||
return -4;
|
||||
}
|
||||
#elif defined(CONFIG_MPC8313)
|
||||
#elif defined(CONFIG_ARCH_MPC8313)
|
||||
tsec2_clk = tsec1_clk;
|
||||
|
||||
if (!(sccr & SCCR_TSEC1ON))
|
||||
@ -225,7 +225,7 @@ int get_clocks(void)
|
||||
tsec2_clk = 0;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
|
||||
case 0:
|
||||
usbmph_clk = 0;
|
||||
@ -252,7 +252,7 @@ int get_clocks(void)
|
||||
return -6;
|
||||
}
|
||||
#endif
|
||||
#if !defined(CONFIG_MPC8309)
|
||||
#if !defined(CONFIG_ARCH_MPC8309)
|
||||
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
|
||||
case 0:
|
||||
enc_clk = 0;
|
||||
@ -291,7 +291,7 @@ int get_clocks(void)
|
||||
return -8;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC8315)
|
||||
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
|
||||
case 0:
|
||||
tdm_clk = 0;
|
||||
@ -311,27 +311,27 @@ int get_clocks(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
i2c1_clk = tsec2_clk;
|
||||
#elif defined(CONFIG_MPC8360)
|
||||
#elif defined(CONFIG_ARCH_MPC8360)
|
||||
i2c1_clk = csb_clk;
|
||||
#elif defined(CONFIG_MPC832x)
|
||||
#elif defined(CONFIG_ARCH_MPC832X)
|
||||
i2c1_clk = enc_clk;
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
|
||||
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
|
||||
i2c1_clk = enc_clk;
|
||||
#elif defined(CONFIG_FSL_ESDHC)
|
||||
i2c1_clk = sdhc_clk;
|
||||
#elif defined(CONFIG_MPC837x)
|
||||
#elif defined(CONFIG_ARCH_MPC837X)
|
||||
i2c1_clk = enc_clk;
|
||||
#elif defined(CONFIG_MPC8309)
|
||||
#elif defined(CONFIG_ARCH_MPC8309)
|
||||
i2c1_clk = csb_clk;
|
||||
#endif
|
||||
#if !defined(CONFIG_MPC832x)
|
||||
#if !defined(CONFIG_ARCH_MPC832X)
|
||||
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
|
||||
case 0:
|
||||
pciexp1_clk = 0;
|
||||
@ -369,7 +369,7 @@ int get_clocks(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
|
||||
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
|
||||
case 0:
|
||||
sata_clk = 0;
|
||||
@ -407,7 +407,7 @@ int get_clocks(void)
|
||||
(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
|
||||
corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
|
||||
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_ARCH_MPC8360)
|
||||
mem_sec_clk = csb_clk * (1 +
|
||||
((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
|
||||
#endif
|
||||
@ -448,18 +448,18 @@ int get_clocks(void)
|
||||
#endif
|
||||
|
||||
gd->arch.csb_clk = csb_clk;
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
gd->arch.tsec1_clk = tsec1_clk;
|
||||
gd->arch.tsec2_clk = tsec2_clk;
|
||||
gd->arch.usbdr_clk = usbdr_clk;
|
||||
#elif defined(CONFIG_MPC8309)
|
||||
#elif defined(CONFIG_ARCH_MPC8309)
|
||||
gd->arch.usbdr_clk = usbdr_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
gd->arch.usbmph_clk = usbmph_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC8315)
|
||||
gd->arch.tdm_clk = tdm_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
@ -467,28 +467,28 @@ int get_clocks(void)
|
||||
#endif
|
||||
gd->arch.core_clk = core_clk;
|
||||
gd->arch.i2c1_clk = i2c1_clk;
|
||||
#if !defined(CONFIG_MPC832x)
|
||||
#if !defined(CONFIG_ARCH_MPC832X)
|
||||
gd->arch.i2c2_clk = i2c2_clk;
|
||||
#endif
|
||||
#if !defined(CONFIG_MPC8309)
|
||||
#if !defined(CONFIG_ARCH_MPC8309)
|
||||
gd->arch.enc_clk = enc_clk;
|
||||
#endif
|
||||
gd->arch.lbiu_clk = lbiu_clk;
|
||||
gd->arch.lclk_clk = lclk_clk;
|
||||
gd->mem_clk = mem_clk;
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_ARCH_MPC8360)
|
||||
gd->arch.mem_sec_clk = mem_sec_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_QE)
|
||||
gd->arch.qe_clk = qe_clk;
|
||||
gd->arch.brg_clk = brg_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
gd->arch.pciexp1_clk = pciexp1_clk;
|
||||
gd->arch.pciexp2_clk = pciexp2_clk;
|
||||
#endif
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
|
||||
gd->arch.sata_clk = sata_clk;
|
||||
#endif
|
||||
gd->pci_clk = pci_sync_in;
|
||||
@ -516,6 +516,11 @@ ulong get_ddr_freq(ulong dummy)
|
||||
return gd->mem_clk;
|
||||
}
|
||||
|
||||
int get_serial_clock(void)
|
||||
{
|
||||
return get_bus_freq(0);
|
||||
}
|
||||
|
||||
static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
char buf[32];
|
||||
@ -536,21 +541,21 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
printf(" Local Bus: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.lclk_clk));
|
||||
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
|
||||
#if defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_ARCH_MPC8360)
|
||||
printf(" DDR Secondary: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.mem_sec_clk));
|
||||
#endif
|
||||
#if !defined(CONFIG_MPC8309)
|
||||
#if !defined(CONFIG_ARCH_MPC8309)
|
||||
printf(" SEC: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.enc_clk));
|
||||
#endif
|
||||
printf(" I2C1: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.i2c1_clk));
|
||||
#if !defined(CONFIG_MPC832x)
|
||||
#if !defined(CONFIG_ARCH_MPC832X)
|
||||
printf(" I2C2: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.i2c2_clk));
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC8315)
|
||||
printf(" TDM: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.tdm_clk));
|
||||
#endif
|
||||
@ -558,30 +563,30 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
printf(" SDHC: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.sdhc_clk));
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
printf(" TSEC1: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.tsec1_clk));
|
||||
printf(" TSEC2: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.tsec2_clk));
|
||||
printf(" USB DR: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.usbdr_clk));
|
||||
#elif defined(CONFIG_MPC8309)
|
||||
#elif defined(CONFIG_ARCH_MPC8309)
|
||||
printf(" USB DR: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.usbdr_clk));
|
||||
#endif
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
printf(" USB MPH: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.usbmph_clk));
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
printf(" PCIEXP1: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.pciexp1_clk));
|
||||
printf(" PCIEXP2: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.pciexp2_clk));
|
||||
#endif
|
||||
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
|
||||
printf(" SATA: %-4s MHz\n",
|
||||
strmhz(buf, gd->arch.sata_clk));
|
||||
#endif
|
||||
|
||||
@ -6,6 +6,9 @@
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
|
||||
#include "lblaw/lblaw.h"
|
||||
#include "elbc/elbc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
@ -24,16 +27,16 @@ void cpu_init_f (volatile immap_t * im)
|
||||
|
||||
/* system performance tweaking */
|
||||
|
||||
#ifdef CONFIG_SYS_ACR_PIPE_DEP
|
||||
#ifndef CONFIG_ACR_PIPE_DEP_UNSET
|
||||
/* Arbiter pipeline depth */
|
||||
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
|
||||
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
|
||||
CONFIG_ACR_PIPE_DEP;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT
|
||||
#ifndef CONFIG_ACR_RPTCNT_UNSET
|
||||
/* Arbiter repeat count */
|
||||
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
|
||||
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
|
||||
CONFIG_ACR_RPTCNT;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_SPCR_OPT
|
||||
@ -89,3 +92,11 @@ void puts(const char *str)
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
|
||||
|
||||
return CONFIG_SYS_CLK_FREQ * spmf;
|
||||
}
|
||||
|
||||
@ -24,6 +24,10 @@
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/u-boot.h>
|
||||
|
||||
#include "hrcw/hrcw.h"
|
||||
#include "bats/bats.h"
|
||||
#include "hid/hid.h"
|
||||
|
||||
/* We don't want the MMU yet.
|
||||
*/
|
||||
#undef MSR_KERNEL
|
||||
@ -115,18 +119,6 @@ disable_addr_trans:
|
||||
mtspr SRR1, r3
|
||||
rfi
|
||||
|
||||
.globl ppcDWstore
|
||||
ppcDWstore:
|
||||
lfd 1, 0(r4)
|
||||
stfd 1, 0(r3)
|
||||
blr
|
||||
|
||||
.globl ppcDWload
|
||||
ppcDWload:
|
||||
lfd 1, 0(r3)
|
||||
stfd 1, 0(r4)
|
||||
blr
|
||||
|
||||
#ifndef CONFIG_DEFAULT_IMMR
|
||||
#error CONFIG_DEFAULT_IMMR must be defined
|
||||
#endif /* CONFIG_DEFAULT_IMMR */
|
||||
|
||||
7
arch/powerpc/cpu/mpc83xx/sysio/Kconfig
Normal file
7
arch/powerpc/cpu/mpc83xx/sysio/Kconfig
Normal file
@ -0,0 +1,7 @@
|
||||
menu "System I/O configuration"
|
||||
|
||||
if ARCH_MPC8308
|
||||
source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308"
|
||||
endif
|
||||
|
||||
endmenu
|
||||
323
arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
Normal file
323
arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
Normal file
@ -0,0 +1,323 @@
|
||||
choice
|
||||
prompt "SPI group"
|
||||
|
||||
config SICR_SPI_SPI
|
||||
bool "SPI"
|
||||
|
||||
config SICR_SPI_MSRCID
|
||||
bool "MSRCID"
|
||||
|
||||
config SICR_SPI_LSRCID
|
||||
bool "LSRCID"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "UART group"
|
||||
|
||||
config SICR_UART_SPI
|
||||
bool "UART"
|
||||
|
||||
config SICR_UART_MSRCID
|
||||
bool "MSRCID"
|
||||
|
||||
config SICR_UART_LSRCID
|
||||
bool "LSRCID"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "IRQ group"
|
||||
|
||||
config SICR_IRQ_SPI
|
||||
bool "IRQ"
|
||||
|
||||
config SICR_IRQ_MCP_CKSTOP
|
||||
bool "MCP/CKSTOP"
|
||||
|
||||
config SICR_IRQ_INTA
|
||||
bool "INTA"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "I2C2 group"
|
||||
|
||||
config SICR_I2C2_I2C
|
||||
bool "IRQ"
|
||||
|
||||
config SICR_I2C2_CKSTOP
|
||||
bool "CKSTOP"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "ETSEC1 A group"
|
||||
|
||||
config SICR_ETSEC1_A_TSEC2
|
||||
bool "TSEC1"
|
||||
|
||||
config SICR_ETSEC1_A_TSEC_GTX_CLK125
|
||||
bool "TSEC1 GTX_CLK125"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "eSDHC A group"
|
||||
|
||||
config SICR_ESDHC_A_SD
|
||||
bool "SD"
|
||||
|
||||
config SICR_ESDHC_A_GTM
|
||||
bool "GTM"
|
||||
|
||||
config SICR_ESDHC_A_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "eSDHC B group"
|
||||
|
||||
config SICR_ESDHC_B_SD
|
||||
bool "SD"
|
||||
|
||||
config SICR_ESDHC_B_GTM
|
||||
bool "GTM"
|
||||
|
||||
config SICR_ESDHC_B_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "eSDHC C group"
|
||||
|
||||
config SICR_ESDHC_C_SD
|
||||
bool "SD"
|
||||
|
||||
config SICR_ESDHC_C_GTM
|
||||
bool "GTM"
|
||||
|
||||
config SICR_ESDHC_C_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "GPIO A group"
|
||||
|
||||
config SICR_GPIO_A_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
config SICR_GPIO_A_TSEC2
|
||||
bool "TSEC2"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "GPIO B group"
|
||||
|
||||
config SICR_GPIO_B_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
config SICR_GPIO_B_TSEC2
|
||||
bool "TSEC2"
|
||||
|
||||
config SICR_GPIO_B_TSEC_GTX_CLK125
|
||||
bool "TSEC2 GTX_CLK125"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "IEEE1588 A group"
|
||||
|
||||
config SICR_IEEE1588_A_TSEC
|
||||
bool "TSEC"
|
||||
|
||||
config SICR_IEEE1588_A_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "USB group"
|
||||
|
||||
config SICR_USB_TSEC
|
||||
bool "USB"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "GTM group"
|
||||
|
||||
config SICR_GTM_TSEC
|
||||
bool "GTM"
|
||||
|
||||
config SICR_GTM_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "IEEE1588 B group"
|
||||
|
||||
config SICR_IEEE1588_B_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "ETSEC2 group"
|
||||
|
||||
config SICR_ETSEC2_TSEC2
|
||||
bool "TSEC2"
|
||||
|
||||
config SICR_ETSEC2_GPIO
|
||||
bool "GPIO"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "GPIO selection"
|
||||
|
||||
config SICR_GPIOSEL_GPIO
|
||||
bool "GPIO_A, GPIO_B"
|
||||
|
||||
config SICR_GPIOSEL_IEEE1588
|
||||
bool "IEEE1588_A, IEEE1588_B, ETSEC2"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "IEEE1588 timer output buffer impedance"
|
||||
|
||||
config SICR_TMROBI_3_3_V
|
||||
bool "40 Ohm, 3.3V"
|
||||
|
||||
config SICR_TMROBI_2_5_V
|
||||
bool "40 Ohm, 2.5V"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "TSEC1 output buffer impedance"
|
||||
|
||||
config SICR_TMSOBI1_3_3_V
|
||||
bool "40 Ohm, 3.3V"
|
||||
|
||||
config SICR_TMSOBI1_2_5_V
|
||||
bool "40 Ohm, 2.5V"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "TSEC2 output buffer impedance"
|
||||
|
||||
config SICR_TMSOBI2_3_3_V
|
||||
bool "40 Ohm, 3.3V"
|
||||
|
||||
config SICR_TMSOBI2_2_5_V
|
||||
bool "40 Ohm, 2.5V"
|
||||
|
||||
endchoice
|
||||
|
||||
config SICRL_SPI
|
||||
hex
|
||||
default 0x0 if SICR_SPI_SPI
|
||||
default 0x10000000 if SICR_SPI_MSRCID
|
||||
default 0x30000000 if SICR_SPI_LSRCID
|
||||
|
||||
config SICRL_UART
|
||||
hex
|
||||
default 0x0 if SICR_UART_SPI
|
||||
default 0x4000000 if SICR_UART_MSRCID
|
||||
default 0xc000000 if SICR_UART_LSRCID
|
||||
|
||||
config SICRL_IRQ
|
||||
hex
|
||||
default 0x0 if SICR_IRQ_SPI
|
||||
default 0x1000000 if SICR_IRQ_MCP_CKSTOP
|
||||
default 0x3000000 if SICR_IRQ_INTA
|
||||
|
||||
config SICRL_I2C2
|
||||
hex
|
||||
default 0x0 if SICR_I2C2_I2C
|
||||
default 0x100000 if SICR_I2C2_CKSTOP
|
||||
|
||||
config SICRL_ETSEC1_A
|
||||
hex
|
||||
default 0x0 if SICR_ETSEC1_A_TSEC2
|
||||
default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125
|
||||
|
||||
config SICRH_ESDHC_A
|
||||
hex
|
||||
default 0x0 if SICR_ESDHC_A_SD
|
||||
default 0x40000000 if SICR_ESDHC_A_GTM
|
||||
default 0xc0000000 if SICR_ESDHC_A_GPIO
|
||||
|
||||
config SICRH_ESDHC_B
|
||||
hex
|
||||
default 0x0 if SICR_ESDHC_B_SD
|
||||
default 0x10000000 if SICR_ESDHC_B_GTM
|
||||
default 0x30000000 if SICR_ESDHC_B_GPIO
|
||||
|
||||
config SICRH_ESDHC_C
|
||||
hex
|
||||
default 0x0 if SICR_ESDHC_C_SD
|
||||
default 0x4000000 if SICR_ESDHC_C_GTM
|
||||
default 0xc000000 if SICR_ESDHC_C_GPIO
|
||||
|
||||
config SICRH_GPIO_A
|
||||
hex
|
||||
default 0x0 if SICR_GPIO_A_GPIO
|
||||
default 0x1000000 if SICR_GPIO_A_TSEC2
|
||||
|
||||
config SICRH_GPIO_B
|
||||
hex
|
||||
default 0x0 if SICR_GPIO_B_GPIO
|
||||
default 0x400000 if SICR_GPIO_B_TSEC2
|
||||
default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125
|
||||
|
||||
config SICRH_IEEE1588_A
|
||||
hex
|
||||
default 0x100000 if SICR_IEEE1588_A_TSEC
|
||||
default 0x300000 if SICR_IEEE1588_A_GPIO
|
||||
|
||||
config SICRH_USB
|
||||
hex
|
||||
default 0x40000 if SICR_USB_TSEC
|
||||
|
||||
config SICRH_GTM
|
||||
hex
|
||||
default 0x10000 if SICR_GTM_TSEC
|
||||
default 0x30000 if SICR_GTM_GPIO
|
||||
|
||||
config SICRH_IEEE1588_B
|
||||
hex
|
||||
default 0xc000 if SICR_IEEE1588_B_GPIO
|
||||
|
||||
config SICRH_ETSEC2
|
||||
hex
|
||||
default 0x1000 if SICR_ETSEC2_TSEC2
|
||||
default 0x3000 if SICR_ETSEC2_GPIO
|
||||
|
||||
config SICRH_GPIOSEL
|
||||
hex
|
||||
default 0x0 if SICR_GPIOSEL_GPIO
|
||||
default 0x100 if SICR_GPIOSEL_IEEE1588
|
||||
|
||||
config SICRH_TMROBI
|
||||
hex
|
||||
default 0x0 if SICR_TMROBI_3_3_V
|
||||
default 0x10 if SICR_TMROBI_2_5_V
|
||||
|
||||
config SICRH_TMSOBI1
|
||||
hex
|
||||
default 0x0 if SICR_TMSOBI1_3_3_V
|
||||
default 0x2 if SICR_TMSOBI1_2_5_V
|
||||
|
||||
config SICRH_TMSOBI2
|
||||
hex
|
||||
default 0x0 if SICR_TMSOBI2_3_3_V
|
||||
default 0x1 if SICR_TMSOBI2_2_5_V
|
||||
32
arch/powerpc/cpu/mpc83xx/sysio/sysio.h
Normal file
32
arch/powerpc/cpu/mpc83xx/sysio/sysio.h
Normal file
@ -0,0 +1,32 @@
|
||||
#ifdef CONFIG_ARCH_MPC8308
|
||||
|
||||
#ifndef CONFIG_SYS_SICRL
|
||||
#define CONFIG_SYS_SICRL (\
|
||||
CONFIG_SICRL_SPI |\
|
||||
CONFIG_SICRL_UART |\
|
||||
CONFIG_SICRL_IRQ |\
|
||||
CONFIG_SICRL_I2C2 |\
|
||||
CONFIG_SICRL_ETSEC1_A \
|
||||
)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_SICRH
|
||||
#define CONFIG_SYS_SICRH (\
|
||||
CONFIG_SICRH_ESDHC_A |\
|
||||
CONFIG_SICRH_ESDHC_B |\
|
||||
CONFIG_SICRH_ESDHC_C |\
|
||||
CONFIG_SICRH_GPIO_A |\
|
||||
CONFIG_SICRH_GPIO_B |\
|
||||
CONFIG_SICRH_IEEE1588_A |\
|
||||
CONFIG_SICRH_USB |\
|
||||
CONFIG_SICRH_GTM |\
|
||||
CONFIG_SICRH_IEEE1588_B |\
|
||||
CONFIG_SICRH_ETSEC2 |\
|
||||
CONFIG_SICRH_GPIOSEL |\
|
||||
CONFIG_SICRH_TMROBI |\
|
||||
CONFIG_SICRH_TMSOBI1 |\
|
||||
CONFIG_SICRH_TMSOBI2 \
|
||||
)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -52,6 +52,12 @@ SECTIONS
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
/*
|
||||
* _end - This is end of u-boot.bin image.
|
||||
* dtb will be appended here to make u-boot-dtb.bin
|
||||
*/
|
||||
_end = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
|
||||
@ -6,6 +6,10 @@
|
||||
#include <common.h>
|
||||
#include <asm/fsl_lbc.h>
|
||||
|
||||
#ifdef CONFIG_MPC83xx
|
||||
#include "../mpc83xx/elbc/elbc.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC85xx
|
||||
/* Boards should provide their own version of this if they use lbc sdram */
|
||||
static void __lbc_sdram_init(void)
|
||||
|
||||
@ -131,10 +131,10 @@ static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
|
||||
set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
|
||||
}
|
||||
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
/* Mark the ppace entry valid */
|
||||
ppaace->addr_bitfields |= PAACE_V_VALID;
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -279,7 +279,7 @@ int pamu_init(void)
|
||||
out_be32(®s->splah, spaact_lim >> 32);
|
||||
out_be32(®s->splal, (uint32_t)spaact_lim);
|
||||
}
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
|
||||
base_addr += PAMU_OFFSET;
|
||||
}
|
||||
@ -294,7 +294,7 @@ void pamu_enable(void)
|
||||
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
|
||||
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
|
||||
PAMU_PCR_PE);
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
base_addr += PAMU_OFFSET;
|
||||
}
|
||||
}
|
||||
@ -318,7 +318,7 @@ void pamu_reset(void)
|
||||
out_be32(®s->splal, 0);
|
||||
|
||||
clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
base_addr += PAMU_OFFSET;
|
||||
}
|
||||
}
|
||||
@ -331,7 +331,7 @@ void pamu_disable(void)
|
||||
|
||||
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
|
||||
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
|
||||
asm volatile("sync" : : : "memory");
|
||||
sync();
|
||||
base_addr += PAMU_OFFSET;
|
||||
}
|
||||
}
|
||||
|
||||
1
arch/powerpc/dts/.gitignore
vendored
Normal file
1
arch/powerpc/dts/.gitignore
vendored
Normal file
@ -0,0 +1 @@
|
||||
*.dtb
|
||||
@ -2,6 +2,7 @@
|
||||
|
||||
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
|
||||
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
|
||||
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
|
||||
602
arch/powerpc/dts/gazerbeam.dts
Normal file
602
arch/powerpc/dts/gazerbeam.dts
Normal file
@ -0,0 +1,602 @@
|
||||
/*
|
||||
* Gazerbeam CON Device Tree Source
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include "gdsys/mpc8308.dtsi"
|
||||
|
||||
/include/ "gdsys/gazerbeam-base.dtsi"
|
||||
|
||||
/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
|
||||
/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
|
||||
/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
|
||||
/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
|
||||
|
||||
&board_lbc {
|
||||
FPGA0:iocon_uart@1,0 {
|
||||
reg = <0x1 0x0 0x100000>;
|
||||
little-endian;
|
||||
interrupts = <48 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
FPGA1:iocon_uart@2,0 {
|
||||
reg = <0x2 0x0 0x100000>;
|
||||
little-endian;
|
||||
interrupts = <17 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
|
||||
&FPGA0 {
|
||||
compatible = "gdsys,iocon_fpga";
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
bus = <&FPGA0BUS>;
|
||||
unit_id = <0>;
|
||||
fpga-type = <1>;
|
||||
usb_base = <0x0080>;
|
||||
audio_base = <0x0040>;
|
||||
timebase_base = <0x013c>;
|
||||
|
||||
/*
|
||||
* for every interrupt source there must be a dataset specifying
|
||||
* 1. type (1: standard)
|
||||
* 2. status register offset
|
||||
* 3. mask register offset
|
||||
* 4. default mask
|
||||
*/
|
||||
fpga_interrupt_sources =
|
||||
<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
|
||||
<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
|
||||
/*
|
||||
* for every interrupt there must be a dataset specifying
|
||||
* 1. type (1: status, 2: event)
|
||||
* 2. interrupt source index
|
||||
* 3. interrupt register bit
|
||||
* 4. mask register bit
|
||||
*/
|
||||
#fpga_interrupt_map-cells = <4>;
|
||||
fpga_interrupt_map =
|
||||
<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
|
||||
<1 0 0 0>, /* 1: VIDEO 0 */
|
||||
<1 0 1 1>, /* 2: VIDEO 1 */
|
||||
<1 0 2 2>, /* 3: VIDEO IC 0 */
|
||||
<1 0 3 3>, /* 4: VIDEO IC 1 */
|
||||
<1 0 4 4>, /* 5: IIC MAIN */
|
||||
<1 0 6 6>, /* 6: IIC VIDEO 0 */
|
||||
<1 0 7 7>, /* 7: IIC VIDEO 1 */
|
||||
<1 1 0 0>, /* 8: OSD 0 */
|
||||
<1 1 1 1>, /* 9: OSD 1 */
|
||||
<1 1 2 2>, /* 10: SPDIF 0 */
|
||||
<1 1 3 3>, /* 11: SPDIF 1 */
|
||||
<1 0 12 12>, /* 12: COMM 0 */
|
||||
<1 0 13 13>, /* 13: COMM 1 */
|
||||
<1 0 10 10>, /* 14: COMM 2 */
|
||||
<1 0 11 11>, /* 15: COMM 3 */
|
||||
<2 0 5 5>, /* 16: MDIO */
|
||||
<1 0 8 8>, /* 17: PHY */
|
||||
<1 1 4 4>, /* 18: RS232 */
|
||||
<1 1 5 5>, /* 19: AUDIO */
|
||||
<1 1 8 8>, /* 20: PROC_AUDIO */
|
||||
<1 1 7 7>, /* 21: USB/ETH-UART INT */
|
||||
<2 1 10 10>, /* 22: AXI Bridge 0 */
|
||||
<2 1 11 11>, /* 23: AXI Bridge 1 */
|
||||
<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
|
||||
<>;
|
||||
};
|
||||
|
||||
&FPGA1 {
|
||||
compatible = "gdsys,iocon_fpga";
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
bus = <&FPGA1BUS>;
|
||||
unit_id = <1>;
|
||||
fpga-type = <1>;
|
||||
usb_base = <0x0070>;
|
||||
audio_base = <0x0040>;
|
||||
timebase_base = <0x013c>;
|
||||
|
||||
/*
|
||||
* for every interrupt source there must be a dataset specifying
|
||||
* 1. type (1: standard)
|
||||
* 2. status register offset
|
||||
* 3. mask register offset
|
||||
* 4. default mask
|
||||
*/
|
||||
fpga_interrupt_sources =
|
||||
<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
|
||||
<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
|
||||
/*
|
||||
* for every interrupt there must be a dataset specifying
|
||||
* 1. type (1: status, 2: event)
|
||||
* 2. interrupt source index
|
||||
* 3. interrupt register bit
|
||||
* 4. mask register bit
|
||||
*/
|
||||
#fpga_interrupt_map-cells = <4>;
|
||||
fpga_interrupt_map =
|
||||
<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
|
||||
<1 0 0 0>, /* 1: VIDEO 0 */
|
||||
<1 0 1 1>, /* 2: VIDEO 1 */
|
||||
<1 0 2 2>, /* 3: VIDEO IC 0 */
|
||||
<1 0 3 3>, /* 4: VIDEO IC 1 */
|
||||
<1 0 4 4>, /* 5: IIC MAIN */
|
||||
<1 0 6 6>, /* 6: IIC VIDEO 0 */
|
||||
<1 0 7 7>, /* 7: IIC VIDEO 1 */
|
||||
<1 1 0 0>, /* 8: OSD 0 */
|
||||
<1 1 1 1>, /* 9: OSD 1 */
|
||||
<1 1 2 2>, /* 10: SPDIF 0 */
|
||||
<1 1 3 3>, /* 11: SPDIF 1 */
|
||||
<1 0 12 12>, /* 12: COMM 0 */
|
||||
<1 0 13 13>, /* 13: COMM 1 */
|
||||
<1 0 10 10>, /* 14: COMM 2 */
|
||||
<1 0 11 11>, /* 15: COMM 3 */
|
||||
<2 0 5 5>, /* 16: MDIO */
|
||||
<1 0 8 8>, /* 17: PHY */
|
||||
<1 1 4 4>, /* 18: RS232 */
|
||||
<1 1 5 5>, /* 19: AUDIO */
|
||||
<1 1 8 8>, /* 20: PROC_AUDIO */
|
||||
<1 1 7 7>, /* 21: USB/ETH-UART INT */
|
||||
<2 1 10 10>, /* 22: AXI Bridge 0 */
|
||||
<2 1 11 11>, /* 23: AXI Bridge 1 */
|
||||
<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
|
||||
<>;
|
||||
};
|
||||
|
||||
/ {
|
||||
FPGA0BUS: fpga0bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x00002000>;
|
||||
|
||||
compatible = "gdsys,soc";
|
||||
|
||||
fpga0_rs232 {
|
||||
compatible = "gdsys,ihs_trans_rs232";
|
||||
reg = <0x50 0x08>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
fpga0_uart_usb {
|
||||
compatible = "gdsys,ihs_simple_uart";
|
||||
reg = <0xa0 0x08>;
|
||||
little-endian;
|
||||
fpga_interrupts = <21>;
|
||||
line = <0>;
|
||||
};
|
||||
|
||||
fpga0_iic_main {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x60 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2c>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2e>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
lm77@48 {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x48>;
|
||||
};
|
||||
ads1015@49 {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
ads1015@4b {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_video0 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x100 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <1 8>; /* VIDEO OSD */
|
||||
osd_base = <0x180>;
|
||||
osd_buffer_base = <0x1000>;
|
||||
spdif_audio_base = <0x1e0>;
|
||||
video_index = <0>;
|
||||
video_id = <0>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga0_dp_video0>;
|
||||
clk_gen = <&fpga0_video0_clkgen>;
|
||||
ddc_ci = <&fpga0_dp_video0>;
|
||||
};
|
||||
|
||||
fpga0_iic_video0 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x1c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_video0_clkgen: fpga0_video0_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_axi_video0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x170 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <22>;
|
||||
|
||||
fpga0_dp_video0: fpga0_dp_video0 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga0_dp_video0_redriver>;
|
||||
video_id = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_video1 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x200 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <2 9>; /* VIDEO OSD */
|
||||
osd_base = <0x280>;
|
||||
osd_buffer_base = <0x2000>;
|
||||
spdif_audio_base = <0x2e0>;
|
||||
video_index = <1>;
|
||||
video_id = <1>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga0_dp_video1>;
|
||||
clk_gen = <&fpga0_video1_clkgen>;
|
||||
ddc_ci = <&fpga0_dp_video1>;
|
||||
};
|
||||
|
||||
fpga0_iic_video1 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x2c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_video1_clkgen: fpga0_video1_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_axi_video1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x270 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <23>;
|
||||
|
||||
fpga0_dp_video1: fpga0_dp_video1 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga0_dp_video1_redriver>;
|
||||
video_id = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_iic_usb {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0xb0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_ep0 {
|
||||
compatible = "gdsys,io-endpoint";
|
||||
reg = < 0x020 0x10
|
||||
0x320 0x10
|
||||
0x340 0x10
|
||||
0x360 0x10>;
|
||||
little-endian;
|
||||
irq-model-local;
|
||||
fpga_interrupts = <12 13 14 15>;
|
||||
pollcycle = <200>;
|
||||
nprot_channel = <16>;
|
||||
uart_line = <0>;
|
||||
ep_index = <0>;
|
||||
line_protocol = <1>;
|
||||
};
|
||||
|
||||
fpga0_mdio {
|
||||
compatible = "gdsys,ihs_mdiomaster";
|
||||
reg = <0x0058 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_phy0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
fpga0_phy1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
fpga0_phy2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <2>;
|
||||
};
|
||||
fpga0_phy3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
FPGA1BUS: fpga1bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x00002000>;
|
||||
|
||||
compatible = "gdsys,soc";
|
||||
|
||||
fpga1_uart_usb {
|
||||
compatible = "gdsys,ihs_simple_uart";
|
||||
reg = <0xa0 0x08>;
|
||||
little-endian;
|
||||
fpga_interrupts = <21>;
|
||||
line = <4>; /* TODO check and FIX */
|
||||
};
|
||||
|
||||
fpga1_iic_main {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x60 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2c>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2e>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
lm77@48 {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x48>;
|
||||
};
|
||||
ads1015@49 {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
ads1015@4b {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_video0 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x100 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <1 8>; /* VIDEO OSD */
|
||||
osd_base = <0x180>;
|
||||
osd_buffer_base = <0x1000>;
|
||||
spdif_audio_base = <0x1e0>;
|
||||
video_index = <0>;
|
||||
video_id = <4>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga1_dp_video0>;
|
||||
clk_gen = <&fpga1_video0_clkgen>;
|
||||
ddc_ci = <&fpga1_dp_video0>;
|
||||
};
|
||||
|
||||
fpga1_iic_video0 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x1c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_video0_clkgen: fpga1_video0_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_axi_video0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x170 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <22>;
|
||||
|
||||
fpga1_dp_video0: fpga1_dp_video0 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga1_dp_video0_redriver>;
|
||||
video_id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_video1 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x200 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <2 9>; /* VIDEO OSD */
|
||||
osd_base = <0x280>;
|
||||
osd_buffer_base = <0x2000>;
|
||||
spdif_audio_base = <0x2e0>;
|
||||
video_index = <1>;
|
||||
video_id = <5>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga1_dp_video1>;
|
||||
clk_gen = <&fpga1_video1_clkgen>;
|
||||
ddc_ci = <&fpga1_dp_video1>;
|
||||
};
|
||||
|
||||
fpga1_iic_video1 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x2c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_video1_clkgen: fpga1_video1_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_axi_video1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x270 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <23>;
|
||||
|
||||
fpga1_dp_video1: fpga1_dp_video1 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga1_dp_video1_redriver>;
|
||||
video_id = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_iic_usb {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0xb0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_ep0 {
|
||||
compatible = "gdsys,io-endpoint";
|
||||
reg = < 0x020 0x10
|
||||
0x320 0x10
|
||||
0x340 0x10
|
||||
0x360 0x10>;
|
||||
little-endian;
|
||||
irq-model-local;
|
||||
fpga_interrupts = <12 13 14 15>;
|
||||
pollcycle = <200>;
|
||||
nprot_channel = <17>;
|
||||
uart_line = <1>;
|
||||
ep_index = <0>;
|
||||
line_protocol = <1>;
|
||||
};
|
||||
|
||||
fpga1_mdio {
|
||||
compatible = "gdsys,ihs_mdiomaster";
|
||||
reg = <0x0058 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_phy0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
fpga1_phy1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
fpga1_phy2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <2>;
|
||||
};
|
||||
fpga1_phy3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "gdsys/gazerbeam-uboot.dtsi"
|
||||
185
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
Normal file
185
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
Normal file
@ -0,0 +1,185 @@
|
||||
/*
|
||||
* Gazerbeam Device Tree Source
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "gdsys,gazerbeam";
|
||||
compatible = "fsl,mpc8308rdb";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&IIC {
|
||||
fsl,preserve-clocking;
|
||||
|
||||
at97sc3205t@29 {
|
||||
compatible = "atmel,at97sc3204t";
|
||||
reg = <0x29>;
|
||||
};
|
||||
|
||||
lm77@48 {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
ads1015@49 {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
lm77@4a {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
|
||||
emc2305@2e {
|
||||
compatible = "smsc,emc2305";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2e>;
|
||||
fan@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
fan@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
fan@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
fan@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
fan@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
emc2305@4c {
|
||||
compatible = "smsc,emc2305";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4c>;
|
||||
fan@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
fan@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
fan@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
fan@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
fan@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
at24c512@54 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
/* PPC-Board */
|
||||
pca9698@22 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x22>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* IO-Board */
|
||||
pca9698@20 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC2 {
|
||||
fsl,preserve-clocking;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* MC2/SC-Board */
|
||||
GPIO_VB0: pca9698@20 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* MC4-Board */
|
||||
GPIO_VB1: pca9698@22 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x22>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
&SPI {
|
||||
gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
|
||||
/*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
|
||||
/*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
|
||||
/*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
|
||||
/*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
|
||||
/*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
|
||||
|
||||
m25p16@0 {
|
||||
compatible = "st,n25q128a11";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@1 {
|
||||
compatible = "st,n25q128a11";
|
||||
reg = <0x1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@2 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x2>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@3 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x3>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@4 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x4>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@5 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x5>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
250
arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
Normal file
250
arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
Normal file
@ -0,0 +1,250 @@
|
||||
#include <dt-bindings/memory/mpc83xx-sdram.h>
|
||||
#include <dt-bindings/clk/mpc83xx-clk.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c0 = &IIC;
|
||||
i2c1 = &IIC2;
|
||||
i2c2 = "/fpga0bus/fpga0_iic_main";
|
||||
i2c3 = "/fpga0bus/fpga0_iic_video0";
|
||||
i2c4 = "/fpga0bus/fpga0_iic_video1";
|
||||
i2c5 = "/fpga0bus/fpga0_iic_usb";
|
||||
gdsys_soc0 = "/fpga0bus";
|
||||
gdsys_soc1 = "/fpga1bus";
|
||||
ioep0 = "/fpga0bus/fpga0_ep0";
|
||||
ioep1 = "/fpga0bus/fpga1_ep0";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
compatible = "cpu_bus";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
PowerPC,8308@0 {
|
||||
compatible = "fsl,mpc8308";
|
||||
clocks = <&socclocks MPC83XX_CLK_CORE
|
||||
&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
board {
|
||||
compatible = "gdsys,board_gazerbeam";
|
||||
csb = <&board_soc>;
|
||||
serdes = <&SERDES>;
|
||||
rxaui0 = <&RXAUI0_0>;
|
||||
rxaui1 = <&RXAUI0_1>;
|
||||
rxaui2 = <&RXAUI0_2>;
|
||||
rxaui3 = <&RXAUI0_3>;
|
||||
rxaui4 = <&RXAUI1_0>;
|
||||
rxaui5 = <&RXAUI1_1>;
|
||||
rxaui6 = <&RXAUI1_2>;
|
||||
rxaui7 = <&RXAUI1_3>;
|
||||
fpga0 = <&FPGA0>;
|
||||
fpga1 = <&FPGA1>;
|
||||
ioep0 = <&IOEP0>;
|
||||
ioep1 = <&IOEP1>;
|
||||
|
||||
ver-gpios = <&PPCPCA 12 0
|
||||
&PPCPCA 13 0
|
||||
&PPCPCA 14 0
|
||||
&PPCPCA 15 0>;
|
||||
|
||||
/* MC2/SC-Board */
|
||||
var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
|
||||
&GPIO_VB0 11 0>; /* VAR-CON */
|
||||
/* MC4-Board */
|
||||
var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
|
||||
&GPIO_VB1 11 0>; /* VAR-CON */
|
||||
|
||||
reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
|
||||
};
|
||||
|
||||
socclocks: clocks {
|
||||
compatible = "fsl,mpc8308-clk";
|
||||
#clock-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "fsl,mpc83xx-timer";
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
};
|
||||
};
|
||||
|
||||
&FPGA0 {
|
||||
reset-gpios = <&PPCPCA 26 0>;
|
||||
done-gpios = <&GPIO_VB0 19 0>;
|
||||
};
|
||||
|
||||
&FPGA1 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
&FPGA0BUS {
|
||||
ranges = <0x0 0xe0600000 0x00004000>;
|
||||
fpga = <&FPGA0>;
|
||||
|
||||
fpga0_video0 {
|
||||
mode = "640_480_60";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
RXAUI0_0: fpga0_rxaui@fc0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fc0 0x10>;
|
||||
};
|
||||
|
||||
fpga0_iic_video0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_axi_video0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_video1 {
|
||||
mode = "640_480_60";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_iic_video1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_axi_video1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
IOEP0: fpga0_ep0 {
|
||||
};
|
||||
|
||||
RXAUI0_1: fpga0_rxaui@fd0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fd0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI0_2: fpga0_rxaui@fe0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fe0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI0_3: fpga0_rxaui@ff0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0ff0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
&FPGA1BUS {
|
||||
ranges = <0x0 0xe0700000 0x00004000>;
|
||||
fpga = <&FPGA1>;
|
||||
|
||||
status = "disable";
|
||||
|
||||
fpga1_video0 {
|
||||
mode = "640_480_60";
|
||||
};
|
||||
|
||||
RXAUI1_0: fpga0_rxaui@fc0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fc0 0x10>;
|
||||
};
|
||||
|
||||
fpga1_video1 {
|
||||
mode = "640_480_60";
|
||||
};
|
||||
|
||||
IOEP1: fpga1_ep0 {
|
||||
};
|
||||
|
||||
RXAUI1_1: fpga0_rxaui@fd0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fd0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI1_2: fpga0_rxaui@fe0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fe0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI1_3: fpga0_rxaui@ff0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0ff0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
|
||||
memory@2000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
clocks = <&socclocks MPC83XX_CLK_SDHC>;
|
||||
clock-names = "per";
|
||||
};
|
||||
|
||||
SERDES: serdes@e3000 {
|
||||
reg = <0xe3000 0x200>;
|
||||
compatible = "fsl,mpc83xx-serdes";
|
||||
proto = "pex";
|
||||
serdes-clk = <100>;
|
||||
vdd;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC {
|
||||
clocks = <&socclocks MPC83XX_CLK_I2C1>;
|
||||
|
||||
PPCPCA: pca9698@20 {
|
||||
label = "ppc";
|
||||
};
|
||||
|
||||
IOPCA: pca9698@22 {
|
||||
label = "io";
|
||||
};
|
||||
|
||||
at97sc3205t@29 {
|
||||
u-boot,i2c-offset-len = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC2 {
|
||||
clocks = <&socclocks MPC83XX_CLK_I2C2>;
|
||||
|
||||
GPIO_VB0: pca9698@20 {
|
||||
label = "mc2-sc";
|
||||
};
|
||||
|
||||
GPIO_VB1: pca9698@22 {
|
||||
label = "mc4";
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&GPIO_VB0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
|
||||
};
|
||||
354
arch/powerpc/dts/gdsys/mpc8308.dtsi
Normal file
354
arch/powerpc/dts/gdsys/mpc8308.dtsi
Normal file
@ -0,0 +1,354 @@
|
||||
/*
|
||||
* Basic platform for gdsys mpc8308 based devices
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* based on mpc8308rdb
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/memory/mpc83xx-sdram.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8308rdb";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8308@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
board_lbc: localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
board_soc: immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8308-immr", "simple-bus";
|
||||
ranges = <0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
memory@2000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc83xx-mem-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
device_type = "memory";
|
||||
|
||||
driver_software_override = <DSO_ENABLE>;
|
||||
p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
|
||||
n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
|
||||
odt_termination_value = <ODT_TERMINATION_150_OHM>;
|
||||
ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
|
||||
|
||||
clock_adjust = <CLOCK_ADJUST_05>;
|
||||
|
||||
read_to_write = <0>;
|
||||
write_to_read = <0>;
|
||||
read_to_read = <0>;
|
||||
write_to_write = <0>;
|
||||
active_powerdown_exit = <2>;
|
||||
precharge_powerdown_exit = <6>;
|
||||
odt_powerdown_exit = <8>;
|
||||
mode_reg_set_cycle = <2>;
|
||||
|
||||
precharge_to_activate = <2>;
|
||||
activate_to_precharge = <6>;
|
||||
activate_to_readwrite = <2>;
|
||||
mcas_latency = <CASLAT_40>;
|
||||
refresh_recovery = <17>;
|
||||
last_data_to_precharge = <2>;
|
||||
activate_to_activate = <2>;
|
||||
last_write_data_to_read = <2>;
|
||||
|
||||
additive_latency = <0>;
|
||||
mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
|
||||
write_latency = <3>;
|
||||
read_to_precharge = <2>;
|
||||
write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
|
||||
minimum_cke_pulse_width = <3>;
|
||||
four_activates_window = <5>;
|
||||
|
||||
self_refresh = <SREN_ENABLE>;
|
||||
sdram_type = <TYPE_DDR2>;
|
||||
databus_width = <DATA_BUS_WIDTH_32>;
|
||||
|
||||
force_self_refresh = <MODE_NORMAL>;
|
||||
dll_reset = <DLL_RESET_ENABLE>;
|
||||
dqs_config = <DQS_TRUE>;
|
||||
odt_config = <ODT_ASSERT_READS>;
|
||||
posted_refreshes = <1>;
|
||||
|
||||
refresh_interval = <2084>;
|
||||
precharge_interval = <256>;
|
||||
|
||||
sdmode = <0x0242>;
|
||||
esdmode = <0x0440>;
|
||||
|
||||
ram@0 {
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
compatible = "nanya,nt5tu64m16hg";
|
||||
|
||||
odt_rd_cfg = <ODT_RD_NEVER>;
|
||||
odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
|
||||
bank_bits = <3>;
|
||||
row_bits = <13>;
|
||||
col_bits = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC:i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
IIC2: i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
SPI:spi@7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
sdhci,auto-cmd12;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
gpio0: gpio@c00 {
|
||||
#gpio-cells = <2>;
|
||||
device_type = "gpio";
|
||||
compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xc00 0x18>;
|
||||
interrupts = <74 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
ipic-msi@7c0 {
|
||||
compatible = "fsl,ipic-msi";
|
||||
reg = <0x7c0 0x40>;
|
||||
msi-available-ranges = <0x0 0x100>;
|
||||
interrupts = < 0x43 0x8
|
||||
0x4 0x8
|
||||
0x51 0x8
|
||||
0x52 0x8
|
||||
0x56 0x8
|
||||
0x57 0x8
|
||||
0x58 0x8
|
||||
0x59 0x8 >;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
dma@2c000 {
|
||||
compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
|
||||
reg = <0x2c000 0x1800>;
|
||||
interrupts = <3 0x8
|
||||
94 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar", "fsl,tsec";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = < &tbi0 >;
|
||||
phy-handle = < &phy1 >;
|
||||
fsl,magic-packet;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar", "fsl,tsec";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy2 >;
|
||||
status = "disabled";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@e0009000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
|
||||
reg = <0xe0009000 0x00001000
|
||||
0xb0000000 0x01000000>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
|
||||
bus-range = <0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||
0 0 0 2 &ipic 1 8
|
||||
0 0 0 3 &ipic 1 8
|
||||
0 0 0 4 &ipic 1 8>;
|
||||
interrupts = <0x1 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <0>;
|
||||
|
||||
pcie@0 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
ranges = <0x02000000 0 0xa0000000
|
||||
0x02000000 0 0xa0000000
|
||||
0 0x10000000
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
6
arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
Normal file
6
arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
Normal file
@ -0,0 +1,6 @@
|
||||
&IIC {
|
||||
cs4265@4f {
|
||||
compatible = "cirrus,cs4265";
|
||||
reg = <0x0000004f>;
|
||||
};
|
||||
};
|
||||
6
arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
Normal file
6
arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
Normal file
@ -0,0 +1,6 @@
|
||||
&IIC {
|
||||
ds1339@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
5
arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
Normal file
5
arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
Normal file
@ -0,0 +1,5 @@
|
||||
&board_lbc {
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00003000
|
||||
0x2 0x0 0xe0700000 0x00003000>;
|
||||
};
|
||||
20
arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
Normal file
20
arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
Normal file
@ -0,0 +1,20 @@
|
||||
&board_lbc {
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
env@80000 {
|
||||
reg = <0x80000 0x10000>;
|
||||
};
|
||||
env1@90000 {
|
||||
reg = <0x90000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
22
arch/powerpc/include/asm/arch-mpc83xx/clock.h
Normal file
22
arch/powerpc/include/asm/arch-mpc83xx/clock.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* (C) Copyright 2018
|
||||
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_POWERPC_CLOCK_H
|
||||
#define __ASM_POWERPC_CLOCK_H
|
||||
|
||||
/* Make fsl_esdhc driver happy */
|
||||
enum mxc_clock {
|
||||
MXC_ESDHC_CLK,
|
||||
};
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
uint mxc_get_clock(int clk)
|
||||
{
|
||||
return gd->arch.sdhc_clk;
|
||||
}
|
||||
#endif /* __ASM_POWERPC_CLOCK_H */
|
||||
@ -6,10 +6,10 @@
|
||||
/*
|
||||
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
|
||||
*/
|
||||
#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \
|
||||
defined(CONFIG_MPC8315)
|
||||
#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
|
||||
defined(CONFIG_ARCH_MPC8315)
|
||||
#define MPC83XX_GPIO_CTRLRS 1
|
||||
#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
#define MPC83XX_GPIO_CTRLRS 2
|
||||
#else
|
||||
#define MPC83XX_GPIO_CTRLRS 0
|
||||
@ -17,7 +17,15 @@
|
||||
|
||||
#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
|
||||
|
||||
struct mpc8xxx_gpio_plat {
|
||||
ulong addr;
|
||||
unsigned long size;
|
||||
uint ngpios;
|
||||
};
|
||||
|
||||
#ifndef DM_GPIO
|
||||
void mpc83xx_gpio_init_f(void);
|
||||
void mpc83xx_gpio_init_r(void);
|
||||
#endif /* DM_GPIO */
|
||||
|
||||
#endif /* MPC83XX_GPIO_H_ */
|
||||
|
||||
@ -43,10 +43,10 @@ void lbc_sdram_init(void);
|
||||
#define BR_MSEL 0x000000E0
|
||||
#define BR_MSEL_SHIFT 5
|
||||
#define BR_MS_GPCM 0x00000000 /* GPCM */
|
||||
#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
|
||||
#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
|
||||
#define BR_MS_FCM 0x00000020 /* FCM */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
|
||||
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
|
||||
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
|
||||
#elif defined(CONFIG_MPC85xx)
|
||||
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
|
||||
@ -54,7 +54,7 @@ void lbc_sdram_init(void);
|
||||
#define BR_MS_UPMA 0x00000080 /* UPMA */
|
||||
#define BR_MS_UPMB 0x000000A0 /* UPMB */
|
||||
#define BR_MS_UPMC 0x000000C0 /* UPMC */
|
||||
#if !defined(CONFIG_MPC834x)
|
||||
#if !defined(CONFIG_ARCH_MPC834X)
|
||||
#define BR_ATOM 0x0000000C
|
||||
#define BR_ATOM_SHIFT 2
|
||||
#endif
|
||||
@ -67,7 +67,7 @@ void lbc_sdram_init(void);
|
||||
#define UPMB 1
|
||||
#define UPMC 2
|
||||
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
|
||||
#else
|
||||
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
|
||||
@ -133,7 +133,7 @@ void lbc_sdram_init(void);
|
||||
#define OR_GPCM_EHTR_SHIFT 1
|
||||
#define OR_GPCM_EHTR_CLEAR 0x00000000
|
||||
#define OR_GPCM_EHTR_SET 0x00000002
|
||||
#if !defined(CONFIG_MPC8308)
|
||||
#if !defined(CONFIG_ARCH_MPC8308)
|
||||
#define OR_GPCM_EAD 0x00000001
|
||||
#define OR_GPCM_EAD_SHIFT 0
|
||||
#endif
|
||||
@ -428,14 +428,17 @@ void lbc_sdram_init(void);
|
||||
#define LSDMR_BSMA1516 (3 << (31 - 10))
|
||||
#define LSDMR_BSMA1617 (4 << (31 - 10))
|
||||
#define LSDMR_RFCR5 (3 << (31 - 16))
|
||||
#define LSDMR_RFCR8 (5 << (31 - 16))
|
||||
#define LSDMR_RFCR16 (7 << (31 - 16))
|
||||
#define LSDMR_PRETOACT3 (3 << (31 - 19))
|
||||
#define LSDMR_PRETOACT6 (5 << (31 - 19))
|
||||
#define LSDMR_PRETOACT7 (7 << (31 - 19))
|
||||
#define LSDMR_ACTTORW3 (3 << (31 - 22))
|
||||
#define LSDMR_ACTTORW7 (7 << (31 - 22))
|
||||
#define LSDMR_ACTTORW6 (6 << (31 - 22))
|
||||
#define LSDMR_BL8 (1 << (31 - 23))
|
||||
#define LSDMR_WRC2 (2 << (31 - 27))
|
||||
#define LSDMR_WRC3 (3 << (31 - 27))
|
||||
#define LSDMR_WRC4 (0 << (31 - 27))
|
||||
#define LSDMR_BUFCMD (1 << (31 - 29))
|
||||
#define LSDMR_CL3 (3 << (31 - 31))
|
||||
|
||||
@ -35,35 +35,35 @@ struct arch_global_data {
|
||||
#else
|
||||
/* There are other clocks in the MPC83XX */
|
||||
u32 csb_clk;
|
||||
# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
|
||||
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
||||
u32 tsec1_clk;
|
||||
u32 tsec2_clk;
|
||||
u32 usbdr_clk;
|
||||
# elif defined(CONFIG_MPC8309)
|
||||
# elif defined(CONFIG_ARCH_MPC8309)
|
||||
u32 usbdr_clk;
|
||||
# endif
|
||||
# if defined(CONFIG_MPC834x)
|
||||
# if defined(CONFIG_ARCH_MPC834X)
|
||||
u32 usbmph_clk;
|
||||
# endif /* CONFIG_MPC834x */
|
||||
# if defined(CONFIG_MPC8315)
|
||||
# endif /* CONFIG_ARCH_MPC834X */
|
||||
# if defined(CONFIG_ARCH_MPC8315)
|
||||
u32 tdm_clk;
|
||||
# endif
|
||||
u32 core_clk;
|
||||
u32 enc_clk;
|
||||
u32 lbiu_clk;
|
||||
u32 lclk_clk;
|
||||
# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
u32 pciexp1_clk;
|
||||
u32 pciexp2_clk;
|
||||
# endif
|
||||
# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
|
||||
# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
|
||||
u32 sata_clk;
|
||||
# endif
|
||||
# if defined(CONFIG_MPC8360)
|
||||
# if defined(CONFIG_ARCH_MPC8360)
|
||||
u32 mem_sec_clk;
|
||||
# endif /* CONFIG_MPC8360 */
|
||||
# endif /* CONFIG_ARCH_MPC8360 */
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
|
||||
|
||||
@ -59,12 +59,12 @@ typedef struct sysconf83xx {
|
||||
u32 obir; /* Output Buffer Impedance Register */
|
||||
u8 res8[0xC];
|
||||
u32 pecr1; /* PCI Express control register 1 */
|
||||
#if defined(CONFIG_MPC830x)
|
||||
#if defined(CONFIG_ARCH_MPC830X)
|
||||
u32 sdhccr; /* eSDHC Control Registers for MPC830x */
|
||||
#else
|
||||
u32 pecr2; /* PCI Express control register 2 */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8309)
|
||||
#if defined(CONFIG_ARCH_MPC8309)
|
||||
u32 can_dbg_ctrl;
|
||||
u32 res9a;
|
||||
u32 gpr1;
|
||||
@ -604,7 +604,7 @@ typedef struct serdes83xx {
|
||||
* On Chip ROM
|
||||
*/
|
||||
typedef struct rom83xx {
|
||||
#if defined(CONFIG_MPC8309)
|
||||
#if defined(CONFIG_ARCH_MPC8309)
|
||||
u8 mem[0x8000];
|
||||
#else
|
||||
u8 mem[0x10000];
|
||||
@ -625,7 +625,7 @@ typedef struct tdmdmac83xx {
|
||||
u8 fixme[0x2000];
|
||||
} tdmdmac83xx_t;
|
||||
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -666,7 +666,7 @@ typedef struct immap {
|
||||
u8 res7[0xC0000];
|
||||
} immap_t;
|
||||
|
||||
#ifndef CONFIG_MPC834x
|
||||
#ifndef CONFIG_ARCH_MPC834X
|
||||
#ifdef CONFIG_HAS_FSL_MPH_USB
|
||||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
|
||||
@ -679,7 +679,7 @@ typedef struct immap {
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_MPC8313)
|
||||
#elif defined(CONFIG_ARCH_MPC8313)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -714,7 +714,7 @@ typedef struct immap {
|
||||
u8 res7[0xC0000];
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
|
||||
#elif defined(CONFIG_ARCH_MPC8315)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -729,8 +729,8 @@ typedef struct immap {
|
||||
gpio83xx_t gpio[1]; /* General purpose I/O module */
|
||||
u8 res0[0x1300];
|
||||
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
||||
fsl_i2c_t i2c[2]; /* I2C Controllers */
|
||||
u8 res1[0x1300];
|
||||
fsl_i2c_t i2c[1]; /* I2C Controllers */
|
||||
u8 res1[0x1400];
|
||||
duart83xx_t duart[2]; /* DUART */
|
||||
u8 res2[0x900];
|
||||
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
|
||||
@ -759,7 +759,43 @@ typedef struct immap {
|
||||
u8 res12[0x1CF00];
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_MPC837x)
|
||||
#elif defined(CONFIG_ARCH_MPC8308)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
|
||||
rtclk83xx_t pit; /* Periodic Interval Timer */
|
||||
gtm83xx_t gtm[1]; /* Global Timers Module */
|
||||
u8 res0[0x100];
|
||||
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
|
||||
arbiter83xx_t arbiter; /* System Arbiter Registers */
|
||||
reset83xx_t reset; /* Reset Module */
|
||||
clk83xx_t clk; /* System Clock Module */
|
||||
pmc83xx_t pmc; /* Power Management Control Module */
|
||||
gpio83xx_t gpio[1]; /* General purpose I/O module */
|
||||
u8 res1[0x1300];
|
||||
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
||||
fsl_i2c_t i2c[2]; /* I2C Controllers */
|
||||
u8 res2[0x1300];
|
||||
duart83xx_t duart[2]; /* DUART */
|
||||
u8 res3[0x900];
|
||||
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
|
||||
u8 res4[0x1000];
|
||||
spi8xxx_t spi; /* Serial Peripheral Interface */
|
||||
u8 res5[0x1000];
|
||||
pex83xx_t pciexp[1]; /* PCI Express Controller */
|
||||
u8 res6[0x19000];
|
||||
usb83xx_t usb[1]; /* USB DR Controller */
|
||||
tsec83xx_t tsec[2];
|
||||
u8 res7[0x6000];
|
||||
tdmdmac83xx_t tdmdmac; /* TDM DMAC */
|
||||
sdhc83xx_t sdhc; /* SDHC Controller */
|
||||
u8 res8[0xb4000];
|
||||
serdes83xx_t serdes[1]; /* SerDes Registers */
|
||||
u8 res9[0x1CF00];
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_ARCH_MPC837X)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -803,7 +839,7 @@ typedef struct immap {
|
||||
rom83xx_t rom; /* On Chip ROM */
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8360)
|
||||
#elif defined(CONFIG_ARCH_MPC8360)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -843,7 +879,7 @@ typedef struct immap {
|
||||
u8 qe[0x100000]; /* QE block */
|
||||
} immap_t;
|
||||
|
||||
#elif defined(CONFIG_MPC832x)
|
||||
#elif defined(CONFIG_ARCH_MPC832X)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -879,7 +915,7 @@ typedef struct immap {
|
||||
u8 res8[0xC0000];
|
||||
u8 qe[0x100000]; /* QE block */
|
||||
} immap_t;
|
||||
#elif defined(CONFIG_MPC8309)
|
||||
#elif defined(CONFIG_ARCH_MPC8309)
|
||||
typedef struct immap {
|
||||
sysconf83xx_t sysconf; /* System configuration */
|
||||
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
||||
@ -946,7 +982,7 @@ typedef struct immap {
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC83xx_USB1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
|
||||
#if defined(CONFIG_MPC834x)
|
||||
#if defined(CONFIG_ARCH_MPC834X)
|
||||
#define CONFIG_SYS_MPC83xx_USB2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
|
||||
#endif
|
||||
|
||||
@ -10,11 +10,11 @@
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#if defined(CONFIG_MPC8308) || \
|
||||
defined(CONFIG_MPC8313) || \
|
||||
defined(CONFIG_MPC8315) || \
|
||||
defined(CONFIG_MPC834x) || \
|
||||
defined(CONFIG_MPC837x)
|
||||
#if defined(CONFIG_ARCH_MPC8308) || \
|
||||
defined(CONFIG_ARCH_MPC8313) || \
|
||||
defined(CONFIG_ARCH_MPC8315) || \
|
||||
defined(CONFIG_ARCH_MPC834X) || \
|
||||
defined(CONFIG_ARCH_MPC837X)
|
||||
|
||||
typedef struct spi8xxx {
|
||||
u8 res0[0x20]; /* 0x0-0x01f reserved */
|
||||
|
||||
@ -1203,127 +1203,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* what kind of prep workstation we are */
|
||||
extern int _prep_type;
|
||||
/*
|
||||
* This is used to identify the board type from a given PReP board
|
||||
* vendor. Board revision is also made available.
|
||||
*/
|
||||
extern unsigned char ucSystemType;
|
||||
extern unsigned char ucBoardRev;
|
||||
extern unsigned char ucBoardRevMaj, ucBoardRevMin;
|
||||
|
||||
struct task_struct;
|
||||
void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
|
||||
void release_thread(struct task_struct *);
|
||||
|
||||
/*
|
||||
* Create a new kernel thread.
|
||||
*/
|
||||
extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
|
||||
|
||||
/*
|
||||
* Bus types
|
||||
*/
|
||||
#define EISA_bus 0
|
||||
#define EISA_bus__is_a_macro /* for versions in ksyms.c */
|
||||
#define MCA_bus 0
|
||||
#define MCA_bus__is_a_macro /* for versions in ksyms.c */
|
||||
|
||||
/* Lazy FPU handling on uni-processor */
|
||||
extern struct task_struct *last_task_used_math;
|
||||
extern struct task_struct *last_task_used_altivec;
|
||||
|
||||
/*
|
||||
* this is the minimum allowable io space due to the location
|
||||
* of the io areas on prep (first one at 0x80000000) but
|
||||
* as soon as I get around to remapping the io areas with the BATs
|
||||
* to match the mac we can raise this. -- Cort
|
||||
*/
|
||||
#define TASK_SIZE (0x80000000UL)
|
||||
|
||||
/* This decides where the kernel will search for a free chunk of vm
|
||||
* space during mmap's.
|
||||
*/
|
||||
#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
|
||||
|
||||
typedef struct {
|
||||
unsigned long seg;
|
||||
} mm_segment_t;
|
||||
|
||||
struct thread_struct {
|
||||
unsigned long ksp; /* Kernel stack pointer */
|
||||
unsigned long wchan; /* Event task is sleeping on */
|
||||
struct pt_regs *regs; /* Pointer to saved register state */
|
||||
mm_segment_t fs; /* for get_fs() validation */
|
||||
void *pgdir; /* root of page-table tree */
|
||||
signed long last_syscall;
|
||||
double fpr[32]; /* Complete floating point set */
|
||||
unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
|
||||
unsigned long fpscr; /* Floating point status */
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
vector128 vr[32]; /* Complete AltiVec set */
|
||||
vector128 vscr; /* AltiVec status */
|
||||
unsigned long vrsave;
|
||||
#endif /* CONFIG_ALTIVEC */
|
||||
};
|
||||
|
||||
#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
|
||||
|
||||
#define INIT_THREAD { \
|
||||
INIT_SP, /* ksp */ \
|
||||
0, /* wchan */ \
|
||||
(struct pt_regs *)INIT_SP - 1, /* regs */ \
|
||||
KERNEL_DS, /*fs*/ \
|
||||
swapper_pg_dir, /* pgdir */ \
|
||||
0, /* last_syscall */ \
|
||||
{0}, 0, 0 \
|
||||
}
|
||||
|
||||
/*
|
||||
* Note: the vm_start and vm_end fields here should *not*
|
||||
* be in kernel space. (Could vm_end == vm_start perhaps?)
|
||||
*/
|
||||
#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
|
||||
PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
|
||||
1, NULL, NULL }
|
||||
|
||||
/*
|
||||
* Return saved PC of a blocked thread. For now, this is the "user" PC
|
||||
*/
|
||||
static inline unsigned long thread_saved_pc(struct thread_struct *t)
|
||||
{
|
||||
return (t->regs) ? t->regs->nip : 0;
|
||||
}
|
||||
|
||||
#define copy_segments(tsk, mm) do { } while (0)
|
||||
#define release_segments(mm) do { } while (0)
|
||||
#define forget_segments() do { } while (0)
|
||||
|
||||
unsigned long get_wchan(struct task_struct *p);
|
||||
|
||||
#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
|
||||
|
||||
/*
|
||||
* NOTE! The task struct and the stack go together
|
||||
*/
|
||||
#define THREAD_SIZE (2*PAGE_SIZE)
|
||||
#define alloc_task_struct() \
|
||||
((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
|
||||
#define free_task_struct(p) free_pages((unsigned long)(p),1)
|
||||
#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
|
||||
|
||||
/* in process.c - for early bootup debug -- Cort */
|
||||
int ll_printk(const char *, ...);
|
||||
void ll_puts(const char *);
|
||||
|
||||
#define init_task (init_task_union.task)
|
||||
#define init_stack (init_task_union.stack)
|
||||
|
||||
/* In misc.c */
|
||||
void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
|
||||
|
||||
#ifndef CONFIG_CPU_MPC83XX
|
||||
int prt_83xx_rsr(void);
|
||||
|
||||
@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
|
||||
default "vme8349"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_CADDY2
|
||||
|
||||
config SYS_BOARD
|
||||
default "vme8349"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "esd"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "caddy2"
|
||||
|
||||
endif
|
||||
|
||||
@ -38,7 +38,7 @@ int dram_init(void)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main memory */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
|
||||
msize = spd_sdram();
|
||||
|
||||
@ -60,7 +60,7 @@ int dram_init(void)
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef VME_CADDY2
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
puts("Board: esd VME-CADDY/2\n");
|
||||
#else
|
||||
puts("Board: esd VME-CPU/8349\n");
|
||||
@ -69,7 +69,7 @@ int checkboard(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef VME_CADDY2
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
@ -102,7 +102,7 @@ int misc_init_r()
|
||||
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
|
||||
* and VME-CADDY/2) have different SDRAM configurations.
|
||||
*/
|
||||
#ifdef VME_CADDY2
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
#define SMALL_RAM 0xff
|
||||
#define LARGE_RAM 0x00
|
||||
#else
|
||||
@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = {
|
||||
SPD_VAL(0x7e, 0x1d), /* 63 */
|
||||
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
|
||||
SPD_VAL(0x00, 0x00), /* 72 */
|
||||
#ifdef VME_CADDY2
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
{ "vme-caddy/2 ram " }
|
||||
#else
|
||||
{ "vme-cpu/2 ram " }
|
||||
|
||||
@ -36,7 +36,7 @@ int pib_init(void)
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
#if defined(CONFIG_MPC832XEMDS)
|
||||
#if defined(CONFIG_TARGET_MPC832XEMDS)
|
||||
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
|
||||
#else
|
||||
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
|
||||
@ -55,7 +55,7 @@ int pib_init(void)
|
||||
|
||||
eieio();
|
||||
|
||||
#if defined(CONFIG_MPC832XEMDS)
|
||||
#if defined(CONFIG_TARGET_MPC832XEMDS)
|
||||
printf("PCI 32bit bus on PMC2 &PMC3\n");
|
||||
#else
|
||||
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
|
||||
@ -76,7 +76,7 @@ int pib_init(void)
|
||||
eieio();
|
||||
|
||||
printf("QOC3 ATM card on PMC0\n");
|
||||
#elif defined(CONFIG_MPC832XEMDS)
|
||||
#elif defined(CONFIG_TARGET_MPC832XEMDS)
|
||||
val8 = 0;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
val8 = 0xf7;
|
||||
|
||||
@ -33,7 +33,7 @@ static long fixed_sdram(void)
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
|
||||
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
|
||||
@ -61,7 +61,7 @@ static long fixed_sdram(void)
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
sync();
|
||||
|
||||
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
|
||||
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
if TARGET_MPC8313ERDB
|
||||
if TARGET_MPC8313ERDB_NOR
|
||||
|
||||
config SYS_BOARD
|
||||
default "mpc8313erdb"
|
||||
@ -7,6 +7,19 @@ config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "MPC8313ERDB"
|
||||
default "MPC8313ERDB_NOR"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_MPC8313ERDB_NAND
|
||||
|
||||
config SYS_BOARD
|
||||
default "mpc8313erdb"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "MPC8313ERDB_NAND"
|
||||
|
||||
endif
|
||||
|
||||
@ -47,7 +47,7 @@ static long fixed_sdram(void)
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
|
||||
|
||||
@ -57,12 +57,12 @@ static long fixed_sdram(void)
|
||||
*/
|
||||
__udelay(50000);
|
||||
|
||||
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#warning Chip select bounds is only configurable in 16MB increments
|
||||
#endif
|
||||
im->ddr.csbnds[0].csbnds =
|
||||
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
|
||||
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
|
||||
CSBNDS_EA);
|
||||
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
|
||||
|
||||
@ -109,8 +109,9 @@ int dram_init(void)
|
||||
msize = fixed_sdram();
|
||||
|
||||
/* Local Bus setup lbcr and mrtpr */
|
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
|
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
|
||||
lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
|
||||
/* LB refresh timer prescal, 266MHz/32 */
|
||||
lbc->mrtpr = 0x20000000;
|
||||
sync();
|
||||
|
||||
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
|
||||
|
||||
@ -4,3 +4,4 @@ S: Orphan (since 2018-05)
|
||||
F: board/freescale/mpc8315erdb/
|
||||
F: include/configs/MPC8315ERDB.h
|
||||
F: configs/MPC8315ERDB_defconfig
|
||||
F: configs/MPC8315ERDB_NANDSPL_defconfig
|
||||
|
||||
@ -44,7 +44,7 @@ static long fixed_sdram(void)
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
|
||||
|
||||
|
||||
@ -79,7 +79,7 @@ int dram_init(void)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
|
||||
msize = fixed_sdram();
|
||||
|
||||
|
||||
@ -98,7 +98,7 @@ int dram_init(void)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
|
||||
msize = fixed_sdram();
|
||||
|
||||
|
||||
@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
|
||||
default "MPC8349EMDS"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_MPC8349EMDS_SDRAM
|
||||
|
||||
config SYS_BOARD
|
||||
default "mpc8349emds"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "MPC8349EMDS_SDRAM"
|
||||
|
||||
endif
|
||||
|
||||
@ -4,3 +4,6 @@ S: Orphan (since 2018-05)
|
||||
F: board/freescale/mpc8349emds/
|
||||
F: include/configs/MPC8349EMDS.h
|
||||
F: configs/MPC8349EMDS_defconfig
|
||||
F: configs/MPC8349EMDS_SDRAM_defconfig
|
||||
F: configs/MPC8349EMDS_PCI64_defconfig
|
||||
F: configs/MPC8349EMDS_SLAVE_defconfig
|
||||
|
||||
@ -56,7 +56,7 @@ int dram_init(void)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#ifndef CONFIG_SYS_FSL_DDR2
|
||||
msize = spd_sdram() * 1024 * 1024;
|
||||
@ -91,7 +91,7 @@ int fixed_sdram(void)
|
||||
u32 ddr_size = msize << 20; /* DDR size in bytes */
|
||||
u32 ddr_size_log2 = __ilog2(ddr_size);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
|
||||
|
||||
#if (CONFIG_SYS_DDR_SIZE != 256)
|
||||
@ -112,12 +112,12 @@ int fixed_sdram(void)
|
||||
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
|
||||
#else
|
||||
|
||||
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#warning Chip select bounds is only configurable in 16MB increments
|
||||
#endif
|
||||
im->ddr.csbnds[2].csbnds =
|
||||
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
|
||||
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
|
||||
CSBNDS_EA_SHIFT) & CSBNDS_EA);
|
||||
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
|
||||
|
||||
@ -183,28 +183,36 @@ void sdram_init(void)
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile fsl_lbc_t *lbc = &immap->im_lbc;
|
||||
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
|
||||
|
||||
const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
|
||||
LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
|
||||
LSDMR_WRC3 | LSDMR_CL3;
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
|
||||
*/
|
||||
|
||||
/* setup mtrpt, lsrt and lbcr for LB bus */
|
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
|
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
|
||||
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
|
||||
lbc->lbcr = 0x00000000;
|
||||
/* LB refresh timer prescal, 266MHz/32 */
|
||||
lbc->mrtpr = 0x20000000;
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
lbc->lsrt = 0x32000000;
|
||||
asm("sync");
|
||||
|
||||
/*
|
||||
* Configure the SDRAM controller Machine Mode Register.
|
||||
*/
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
|
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
|
||||
/* 0x40636733; normal operation */
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
||||
|
||||
/* 0x68636733; precharge all the banks */
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
|
||||
asm("sync");
|
||||
*sdram_addr = 0xff;
|
||||
udelay(100);
|
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
|
||||
/* 0x48636733; auto refresh */
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
|
||||
asm("sync");
|
||||
/*1 times*/
|
||||
*sdram_addr = 0xff;
|
||||
@ -232,12 +240,13 @@ void sdram_init(void)
|
||||
udelay(100);
|
||||
|
||||
/* 0x58636733; mode register write operation */
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
|
||||
asm("sync");
|
||||
*sdram_addr = 0xff;
|
||||
udelay(100);
|
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
|
||||
/* 0x40636733; normal operation */
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
||||
asm("sync");
|
||||
*sdram_addr = 0xff;
|
||||
udelay(100);
|
||||
|
||||
@ -77,11 +77,11 @@ void pib_init(void)
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
#if defined(PCI_64BIT)
|
||||
#if defined(CONFIG_PCI_64BIT)
|
||||
val8 = 0xf4; /* PMC2:PCI1/64-bit */
|
||||
#elif defined(PCI_ALL_PCI1)
|
||||
#elif defined(CONFIG_PCI_ALL_PCI1)
|
||||
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
|
||||
#elif defined(PCI_ONE_PCI1)
|
||||
#elif defined(CONFIG_PCI_ONE_PCI1)
|
||||
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
|
||||
#else
|
||||
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
|
||||
@ -98,11 +98,11 @@ void pib_init(void)
|
||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
||||
asm("eieio");
|
||||
|
||||
#if defined(PCI_64BIT)
|
||||
#if defined(CONFIG_PCI_64BIT)
|
||||
printf("PCI1: 64-bit on PMC2\n");
|
||||
#elif defined(PCI_ALL_PCI1)
|
||||
#elif defined(CONFIG_PCI_ALL_PCI1)
|
||||
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
|
||||
#elif defined(PCI_ONE_PCI1)
|
||||
#elif defined(CONFIG_PCI_ONE_PCI1)
|
||||
printf("PCI1: 32-bit on PMC1\n");
|
||||
printf("PCI2: 32-bit on PMC2, PMC3\n");
|
||||
#else
|
||||
|
||||
@ -19,6 +19,9 @@
|
||||
#include <linux/libfdt.h>
|
||||
#endif
|
||||
|
||||
#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
|
||||
#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
@ -34,14 +37,14 @@ int fixed_sdram(void)
|
||||
|
||||
im->sysconf.ddrlaw[0].ar =
|
||||
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
|
||||
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
|
||||
#warning Chip select bounds is only configurable in 16MB increments
|
||||
#endif
|
||||
im->ddr.csbnds[0].csbnds =
|
||||
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
|
||||
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
||||
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
|
||||
CSBNDS_EA_SHIFT) & CSBNDS_EA);
|
||||
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
|
||||
|
||||
@ -129,7 +132,7 @@ int dram_init(void)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
msize = spd_sdram();
|
||||
#else
|
||||
@ -152,7 +155,7 @@ int dram_init(void)
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_MPC8349ITX
|
||||
#ifdef CONFIG_TARGET_MPC8349ITX
|
||||
puts("Board: Freescale MPC8349E-mITX\n");
|
||||
#else
|
||||
puts("Board: Freescale MPC8349E-mITX-GP\n");
|
||||
|
||||
@ -4,4 +4,5 @@ S: Orphan (since 2018-05)
|
||||
F: board/freescale/mpc837xemds/
|
||||
F: include/configs/MPC837XEMDS.h
|
||||
F: configs/MPC837XEMDS_defconfig
|
||||
F: configs/MPC837XEMDS_SLAVE_defconfig
|
||||
F: configs/MPC837XEMDS_HOST_defconfig
|
||||
|
||||
@ -252,7 +252,7 @@ int fixed_sdram(void)
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
|
||||
#if (CONFIG_SYS_DDR_SIZE != 512)
|
||||
|
||||
@ -4,3 +4,4 @@ S: Maintained
|
||||
F: board/freescale/mpc837xerdb/
|
||||
F: include/configs/MPC837XERDB.h
|
||||
F: configs/MPC837XERDB_defconfig
|
||||
F: configs/MPC837XERDB_SLAVE_defconfig
|
||||
|
||||
@ -95,7 +95,7 @@ int fixed_sdram(void)
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
|
||||
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
|
||||
|
||||
@ -5,16 +5,13 @@
|
||||
|
||||
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
|
||||
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
|
||||
obj-$(CONFIG_IO) += miiphybb.o
|
||||
obj-$(CONFIG_IO64) += miiphybb.o
|
||||
obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
|
||||
obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
|
||||
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
|
||||
obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
|
||||
obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
|
||||
obj-$(CONFIG_STRIDER) += fanctrl.o
|
||||
obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
|
||||
obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
|
||||
obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
|
||||
obj-$(CONFIG_STRIDER_CON) += osd.o
|
||||
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
|
||||
obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
|
||||
|
||||
ifdef CONFIG_OSD
|
||||
obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
|
||||
@ -174,3 +176,5 @@ out:
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
|
||||
/* Chrontel CH7301C DVI Transmitter */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
@ -61,3 +63,5 @@ int ch7301_probe(unsigned screen, bool power)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -10,34 +10,53 @@
|
||||
|
||||
#include <gdsys_fpga.h>
|
||||
|
||||
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
#include <dm.h>
|
||||
#include <misc.h>
|
||||
#include <regmap.h>
|
||||
#include <board.h>
|
||||
|
||||
#include "../../../drivers/misc/gdsys_soc.h"
|
||||
#include "../../../drivers/misc/gdsys_ioep.h"
|
||||
#include "../../../drivers/misc/ihs_fpga.h"
|
||||
|
||||
const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
|
||||
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
enum status_print_type {
|
||||
STATUS_LOUD = 0,
|
||||
STATUS_SILENT = 1,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
enum {
|
||||
STATE_TX_PACKET_BUILDING = 1<<0,
|
||||
STATE_TX_TRANSMITTING = 1<<1,
|
||||
STATE_TX_BUFFER_FULL = 1<<2,
|
||||
STATE_TX_ERR = 1<<3,
|
||||
STATE_RECEIVE_TIMEOUT = 1<<4,
|
||||
STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
|
||||
STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
|
||||
STATE_RX_DIST_ERR = 1<<7,
|
||||
STATE_RX_LENGTH_ERR = 1<<8,
|
||||
STATE_RX_FRAME_CTR_ERR = 1<<9,
|
||||
STATE_RX_FCS_ERR = 1<<10,
|
||||
STATE_RX_PACKET_DROPPED = 1<<11,
|
||||
STATE_RX_DATA_LAST = 1<<12,
|
||||
STATE_RX_DATA_FIRST = 1<<13,
|
||||
STATE_RX_DATA_AVAILABLE = 1<<15,
|
||||
STATE_TX_PACKET_BUILDING = BIT(0),
|
||||
STATE_TX_TRANSMITTING = BIT(1),
|
||||
STATE_TX_BUFFER_FULL = BIT(2),
|
||||
STATE_TX_ERR = BIT(3),
|
||||
STATE_RECEIVE_TIMEOUT = BIT(4),
|
||||
STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
|
||||
STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
|
||||
STATE_RX_DIST_ERR = BIT(7),
|
||||
STATE_RX_LENGTH_ERR = BIT(8),
|
||||
STATE_RX_FRAME_CTR_ERR = BIT(9),
|
||||
STATE_RX_FCS_ERR = BIT(10),
|
||||
STATE_RX_PACKET_DROPPED = BIT(11),
|
||||
STATE_RX_DATA_LAST = BIT(12),
|
||||
STATE_RX_DATA_FIRST = BIT(13),
|
||||
STATE_RX_DATA_AVAILABLE = BIT(15),
|
||||
};
|
||||
|
||||
enum {
|
||||
CTRL_PROC_RECEIVE_ENABLE = 1<<12,
|
||||
CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
|
||||
IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
|
||||
IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
|
||||
IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
|
||||
IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
|
||||
};
|
||||
|
||||
enum {
|
||||
IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
|
||||
IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
|
||||
IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
|
||||
IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
|
||||
CTRL_PROC_RECEIVE_ENABLE = BIT(12),
|
||||
CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
|
||||
};
|
||||
|
||||
struct io_generic_packet {
|
||||
@ -47,12 +66,17 @@ struct io_generic_packet {
|
||||
u8 bc;
|
||||
u16 packet_length;
|
||||
} __attribute__((__packed__));
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
unsigned long long rx_ctr;
|
||||
unsigned long long tx_ctr;
|
||||
unsigned long long err_ctr;
|
||||
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
struct udevice *dev;
|
||||
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
static void io_check_status(unsigned int fpga, u16 status, bool silent)
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
static void io_check_status(uint fpga, u16 status, enum status_print_type type)
|
||||
{
|
||||
u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
|
||||
STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
|
||||
@ -66,7 +90,7 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent)
|
||||
err_ctr++;
|
||||
FPGA_SET_REG(fpga, ep.rx_tx_status, status);
|
||||
|
||||
if (silent)
|
||||
if (type == STATUS_SILENT)
|
||||
return;
|
||||
|
||||
if (status & STATE_RX_PACKET_DROPPED)
|
||||
@ -84,10 +108,42 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent)
|
||||
if (status & STATE_TX_ERR)
|
||||
printf("TX_ERR\n");
|
||||
}
|
||||
|
||||
static void io_send(unsigned int fpga, unsigned int size)
|
||||
#else
|
||||
static void io_check_status(struct udevice *dev, enum status_print_type type)
|
||||
{
|
||||
unsigned int k;
|
||||
u16 status = 0;
|
||||
int ret;
|
||||
|
||||
ret = misc_call(dev, 0, NULL, 0, &status, 0);
|
||||
if (!ret)
|
||||
return;
|
||||
|
||||
err_ctr++;
|
||||
|
||||
if (type != STATUS_LOUD)
|
||||
return;
|
||||
|
||||
if (status & STATE_RX_PACKET_DROPPED)
|
||||
printf("RX_PACKET_DROPPED, status %04x\n", status);
|
||||
|
||||
if (status & STATE_RX_DIST_ERR)
|
||||
printf("RX_DIST_ERR\n");
|
||||
if (status & STATE_RX_LENGTH_ERR)
|
||||
printf("RX_LENGTH_ERR\n");
|
||||
if (status & STATE_RX_FRAME_CTR_ERR)
|
||||
printf("RX_FRAME_CTR_ERR\n");
|
||||
if (status & STATE_RX_FCS_ERR)
|
||||
printf("RX_FCS_ERR\n");
|
||||
|
||||
if (status & STATE_TX_ERR)
|
||||
printf("TX_ERR\n");
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
static void io_send(uint fpga, uint size)
|
||||
{
|
||||
uint k;
|
||||
struct io_generic_packet packet = {
|
||||
.source_address = 1,
|
||||
.packet_type = 1,
|
||||
@ -106,10 +162,31 @@ static void io_send(unsigned int fpga, unsigned int size)
|
||||
|
||||
tx_ctr++;
|
||||
}
|
||||
|
||||
static void io_receive(unsigned int fpga)
|
||||
#else
|
||||
static void io_send(struct udevice *dev, uint size)
|
||||
{
|
||||
uint k;
|
||||
u16 buffer[HEADER_WORDS + 128];
|
||||
struct io_generic_packet header = {
|
||||
.source_address = 1,
|
||||
.packet_type = 1,
|
||||
.packet_length = size,
|
||||
};
|
||||
const uint words = (size + 1) / 2;
|
||||
|
||||
memcpy(buffer, &header, 2 * HEADER_WORDS);
|
||||
for (k = 0; k < words; ++k)
|
||||
buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
|
||||
|
||||
misc_write(dev, 0, buffer, HEADER_WORDS + words);
|
||||
|
||||
tx_ctr++;
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
static void io_receive(uint fpga)
|
||||
{
|
||||
unsigned int k = 0;
|
||||
u16 rx_tx_status;
|
||||
|
||||
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
|
||||
@ -123,17 +200,25 @@ static void io_receive(unsigned int fpga)
|
||||
FPGA_GET_REG(fpga, ep.receive_data, &rx);
|
||||
|
||||
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
|
||||
|
||||
++k;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void io_receive(struct udevice *dev)
|
||||
{
|
||||
u16 buffer[HEADER_WORDS + 128];
|
||||
|
||||
static void io_reflect(unsigned int fpga)
|
||||
if (!misc_read(dev, 0, buffer, 0))
|
||||
rx_ctr++;
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
static void io_reflect(uint fpga)
|
||||
{
|
||||
u16 buffer[128];
|
||||
|
||||
unsigned int k = 0;
|
||||
unsigned int n;
|
||||
uint k = 0;
|
||||
uint n;
|
||||
u16 rx_tx_status;
|
||||
|
||||
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
|
||||
@ -157,7 +242,22 @@ static void io_reflect(unsigned int fpga)
|
||||
|
||||
tx_ctr++;
|
||||
}
|
||||
#else
|
||||
static void io_reflect(struct udevice *dev)
|
||||
{
|
||||
u16 buffer[HEADER_WORDS + 128];
|
||||
struct io_generic_packet *header;
|
||||
|
||||
if (misc_read(dev, 0, buffer, 0))
|
||||
return;
|
||||
|
||||
header = (struct io_generic_packet *)&buffer;
|
||||
|
||||
misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
/*
|
||||
* FPGA io-endpoint reflector
|
||||
*
|
||||
@ -166,8 +266,8 @@ static void io_reflect(unsigned int fpga)
|
||||
*/
|
||||
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned int fpga;
|
||||
unsigned int rate = 0;
|
||||
uint fpga;
|
||||
uint rate = 0;
|
||||
unsigned long long last_seen = 0;
|
||||
|
||||
if (argc < 2)
|
||||
@ -181,10 +281,10 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
if (argc > 2)
|
||||
rate = simple_strtoul(argv[2], NULL, 10);
|
||||
|
||||
/* enable receive path */
|
||||
/* Enable receive path */
|
||||
FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
|
||||
|
||||
/* set device address to dummy 1*/
|
||||
/* Set device address to dummy 1*/
|
||||
FPGA_SET_REG(fpga, ep.device_address, 1);
|
||||
|
||||
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
|
||||
@ -196,7 +296,7 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
FPGA_GET_REG(fpga, top_interrupt, &top_int);
|
||||
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
|
||||
|
||||
io_check_status(fpga, rx_tx_status, true);
|
||||
io_check_status(fpga, rx_tx_status, STATUS_SILENT);
|
||||
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
|
||||
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
|
||||
io_reflect(fpga);
|
||||
@ -214,19 +314,71 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
/*
|
||||
* FPGA io-endpoint reflector
|
||||
*
|
||||
* Syntax:
|
||||
* ioreflect {reportrate}
|
||||
*/
|
||||
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
struct udevice *fpga;
|
||||
struct regmap *map;
|
||||
uint rate = 0;
|
||||
unsigned long long last_seen = 0;
|
||||
|
||||
if (!dev) {
|
||||
printf("No device selected\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
gdsys_soc_get_fpga(dev, &fpga);
|
||||
regmap_init_mem(dev_ofnode(dev), &map);
|
||||
|
||||
/* Enable receive path */
|
||||
misc_set_enabled(dev, true);
|
||||
|
||||
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
|
||||
|
||||
while (1) {
|
||||
uint top_int;
|
||||
|
||||
ihs_fpga_get(map, top_interrupt, &top_int);
|
||||
io_check_status(dev, STATUS_SILENT);
|
||||
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
|
||||
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
|
||||
io_reflect(dev);
|
||||
|
||||
if (rate) {
|
||||
if (!(tx_ctr % rate) && (tx_ctr != last_seen))
|
||||
printf("refl %llu, err %llu\n", tx_ctr,
|
||||
err_ctr);
|
||||
last_seen = tx_ctr;
|
||||
}
|
||||
|
||||
if (ctrlc())
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#define DISP_LINE_LEN 16
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
/*
|
||||
* FPGA io-endpoint looptest
|
||||
*
|
||||
* Syntax:
|
||||
* ioloop {fpga} {size} {rate}
|
||||
*/
|
||||
#define DISP_LINE_LEN 16
|
||||
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned int fpga;
|
||||
unsigned int size;
|
||||
unsigned int rate = 0;
|
||||
uint fpga;
|
||||
uint size;
|
||||
uint rate = 0;
|
||||
|
||||
if (argc < 3)
|
||||
return CMD_RET_USAGE;
|
||||
@ -262,7 +414,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
FPGA_GET_REG(fpga, top_interrupt, &top_int);
|
||||
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
|
||||
|
||||
io_check_status(fpga, rx_tx_status, false);
|
||||
io_check_status(fpga, rx_tx_status, STATUS_LOUD);
|
||||
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
|
||||
io_send(fpga, size);
|
||||
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
|
||||
@ -273,7 +425,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
break;
|
||||
udelay(1000000 / rate);
|
||||
if (!(tx_ctr % rate))
|
||||
printf("d %lld, tx %llu, rx %llu, err %llu\n",
|
||||
printf("d %llu, tx %llu, rx %llu, err %llu\n",
|
||||
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
|
||||
err_ctr);
|
||||
}
|
||||
@ -281,7 +433,122 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
/*
|
||||
* FPGA io-endpoint looptest
|
||||
*
|
||||
* Syntax:
|
||||
* ioloop {size} {rate}
|
||||
*/
|
||||
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
uint size;
|
||||
uint rate = 0;
|
||||
struct udevice *fpga;
|
||||
struct regmap *map;
|
||||
|
||||
if (!dev) {
|
||||
printf("No device selected\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
gdsys_soc_get_fpga(dev, &fpga);
|
||||
regmap_init_mem(dev_ofnode(dev), &map);
|
||||
|
||||
if (argc < 2)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
/*
|
||||
* packet size is specified since argc > 1
|
||||
*/
|
||||
size = simple_strtoul(argv[2], NULL, 10);
|
||||
|
||||
/*
|
||||
* If another parameter, it is the test rate in packets per second.
|
||||
*/
|
||||
if (argc > 2)
|
||||
rate = simple_strtoul(argv[3], NULL, 10);
|
||||
|
||||
/* Enable receive path */
|
||||
misc_set_enabled(dev, true);
|
||||
|
||||
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
|
||||
|
||||
while (1) {
|
||||
uint top_int;
|
||||
|
||||
if (ctrlc())
|
||||
break;
|
||||
|
||||
ihs_fpga_get(map, top_interrupt, &top_int);
|
||||
|
||||
io_check_status(dev, STATUS_LOUD);
|
||||
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
|
||||
io_send(dev, size);
|
||||
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
|
||||
io_receive(dev);
|
||||
|
||||
if (rate) {
|
||||
udelay(1000000 / rate);
|
||||
if (!(tx_ctr % rate))
|
||||
printf("d %llu, tx %llu, rx %llu, err %llu\n",
|
||||
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
|
||||
err_ctr);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
struct udevice *ioep = NULL;
|
||||
struct udevice *board;
|
||||
char name[8];
|
||||
int ret;
|
||||
|
||||
if (board_get(&board))
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
if (argc > 1) {
|
||||
int i = simple_strtoul(argv[1], NULL, 10);
|
||||
|
||||
snprintf(name, sizeof(name), "ioep%d", i);
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
|
||||
|
||||
if (ret || !ioep) {
|
||||
printf("Invalid IOEP %d\n", i);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
dev = ioep;
|
||||
} else {
|
||||
int i = 0;
|
||||
|
||||
while (1) {
|
||||
snprintf(name, sizeof(name), "ioep%d", i);
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
|
||||
|
||||
if (ret || !ioep)
|
||||
break;
|
||||
|
||||
printf("IOEP %d:\t%s\n", i++, ioep->name);
|
||||
}
|
||||
|
||||
if (dev)
|
||||
printf("\nSelected IOEP: %s\n", dev->name);
|
||||
else
|
||||
puts("\nNo IOEP selected.\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
U_BOOT_CMD(
|
||||
ioloop, 4, 0, do_ioloop,
|
||||
"fpga io-endpoint looptest",
|
||||
@ -293,3 +560,22 @@ U_BOOT_CMD(
|
||||
"fpga io-endpoint reflector",
|
||||
"fpga reportrate"
|
||||
);
|
||||
#else
|
||||
U_BOOT_CMD(
|
||||
ioloop, 3, 0, do_ioloop,
|
||||
"fpga io-endpoint looptest",
|
||||
"packetsize [packets/sec]"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
ioreflect, 2, 0, do_ioreflect,
|
||||
"fpga io-endpoint reflector",
|
||||
"reportrate"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
iodev, 2, 0, do_iodev,
|
||||
"fpga io-endpoint listing/selection",
|
||||
"[ioep device to select]"
|
||||
);
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
|
||||
/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
@ -155,3 +157,5 @@ int dp501_probe(unsigned screen, bool power)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
|
||||
@ -29,3 +31,5 @@ void init_fan_controller(u8 addr)
|
||||
val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
|
||||
i2c_reg_write(addr, FAN_CONFIG, val);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <gdsys_fpga.h>
|
||||
|
||||
@ -22,3 +24,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include <gdsys_fpga.h>
|
||||
#else
|
||||
#include <fdtdec.h>
|
||||
#include <dm.h>
|
||||
#include <regmap.h>
|
||||
#endif
|
||||
|
||||
@ -28,7 +29,7 @@ static inline u16 read_reg(struct udevice *fpga, uint base, uint addr)
|
||||
struct regmap *map;
|
||||
u8 *ptr;
|
||||
|
||||
regmap_init_mem(fpga, &map);
|
||||
regmap_init_mem(dev_ofnode(fpga), &map);
|
||||
ptr = regmap_get_range(map, 0);
|
||||
|
||||
return in_le16((u16 *)(ptr + base + addr));
|
||||
@ -40,7 +41,7 @@ static inline void write_reg(struct udevice *fpga, uint base, uint addr,
|
||||
struct regmap *map;
|
||||
u8 *ptr;
|
||||
|
||||
regmap_init_mem(fpga, &map);
|
||||
regmap_init_mem(dev_ofnode(fpga), &map);
|
||||
ptr = regmap_get_range(map, 0);
|
||||
|
||||
out_le16((u16 *)(ptr + base + addr), val);
|
||||
|
||||
@ -4,233 +4,586 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <gdsys_fpga.h>
|
||||
|
||||
enum {
|
||||
UNITTYPE_MAIN_SERVER = 0,
|
||||
UNITTYPE_MAIN_USER = 1,
|
||||
UNITTYPE_VIDEO_SERVER = 2,
|
||||
UNITTYPE_VIDEO_USER = 3,
|
||||
enum pcb_video_type {
|
||||
PCB_DVI_SL,
|
||||
PCB_DP_165MPIX,
|
||||
PCB_DP_300MPIX,
|
||||
PCB_HDMI,
|
||||
PCB_DP_1_2,
|
||||
PCB_HDMI_2_0,
|
||||
};
|
||||
|
||||
enum {
|
||||
UNITTYPEPCB_DVI = 0,
|
||||
UNITTYPEPCB_DP_165 = 1,
|
||||
UNITTYPEPCB_DP_300 = 2,
|
||||
UNITTYPEPCB_HDMI = 3,
|
||||
enum pcb_transmission_type {
|
||||
PCB_CAT_1G,
|
||||
PCB_FIBER_3G,
|
||||
PCB_CAT_10G,
|
||||
PCB_FIBER_10G,
|
||||
};
|
||||
|
||||
enum {
|
||||
COMPRESSION_NONE = 0,
|
||||
COMPRESSION_TYPE_1 = 1,
|
||||
COMPRESSION_TYPE_1_2 = 3,
|
||||
COMPRESSION_TYPE_1_2_3 = 7,
|
||||
enum carrier_speed {
|
||||
CARRIER_SPEED_1G,
|
||||
CARRIER_SPEED_3G,
|
||||
CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
|
||||
CARRIER_SPEED_10G,
|
||||
};
|
||||
|
||||
enum {
|
||||
AUDIO_NONE = 0,
|
||||
AUDIO_TX = 1,
|
||||
AUDIO_RX = 2,
|
||||
AUDIO_RXTX = 3,
|
||||
enum ram_config {
|
||||
RAM_DDR2_32BIT_295MBPS,
|
||||
RAM_DDR3_32BIT_590MBPS,
|
||||
RAM_DDR3_48BIT_590MBPS,
|
||||
RAM_DDR3_64BIT_1800MBPS,
|
||||
RAM_DDR3_48BIT_1800MBPS,
|
||||
};
|
||||
|
||||
enum {
|
||||
SYSCLK_147456 = 0,
|
||||
enum sysclock {
|
||||
SYSCLK_147456,
|
||||
};
|
||||
|
||||
enum {
|
||||
RAM_DDR2_32 = 0,
|
||||
RAM_DDR3_32 = 1,
|
||||
RAM_DDR3_48 = 2,
|
||||
struct fpga_versions {
|
||||
bool video_channel;
|
||||
bool con_side;
|
||||
enum pcb_video_type pcb_video_type;
|
||||
enum pcb_transmission_type pcb_transmission_type;
|
||||
unsigned int hw_version;
|
||||
};
|
||||
|
||||
enum {
|
||||
CARRIER_SPEED_1G = 0,
|
||||
CARRIER_SPEED_2_5G = 1,
|
||||
struct fpga_features {
|
||||
u8 video_channels;
|
||||
u8 carriers;
|
||||
enum carrier_speed carrier_speed;
|
||||
enum ram_config ram_config;
|
||||
enum sysclock sysclock;
|
||||
|
||||
bool pcm_tx;
|
||||
bool pcm_rx;
|
||||
bool spdif_tx;
|
||||
bool spdif_rx;
|
||||
bool usb2;
|
||||
bool rs232;
|
||||
bool compression_type1;
|
||||
bool compression_type2;
|
||||
bool compression_type3;
|
||||
bool interlace;
|
||||
bool osd;
|
||||
bool compression_pipes;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
|
||||
|
||||
static int get_versions(unsigned int fpga, struct fpga_versions *versions)
|
||||
{
|
||||
enum {
|
||||
VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
|
||||
VERSIONS_FPGA_CON_SIDE = BIT(13),
|
||||
VERSIONS_FPGA_SC = BIT(14),
|
||||
VERSIONS_PCB_CON = BIT(9),
|
||||
VERSIONS_PCB_SC = BIT(8),
|
||||
VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
|
||||
VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
|
||||
VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
|
||||
VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
|
||||
VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
|
||||
VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
|
||||
VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
|
||||
VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
|
||||
VERSIONS_HW_VER_MASK = 0xf << 0,
|
||||
};
|
||||
u16 raw_versions;
|
||||
|
||||
memset(versions, 0, sizeof(struct fpga_versions));
|
||||
|
||||
FPGA_GET_REG(fpga, versions, &raw_versions);
|
||||
|
||||
versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
|
||||
versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
|
||||
|
||||
switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
|
||||
case VERSIONS_PCB_VIDEO_DP_1_2:
|
||||
versions->pcb_video_type = PCB_DP_1_2;
|
||||
break;
|
||||
|
||||
case VERSIONS_PCB_VIDEO_HDMI_2_0:
|
||||
versions->pcb_video_type = PCB_HDMI_2_0;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
|
||||
case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
|
||||
versions->pcb_transmission_type = PCB_FIBER_10G;
|
||||
break;
|
||||
|
||||
case VERSIONS_PCB_TRANSMISSION_CAT_10G:
|
||||
versions->pcb_transmission_type = PCB_CAT_10G;
|
||||
break;
|
||||
|
||||
case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
|
||||
versions->pcb_transmission_type = PCB_FIBER_3G;
|
||||
break;
|
||||
|
||||
case VERSIONS_PCB_TRANSMISSION_CAT_1G:
|
||||
versions->pcb_transmission_type = PCB_CAT_1G;
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_features(unsigned int fpga, struct fpga_features *features)
|
||||
{
|
||||
enum {
|
||||
FEATURE_SPDIF_RX = BIT(15),
|
||||
FEATURE_SPDIF_TX = BIT(14),
|
||||
FEATURE_PCM_RX = BIT(13),
|
||||
FEATURE_PCM_TX = BIT(12),
|
||||
FEATURE_RAM_MASK = GENMASK(11, 8),
|
||||
FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
|
||||
FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
|
||||
FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
|
||||
FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
|
||||
FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
|
||||
FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
|
||||
FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
|
||||
FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
|
||||
FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
|
||||
FEATURE_CARRIERS_MASK = GENMASK(5, 4),
|
||||
FEATURE_CARRIERS_0 = 0x0 << 4,
|
||||
FEATURE_CARRIERS_1 = 0x1 << 4,
|
||||
FEATURE_CARRIERS_2 = 0x2 << 4,
|
||||
FEATURE_CARRIERS_4 = 0x3 << 4,
|
||||
FEATURE_USB2 = BIT(3),
|
||||
FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
|
||||
FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
|
||||
FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
|
||||
FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
|
||||
FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
|
||||
};
|
||||
|
||||
enum {
|
||||
EXT_FEATURE_OSD = BIT(15),
|
||||
EXT_FEATURE_ETHERNET = BIT(9),
|
||||
EXT_FEATURE_INTERLACE = BIT(8),
|
||||
EXT_FEATURE_RS232 = BIT(7),
|
||||
EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
|
||||
EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
|
||||
EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
|
||||
EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
|
||||
EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
|
||||
EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
|
||||
EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
|
||||
};
|
||||
|
||||
u16 raw_features;
|
||||
u16 raw_extended_features;
|
||||
|
||||
memset(features, 0, sizeof(struct fpga_features));
|
||||
|
||||
FPGA_GET_REG(fpga, fpga_features, &raw_features);
|
||||
FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
|
||||
|
||||
switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
|
||||
case FEATURE_VIDEOCHANNELS_0:
|
||||
features->video_channels = 0;
|
||||
break;
|
||||
|
||||
case FEATURE_VIDEOCHANNELS_1:
|
||||
features->video_channels = 1;
|
||||
break;
|
||||
|
||||
case FEATURE_VIDEOCHANNELS_1_1:
|
||||
case FEATURE_VIDEOCHANNELS_2:
|
||||
features->video_channels = 2;
|
||||
break;
|
||||
};
|
||||
|
||||
switch (raw_features & FEATURE_CARRIERS_MASK) {
|
||||
case FEATURE_CARRIERS_0:
|
||||
features->carriers = 0;
|
||||
break;
|
||||
|
||||
case FEATURE_CARRIERS_1:
|
||||
features->carriers = 1;
|
||||
break;
|
||||
|
||||
case FEATURE_CARRIERS_2:
|
||||
features->carriers = 2;
|
||||
break;
|
||||
|
||||
case FEATURE_CARRIERS_4:
|
||||
features->carriers = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
|
||||
case FEATURE_CARRIER_SPEED_1G:
|
||||
features->carrier_speed = CARRIER_SPEED_1G;
|
||||
break;
|
||||
case FEATURE_CARRIER_SPEED_2_5G:
|
||||
features->carrier_speed = CARRIER_SPEED_2_5G;
|
||||
break;
|
||||
case FEATURE_CARRIER_SPEED_10G:
|
||||
features->carrier_speed = CARRIER_SPEED_10G;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (raw_features & FEATURE_RAM_MASK) {
|
||||
case FEATURE_RAM_DDR2_32BIT_295MBPS:
|
||||
features->ram_config = RAM_DDR2_32BIT_295MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_32BIT_590MBPS:
|
||||
features->ram_config = RAM_DDR3_32BIT_590MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_48BIT_590MBPS:
|
||||
features->ram_config = RAM_DDR3_48BIT_590MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_64BIT_1800MBPS:
|
||||
features->ram_config = RAM_DDR3_64BIT_1800MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_48BIT_1800MBPS:
|
||||
features->ram_config = RAM_DDR3_48BIT_1800MBPS;
|
||||
break;
|
||||
}
|
||||
|
||||
features->pcm_tx = raw_features & FEATURE_PCM_TX;
|
||||
features->pcm_rx = raw_features & FEATURE_PCM_RX;
|
||||
features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
|
||||
features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
|
||||
features->usb2 = raw_features & FEATURE_USB2;
|
||||
features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
|
||||
features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
|
||||
features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
|
||||
features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
|
||||
features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
|
||||
features->osd = raw_extended_features & EXT_FEATURE_OSD;
|
||||
features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static int get_versions(unsigned int fpga, struct fpga_versions *versions)
|
||||
{
|
||||
enum {
|
||||
/* HW version encoding is a mess, leave it for the moment */
|
||||
VERSIONS_HW_VER_MASK = 0xf << 0,
|
||||
VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
|
||||
VERSIONS_SFP = BIT(5),
|
||||
VERSIONS_VIDEO_MASK = 0x7 << 6,
|
||||
VERSIONS_VIDEO_DVI = 0x0 << 6,
|
||||
VERSIONS_VIDEO_DP_165 = 0x1 << 6,
|
||||
VERSIONS_VIDEO_DP_300 = 0x2 << 6,
|
||||
VERSIONS_VIDEO_HDMI = 0x3 << 6,
|
||||
VERSIONS_UT_MASK = 0xf << 12,
|
||||
VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
|
||||
VERSIONS_UT_MAIN_USER = 0x1 << 12,
|
||||
VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
|
||||
VERSIONS_UT_VIDEO_USER = 0x3 << 12,
|
||||
};
|
||||
u16 raw_versions;
|
||||
|
||||
memset(versions, 0, sizeof(struct fpga_versions));
|
||||
|
||||
FPGA_GET_REG(fpga, versions, &raw_versions);
|
||||
|
||||
switch (raw_versions & VERSIONS_UT_MASK) {
|
||||
case VERSIONS_UT_MAIN_SERVER:
|
||||
versions->video_channel = false;
|
||||
versions->con_side = false;
|
||||
break;
|
||||
|
||||
case VERSIONS_UT_MAIN_USER:
|
||||
versions->video_channel = false;
|
||||
versions->con_side = true;
|
||||
break;
|
||||
|
||||
case VERSIONS_UT_VIDEO_SERVER:
|
||||
versions->video_channel = true;
|
||||
versions->con_side = false;
|
||||
break;
|
||||
|
||||
case VERSIONS_UT_VIDEO_USER:
|
||||
versions->video_channel = true;
|
||||
versions->con_side = true;
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
switch (raw_versions & VERSIONS_VIDEO_MASK) {
|
||||
case VERSIONS_VIDEO_DVI:
|
||||
versions->pcb_video_type = PCB_DVI_SL;
|
||||
break;
|
||||
|
||||
case VERSIONS_VIDEO_DP_165:
|
||||
versions->pcb_video_type = PCB_DP_165MPIX;
|
||||
break;
|
||||
|
||||
case VERSIONS_VIDEO_DP_300:
|
||||
versions->pcb_video_type = PCB_DP_300MPIX;
|
||||
break;
|
||||
|
||||
case VERSIONS_VIDEO_HDMI:
|
||||
versions->pcb_video_type = PCB_HDMI;
|
||||
break;
|
||||
}
|
||||
|
||||
versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
|
||||
|
||||
if (raw_versions & VERSIONS_SFP)
|
||||
versions->pcb_transmission_type = PCB_FIBER_3G;
|
||||
else
|
||||
versions->pcb_transmission_type = PCB_CAT_1G;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_features(unsigned int fpga, struct fpga_features *features)
|
||||
{
|
||||
enum {
|
||||
FEATURE_CARRIER_SPEED_2_5 = BIT(4),
|
||||
FEATURE_RAM_MASK = 0x7 << 5,
|
||||
FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
|
||||
FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
|
||||
FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
|
||||
FEATURE_PCM_AUDIO_TX = BIT(9),
|
||||
FEATURE_PCM_AUDIO_RX = BIT(10),
|
||||
FEATURE_OSD = BIT(11),
|
||||
FEATURE_USB20 = BIT(12),
|
||||
FEATURE_COMPRESSION_MASK = 7 << 13,
|
||||
FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
|
||||
FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
|
||||
FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
|
||||
};
|
||||
|
||||
enum {
|
||||
EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
|
||||
EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
|
||||
EXTENDED_FEATURE_RS232 = BIT(2),
|
||||
EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
|
||||
EXTENDED_FEATURE_INTERLACE = BIT(4),
|
||||
};
|
||||
|
||||
u16 raw_features;
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
u16 raw_extended_features;
|
||||
#endif
|
||||
|
||||
memset(features, 0, sizeof(struct fpga_features));
|
||||
|
||||
FPGA_GET_REG(fpga, fpga_features, &raw_features);
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
|
||||
#endif
|
||||
|
||||
features->video_channels = raw_features & 0x3;
|
||||
features->carriers = (raw_features >> 2) & 0x3;
|
||||
|
||||
features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
|
||||
? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
|
||||
|
||||
switch (raw_features & FEATURE_RAM_MASK) {
|
||||
case FEATURE_RAM_DDR2_32BIT:
|
||||
features->ram_config = RAM_DDR2_32BIT_295MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_32BIT:
|
||||
features->ram_config = RAM_DDR3_32BIT_590MBPS;
|
||||
break;
|
||||
|
||||
case FEATURE_RAM_DDR3_48BIT:
|
||||
features->ram_config = RAM_DDR3_48BIT_590MBPS;
|
||||
break;
|
||||
}
|
||||
|
||||
features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
|
||||
features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
|
||||
features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
|
||||
#endif
|
||||
|
||||
features->usb2 = raw_features & FEATURE_USB20;
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
|
||||
#endif
|
||||
|
||||
features->compression_type1 = false;
|
||||
features->compression_type2 = false;
|
||||
features->compression_type3 = false;
|
||||
switch (raw_features & FEATURE_COMPRESSION_MASK) {
|
||||
case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
|
||||
features->compression_type3 = true;
|
||||
case FEATURE_COMPRESSION_TYPE1_TYPE2:
|
||||
features->compression_type2 = true;
|
||||
case FEATURE_COMPRESSION_TYPE1:
|
||||
features->compression_type1 = true;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
|
||||
#endif
|
||||
features->osd = raw_features & FEATURE_OSD;
|
||||
#ifdef GDSYS_LEGACY_DRIVERS
|
||||
features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
bool ioep_fpga_has_osd(unsigned int fpga)
|
||||
{
|
||||
u16 fpga_features;
|
||||
unsigned feature_osd;
|
||||
struct fpga_features features;
|
||||
|
||||
FPGA_GET_REG(0, fpga_features, &fpga_features);
|
||||
feature_osd = fpga_features & (1<<11);
|
||||
get_features(fpga, &features);
|
||||
|
||||
return feature_osd;
|
||||
return features.osd;
|
||||
}
|
||||
|
||||
void ioep_fpga_print_info(unsigned int fpga)
|
||||
{
|
||||
u16 versions;
|
||||
u16 fpga_version;
|
||||
u16 fpga_features;
|
||||
unsigned unit_type;
|
||||
unsigned unit_type_pcb_video;
|
||||
unsigned feature_compression;
|
||||
unsigned feature_osd;
|
||||
unsigned feature_audio;
|
||||
unsigned feature_sysclock;
|
||||
unsigned feature_ramconfig;
|
||||
unsigned feature_carrier_speed;
|
||||
unsigned feature_carriers;
|
||||
unsigned feature_video_channels;
|
||||
struct fpga_versions versions;
|
||||
struct fpga_features features;
|
||||
|
||||
FPGA_GET_REG(fpga, versions, &versions);
|
||||
FPGA_GET_REG(fpga, fpga_version, &fpga_version);
|
||||
FPGA_GET_REG(fpga, fpga_features, &fpga_features);
|
||||
get_versions(fpga, &versions);
|
||||
get_features(fpga, &features);
|
||||
|
||||
unit_type = (versions & 0xf000) >> 12;
|
||||
unit_type_pcb_video = (versions & 0x01c0) >> 6;
|
||||
feature_compression = (fpga_features & 0xe000) >> 13;
|
||||
feature_osd = fpga_features & (1<<11);
|
||||
feature_audio = (fpga_features & 0x0600) >> 9;
|
||||
feature_sysclock = (fpga_features & 0x0180) >> 7;
|
||||
feature_ramconfig = (fpga_features & 0x0060) >> 5;
|
||||
feature_carrier_speed = fpga_features & (1<<4);
|
||||
feature_carriers = (fpga_features & 0x000c) >> 2;
|
||||
feature_video_channels = fpga_features & 0x0003;
|
||||
|
||||
switch (unit_type) {
|
||||
case UNITTYPE_MAIN_SERVER:
|
||||
case UNITTYPE_MAIN_USER:
|
||||
printf("Mainchannel");
|
||||
break;
|
||||
|
||||
case UNITTYPE_VIDEO_SERVER:
|
||||
case UNITTYPE_VIDEO_USER:
|
||||
if (versions.video_channel)
|
||||
printf("Videochannel");
|
||||
break;
|
||||
else
|
||||
printf("Mainchannel");
|
||||
|
||||
default:
|
||||
printf("UnitType %d(not supported)", unit_type);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (unit_type) {
|
||||
case UNITTYPE_MAIN_SERVER:
|
||||
case UNITTYPE_VIDEO_SERVER:
|
||||
if (versions.con_side)
|
||||
printf(" User");
|
||||
else
|
||||
printf(" Server");
|
||||
|
||||
// FIXME
|
||||
#if 0
|
||||
if (versions & (1<<4))
|
||||
printf(" UC");
|
||||
break;
|
||||
#endif
|
||||
|
||||
case UNITTYPE_MAIN_USER:
|
||||
case UNITTYPE_VIDEO_USER:
|
||||
printf(" User");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (versions & (1<<5))
|
||||
printf(" Fiber");
|
||||
else
|
||||
switch(versions.pcb_transmission_type) {
|
||||
case PCB_CAT_1G:
|
||||
case PCB_CAT_10G:
|
||||
printf(" CAT");
|
||||
break;
|
||||
case PCB_FIBER_3G:
|
||||
case PCB_FIBER_10G:
|
||||
printf(" Fiber");
|
||||
break;
|
||||
};
|
||||
|
||||
switch (unit_type_pcb_video) {
|
||||
case UNITTYPEPCB_DVI:
|
||||
switch (versions.pcb_video_type) {
|
||||
case PCB_DVI_SL:
|
||||
printf(" DVI,");
|
||||
break;
|
||||
|
||||
case UNITTYPEPCB_DP_165:
|
||||
case PCB_DP_165MPIX:
|
||||
printf(" DP 165MPix/s,");
|
||||
break;
|
||||
|
||||
case UNITTYPEPCB_DP_300:
|
||||
case PCB_DP_300MPIX:
|
||||
printf(" DP 300MPix/s,");
|
||||
break;
|
||||
|
||||
case UNITTYPEPCB_HDMI:
|
||||
case PCB_HDMI:
|
||||
printf(" HDMI,");
|
||||
break;
|
||||
case PCB_DP_1_2:
|
||||
printf(" DP 1.2,");
|
||||
break;
|
||||
case PCB_HDMI_2_0:
|
||||
printf(" HDMI 2.0,");
|
||||
break;
|
||||
}
|
||||
|
||||
printf(" FPGA V %d.%02d\n features:",
|
||||
printf(" FPGA V %d.%02d\n features: ",
|
||||
fpga_version / 100, fpga_version % 100);
|
||||
|
||||
if (!features.compression_type1 &&
|
||||
!features.compression_type2 &&
|
||||
!features.compression_type3)
|
||||
printf("no compression, ");
|
||||
|
||||
switch (feature_compression) {
|
||||
case COMPRESSION_NONE:
|
||||
printf(" no compression");
|
||||
break;
|
||||
if (features.compression_type1)
|
||||
printf("type1, ");
|
||||
|
||||
case COMPRESSION_TYPE_1:
|
||||
printf(" compression type1(delta)");
|
||||
break;
|
||||
if (features.compression_type2)
|
||||
printf("type2, ");
|
||||
|
||||
case COMPRESSION_TYPE_1_2:
|
||||
printf(" compression type1(delta), type2(inline)");
|
||||
break;
|
||||
if (features.compression_type3)
|
||||
printf("type3, ");
|
||||
|
||||
case COMPRESSION_TYPE_1_2_3:
|
||||
printf(" compression type1(delta), type2(inline), type3(intempo)");
|
||||
break;
|
||||
printf("%sosd", features.osd ? "" : "no ");
|
||||
|
||||
default:
|
||||
printf(" compression %d(not supported)", feature_compression);
|
||||
break;
|
||||
}
|
||||
if (features.pcm_rx && features.pcm_tx)
|
||||
printf(", pcm rx+tx");
|
||||
else if(features.pcm_rx)
|
||||
printf(", pcm rx");
|
||||
else if(features.pcm_tx)
|
||||
printf(", pcm tx");
|
||||
|
||||
printf(", %sosd", feature_osd ? "" : "no ");
|
||||
|
||||
switch (feature_audio) {
|
||||
case AUDIO_NONE:
|
||||
printf(", no audio");
|
||||
break;
|
||||
|
||||
case AUDIO_TX:
|
||||
printf(", audio tx");
|
||||
break;
|
||||
|
||||
case AUDIO_RX:
|
||||
printf(", audio rx");
|
||||
break;
|
||||
|
||||
case AUDIO_RXTX:
|
||||
printf(", audio rx+tx");
|
||||
break;
|
||||
|
||||
default:
|
||||
printf(", audio %d(not supported)", feature_audio);
|
||||
break;
|
||||
}
|
||||
if (features.spdif_rx && features.spdif_tx)
|
||||
printf(", spdif rx+tx");
|
||||
else if(features.spdif_rx)
|
||||
printf(", spdif rx");
|
||||
else if(features.spdif_tx)
|
||||
printf(", spdif tx");
|
||||
|
||||
puts(",\n ");
|
||||
|
||||
switch (feature_sysclock) {
|
||||
switch (features.sysclock) {
|
||||
case SYSCLK_147456:
|
||||
printf("clock 147.456 MHz");
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("clock %d(not supported)", feature_sysclock);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (feature_ramconfig) {
|
||||
case RAM_DDR2_32:
|
||||
switch (features.ram_config) {
|
||||
case RAM_DDR2_32BIT_295MBPS:
|
||||
printf(", RAM 32 bit DDR2");
|
||||
break;
|
||||
|
||||
case RAM_DDR3_32:
|
||||
case RAM_DDR3_32BIT_590MBPS:
|
||||
printf(", RAM 32 bit DDR3");
|
||||
break;
|
||||
|
||||
case RAM_DDR3_48:
|
||||
case RAM_DDR3_48BIT_590MBPS:
|
||||
case RAM_DDR3_48BIT_1800MBPS:
|
||||
printf(", RAM 48 bit DDR3");
|
||||
break;
|
||||
|
||||
default:
|
||||
printf(", RAM %d(not supported)", feature_ramconfig);
|
||||
case RAM_DDR3_64BIT_1800MBPS:
|
||||
printf(", RAM 64 bit DDR3");
|
||||
break;
|
||||
}
|
||||
|
||||
printf(", %d carrier(s) %s", feature_carriers,
|
||||
feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
|
||||
printf(", %d carrier(s)", features.carriers);
|
||||
|
||||
printf(", %d video channel(s)\n", feature_video_channels);
|
||||
switch(features.carrier_speed) {
|
||||
case CARRIER_SPEED_1G:
|
||||
printf(", 1Gbit/s");
|
||||
break;
|
||||
case CARRIER_SPEED_3G:
|
||||
printf(", 3Gbit/s");
|
||||
break;
|
||||
case CARRIER_SPEED_10G:
|
||||
printf(", 10Gbit/s");
|
||||
break;
|
||||
}
|
||||
|
||||
printf(", %d video channel(s)\n", features.video_channels);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -4,6 +4,8 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
@ -134,3 +136,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
|
||||
@ -1,127 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
struct io_bb_pinset {
|
||||
int mdio;
|
||||
int mdc;
|
||||
};
|
||||
|
||||
static int io_bb_mii_init(struct bb_miiphy_bus *bus)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
|
||||
{
|
||||
struct io_bb_pinset *pins = bus->priv;
|
||||
|
||||
out_be32((void *)GPIO0_TCR,
|
||||
in_be32((void *)GPIO0_TCR) | pins->mdio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
|
||||
{
|
||||
struct io_bb_pinset *pins = bus->priv;
|
||||
|
||||
out_be32((void *)GPIO0_TCR,
|
||||
in_be32((void *)GPIO0_TCR) & ~pins->mdio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
|
||||
{
|
||||
struct io_bb_pinset *pins = bus->priv;
|
||||
|
||||
if (v)
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) | pins->mdio);
|
||||
else
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) & ~pins->mdio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
||||
{
|
||||
struct io_bb_pinset *pins = bus->priv;
|
||||
|
||||
*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
|
||||
{
|
||||
struct io_bb_pinset *pins = bus->priv;
|
||||
|
||||
if (v)
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) | pins->mdc);
|
||||
else
|
||||
out_be32((void *)GPIO0_OR,
|
||||
in_be32((void *)GPIO0_OR) & ~pins->mdc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int io_bb_delay(struct bb_miiphy_bus *bus)
|
||||
{
|
||||
udelay(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct io_bb_pinset io_bb_pinsets[] = {
|
||||
{
|
||||
.mdio = CONFIG_SYS_MDIO_PIN,
|
||||
.mdc = CONFIG_SYS_MDC_PIN,
|
||||
},
|
||||
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
|
||||
{
|
||||
.mdio = CONFIG_SYS_MDIO1_PIN,
|
||||
.mdc = CONFIG_SYS_MDC1_PIN,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
||||
{
|
||||
.name = CONFIG_SYS_GBIT_MII_BUSNAME,
|
||||
.init = io_bb_mii_init,
|
||||
.mdio_active = io_bb_mdio_active,
|
||||
.mdio_tristate = io_bb_mdio_tristate,
|
||||
.set_mdio = io_bb_set_mdio,
|
||||
.get_mdio = io_bb_get_mdio,
|
||||
.set_mdc = io_bb_set_mdc,
|
||||
.delay = io_bb_delay,
|
||||
.priv = &io_bb_pinsets[0],
|
||||
},
|
||||
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
|
||||
{
|
||||
.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
|
||||
.init = io_bb_mii_init,
|
||||
.mdio_active = io_bb_mdio_active,
|
||||
.mdio_tristate = io_bb_mdio_tristate,
|
||||
.set_mdio = io_bb_set_mdio,
|
||||
.get_mdio = io_bb_get_mdio,
|
||||
.set_mdc = io_bb_set_mdc,
|
||||
.delay = io_bb_delay,
|
||||
.priv = &io_bb_pinsets[1],
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
|
||||
sizeof(bb_miiphy_buses[0]);
|
||||
@ -4,6 +4,8 @@
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
@ -497,3 +499,5 @@ U_BOOT_CMD(
|
||||
"size_x(max. " __stringify(MAX_X_CHARS)
|
||||
") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
|
||||
);
|
||||
|
||||
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|
||||
@ -45,8 +45,6 @@ struct mii_setupcmd fixup_88e1518[] = {
|
||||
{ MIICMD_SET, 16, 0x214d },
|
||||
{ MIICMD_SET, 17, 0xcc0c },
|
||||
{ MIICMD_SET, 16, 0x2159 },
|
||||
{ MIICMD_SET, 22, 0x00fb },
|
||||
{ MIICMD_SET, 7, 0xc00d },
|
||||
{ MIICMD_SET, 22, 0x0000 },
|
||||
};
|
||||
|
||||
|
||||
@ -4,6 +4,35 @@ config GDSYS_LEGACY_OSD_CMDS
|
||||
Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
|
||||
gdsys devices.
|
||||
|
||||
config GDSYS_LEGACY_DRIVERS
|
||||
bool
|
||||
help
|
||||
Enable the gdsys legacy drivers under board/gdsys/common. If this
|
||||
option is not set, all relevant DM drivers must be configured for the
|
||||
device in question.
|
||||
|
||||
config SYS_FPGA0_BASE
|
||||
hex
|
||||
default E0600000
|
||||
help
|
||||
The base address of the first FPGA's register map.
|
||||
|
||||
config SYS_FPGA0_SIZE
|
||||
hex
|
||||
default 1
|
||||
help
|
||||
The base address of the first FPGA's register map.
|
||||
|
||||
config SYS_FPGA1_BASE
|
||||
hex
|
||||
help
|
||||
The base address of the second FPGA's register map.
|
||||
|
||||
config SYS_FPGA1_SIZE
|
||||
hex
|
||||
help
|
||||
The base address of the second FPGA's register map.
|
||||
|
||||
if TARGET_HRCON
|
||||
|
||||
config SYS_BOARD
|
||||
@ -18,6 +47,9 @@ config SYS_CONFIG_NAME
|
||||
config GDSYS_LEGACY_OSD_CMDS
|
||||
default y
|
||||
|
||||
config GDSYS_LEGACY_DRIVERS
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_STRIDER
|
||||
@ -33,9 +65,60 @@ config SYS_CONFIG_NAME
|
||||
|
||||
config GDSYS_LEGACY_OSD_CMDS
|
||||
default y
|
||||
|
||||
config GDSYS_LEGACY_DRIVERS
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_GAZERBEAM
|
||||
|
||||
config SYS_BOARD
|
||||
default "mpc8308"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "gdsys"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "gazerbeam"
|
||||
|
||||
config SYS_FPGA1_BASE
|
||||
default E0700000
|
||||
|
||||
config SYS_FPGA1_SIZE
|
||||
default 1
|
||||
|
||||
config GDSYS_LEGACY_OSD_CMDS
|
||||
default y
|
||||
endif
|
||||
|
||||
if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
|
||||
|
||||
choice
|
||||
prompt "FPGA flavor selection"
|
||||
|
||||
config SYS_FPGA_FLAVOR_LEGACY
|
||||
bool "Legacy flavor"
|
||||
help
|
||||
This enables support for the gdsys pre-Gazerbeam FPGA memory layout.
|
||||
|
||||
config SYS_FPGA_FLAVOR_GAZERBEAM
|
||||
bool "Gazerbeam flavor"
|
||||
help
|
||||
This enables support for the gdsys FPGA memory layout of the
|
||||
Gazerbeam board.
|
||||
|
||||
endchoice
|
||||
|
||||
config EXTENDED_FEATURES
|
||||
bool "FPGA extended features"
|
||||
depends on GDSYS_LEGACY_DRIVERS
|
||||
help
|
||||
Enable support for the extended features field of the IHS FPGA.
|
||||
|
||||
config CMD_IOLOOP
|
||||
bool "Enable 'ioloop' and 'ioreflect' commands"
|
||||
help
|
||||
These commands provide FPGA tests.
|
||||
|
||||
endif
|
||||
|
||||
@ -6,7 +6,9 @@ F: include/configs/hrcon.h
|
||||
F: configs/hrcon_defconfig
|
||||
F: configs/hrcon_dh_defconfig
|
||||
F: include/configs/strider.h
|
||||
F: configs/strider_defconfig
|
||||
F: configs/strider_cpu_defconfig
|
||||
F: configs/strider_cpu_dp_defconfig
|
||||
F: configs/strider_con_defconfig
|
||||
F: configs/strider_con_dp_defconfig
|
||||
F: configs/gazerbeam_defconfig
|
||||
|
||||
@ -4,5 +4,6 @@
|
||||
# Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
||||
|
||||
obj-y := mpc8308.o sdram.o
|
||||
obj-$(CONFIG_HRCON) += hrcon.o
|
||||
obj-$(CONFIG_STRIDER) += strider.o
|
||||
obj-$(CONFIG_TARGET_HRCON) += hrcon.o
|
||||
obj-$(CONFIG_TARGET_STRIDER) += strider.o
|
||||
obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
|
||||
|
||||
179
board/gdsys/mpc8308/gazerbeam.c
Normal file
179
board/gdsys/mpc8308/gazerbeam.c
Normal file
@ -0,0 +1,179 @@
|
||||
/*
|
||||
* (C) Copyright 2015
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <board.h>
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <miiphy.h>
|
||||
#include <misc.h>
|
||||
#include <tpm-v1.h>
|
||||
#include <video_osd.h>
|
||||
|
||||
#include "../common/ihs_mdio.h"
|
||||
#include "../../../drivers/board/gazerbeam.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct ihs_mdio_info ihs_mdio_info[] = {
|
||||
{ .fpga = NULL, .name = "ihs0", .base = 0x58 },
|
||||
{ .fpga = NULL, .name = "ihs1", .base = 0x58 },
|
||||
};
|
||||
|
||||
static int get_tpm(struct udevice **devp)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = uclass_first_device_err(UCLASS_TPM, devp);
|
||||
if (rc) {
|
||||
printf("Could not find TPM (ret=%d)\n", rc);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
struct udevice *board;
|
||||
struct udevice *serdes;
|
||||
int mc = 0;
|
||||
int con = 0;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
|
||||
/* Initialize serdes */
|
||||
uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
|
||||
|
||||
if (board_detect(board))
|
||||
puts("Device information detection failed.\n");
|
||||
|
||||
board_get_int(board, BOARD_MULTICHANNEL, &mc);
|
||||
board_get_int(board, BOARD_VARIANT, &con);
|
||||
|
||||
if (mc == 2 || mc == 1)
|
||||
dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
|
||||
|
||||
if (mc == 4) {
|
||||
dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
|
||||
dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
|
||||
dev_enable_by_path("/fpga1bus");
|
||||
}
|
||||
|
||||
if (mc == 2 || con == VAR_CON) {
|
||||
dev_enable_by_path("/fpga0bus/fpga0_video1");
|
||||
dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
|
||||
dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
|
||||
}
|
||||
|
||||
if (con == VAR_CON) {
|
||||
dev_enable_by_path("/fpga0bus/fpga0_video0");
|
||||
dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
|
||||
dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
struct udevice *board;
|
||||
char *s = env_get("serial#");
|
||||
int mc = 0;
|
||||
int con = 0;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
|
||||
board_get_int(board, BOARD_MULTICHANNEL, &mc);
|
||||
board_get_int(board, BOARD_VARIANT, &con);
|
||||
|
||||
puts("Board: Gazerbeam ");
|
||||
printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
|
||||
printf("%s", con == VAR_CON ? "CON" : "CPU");
|
||||
|
||||
if (s) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void display_osd_info(struct udevice *osd,
|
||||
struct video_osd_info *osd_info)
|
||||
{
|
||||
printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
|
||||
osd->name, osd_info->major_version, osd_info->minor_version,
|
||||
osd_info->width, osd_info->height);
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
int fpga_hw_rev = 0;
|
||||
int i;
|
||||
struct udevice *board;
|
||||
struct udevice *osd;
|
||||
struct video_osd_info osd_info;
|
||||
struct udevice *tpm;
|
||||
int ret;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
|
||||
if (board) {
|
||||
int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
|
||||
|
||||
if (res)
|
||||
printf("Could not determind FPGA HW revision (res = %d)\n", res);
|
||||
}
|
||||
|
||||
env_set_ulong("fpga_hw_rev", fpga_hw_rev);
|
||||
|
||||
ret = get_tpm(&tpm);
|
||||
if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
|
||||
tpm_continue_self_test(tpm)) {
|
||||
printf("TPM init failed\n");
|
||||
}
|
||||
|
||||
if (fpga_hw_rev >= 4) {
|
||||
for (i = 0; i < 4; i++) {
|
||||
struct udevice *rxaui;
|
||||
char name[8];
|
||||
|
||||
snprintf(name, sizeof(name), "rxaui%d", i);
|
||||
/* Disable RXAUI polarity inversion */
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
|
||||
if (!ret)
|
||||
misc_set_enabled(rxaui, false);
|
||||
}
|
||||
}
|
||||
|
||||
for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
|
||||
osd;
|
||||
uclass_next_device(&osd)) {
|
||||
video_osd_get_info(osd, &osd_info);
|
||||
display_osd_info(osd, &osd_info);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
fdt_fixup_esdhc(blob, bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -35,11 +35,11 @@
|
||||
#define MAX_MUX_CHANNELS 2
|
||||
|
||||
enum {
|
||||
MCFPGA_DONE = 1 << 0,
|
||||
MCFPGA_INIT_N = 1 << 1,
|
||||
MCFPGA_PROGRAM_N = 1 << 2,
|
||||
MCFPGA_UPDATE_ENABLE_N = 1 << 3,
|
||||
MCFPGA_RESET_N = 1 << 4,
|
||||
MCFPGA_DONE = BIT(0),
|
||||
MCFPGA_INIT_N = BIT(1),
|
||||
MCFPGA_PROGRAM_N = BIT(2),
|
||||
MCFPGA_UPDATE_ENABLE_N = BIT(3),
|
||||
MCFPGA_RESET_N = BIT(4),
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -47,7 +47,7 @@ enum {
|
||||
GPIO_MDIO = 1 << 15,
|
||||
};
|
||||
|
||||
unsigned int mclink_fpgacount;
|
||||
uint mclink_fpgacount;
|
||||
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
|
||||
|
||||
struct {
|
||||
@ -107,7 +107,7 @@ int checkboard(void)
|
||||
|
||||
printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
|
||||
|
||||
if (s != NULL) {
|
||||
if (s) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
@ -120,12 +120,11 @@ int checkboard(void)
|
||||
int last_stage_init(void)
|
||||
{
|
||||
int slaves;
|
||||
unsigned int k;
|
||||
unsigned int mux_ch;
|
||||
unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
|
||||
uint k;
|
||||
uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
|
||||
u16 fpga_features;
|
||||
bool hw_type_cat = pca9698_get_value(0x20, 20);
|
||||
bool ch0_rgmii2_present = false;
|
||||
bool ch0_rgmii2_present;
|
||||
|
||||
FPGA_GET_REG(0, fpga_features, &fpga_features);
|
||||
|
||||
@ -137,16 +136,16 @@ int last_stage_init(void)
|
||||
|
||||
/* wait for FPGA done, then reset FPGA */
|
||||
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
|
||||
unsigned int ctr = 0;
|
||||
uint ctr = 0;
|
||||
|
||||
if (i2c_probe(mclink_controllers[k]))
|
||||
continue;
|
||||
|
||||
while (!(pca953x_get_val(mclink_controllers[k])
|
||||
& MCFPGA_DONE)) {
|
||||
udelay(100000);
|
||||
mdelay(100);
|
||||
if (ctr++ > 5) {
|
||||
printf("no done for mclink_controller %d\n", k);
|
||||
printf("no done for mclink_controller %u\n", k);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -159,8 +158,10 @@ int last_stage_init(void)
|
||||
}
|
||||
|
||||
if (hw_type_cat) {
|
||||
uint mux_ch;
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
|
||||
@ -179,7 +180,7 @@ int last_stage_init(void)
|
||||
}
|
||||
|
||||
/* give slave-PLLs and Parade DP501 some time to be up and running */
|
||||
udelay(500000);
|
||||
mdelay(500);
|
||||
|
||||
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
|
||||
slaves = mclink_probe();
|
||||
@ -207,6 +208,7 @@ int last_stage_init(void)
|
||||
if (hw_type_cat) {
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
|
||||
@ -233,17 +235,17 @@ int last_stage_init(void)
|
||||
* provide access to fpga gpios and controls (for I2C bitbang)
|
||||
* (these may look all too simple but make iocon.h much more readable)
|
||||
*/
|
||||
void fpga_gpio_set(unsigned int bus, int pin)
|
||||
void fpga_gpio_set(uint bus, int pin)
|
||||
{
|
||||
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
|
||||
}
|
||||
|
||||
void fpga_gpio_clear(unsigned int bus, int pin)
|
||||
void fpga_gpio_clear(uint bus, int pin)
|
||||
{
|
||||
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
|
||||
}
|
||||
|
||||
int fpga_gpio_get(unsigned int bus, int pin)
|
||||
int fpga_gpio_get(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
|
||||
return val & pin;
|
||||
}
|
||||
|
||||
void fpga_control_set(unsigned int bus, int pin)
|
||||
void fpga_control_set(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin)
|
||||
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
|
||||
}
|
||||
|
||||
void fpga_control_clear(unsigned int bus, int pin)
|
||||
void fpga_control_clear(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -273,7 +275,7 @@ void mpc8308_init(void)
|
||||
pca9698_direction_output(0x20, 4, 1);
|
||||
}
|
||||
|
||||
void mpc8308_set_fpga_reset(unsigned state)
|
||||
void mpc8308_set_fpga_reset(uint state)
|
||||
{
|
||||
pca9698_set_value(0x20, 4, state ? 0 : 1);
|
||||
}
|
||||
@ -285,11 +287,11 @@ void mpc8308_setup_hw(void)
|
||||
/*
|
||||
* set "startup-finished"-gpios
|
||||
*/
|
||||
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
|
||||
setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
|
||||
setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
|
||||
setbits_gpio0_out(BIT(31 - 12));
|
||||
}
|
||||
|
||||
int mpc8308_get_fpga_done(unsigned fpga)
|
||||
int mpc8308_get_fpga_done(uint fpga)
|
||||
{
|
||||
return pca9698_get_value(0x20, 19);
|
||||
}
|
||||
@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
*/
|
||||
|
||||
struct fpga_mii {
|
||||
unsigned fpga;
|
||||
uint fpga;
|
||||
int mdio;
|
||||
} fpga_mii[] = {
|
||||
{ 0, 1},
|
||||
@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
|
||||
},
|
||||
};
|
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
|
||||
sizeof(bb_miiphy_buses[0]);
|
||||
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|
||||
|
||||
@ -24,14 +24,34 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int get_fpga_state(unsigned dev)
|
||||
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
|
||||
/* as gpio output status cannot be read back, we have to buffer it locally */
|
||||
u32 gpio0_out;
|
||||
|
||||
void setbits_gpio0_out(u32 mask)
|
||||
{
|
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
gpio0_out |= mask;
|
||||
out_be32(&immr->gpio[0].dat, gpio0_out);
|
||||
}
|
||||
|
||||
void clrbits_gpio0_out(u32 mask)
|
||||
{
|
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
gpio0_out &= ~mask;
|
||||
out_be32(&immr->gpio[0].dat, gpio0_out);
|
||||
}
|
||||
|
||||
int get_fpga_state(uint dev)
|
||||
{
|
||||
return gd->arch.fpga_state[dev];
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
unsigned k;
|
||||
uint k;
|
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
|
||||
gd->arch.fpga_state[k] = 0;
|
||||
@ -41,8 +61,8 @@ int board_early_init_f(void)
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
unsigned k;
|
||||
unsigned ctr;
|
||||
uint k;
|
||||
uint ctr;
|
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
|
||||
gd->arch.fpga_state[k] = 0;
|
||||
@ -59,7 +79,7 @@ int board_early_init_r(void)
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
|
||||
ctr = 0;
|
||||
while (!mpc8308_get_fpga_done(k)) {
|
||||
udelay(100000);
|
||||
mdelay(100);
|
||||
if (ctr++ > 5) {
|
||||
gd->arch.fpga_state[k] |=
|
||||
FPGA_STATE_DONE_FAILED;
|
||||
@ -86,7 +106,7 @@ int board_early_init_r(void)
|
||||
if (val == REFLECTION_TESTPATTERN_INV)
|
||||
break;
|
||||
|
||||
udelay(100000);
|
||||
mdelay(100);
|
||||
if (ctr++ > 5) {
|
||||
gd->arch.fpga_state[k] |=
|
||||
FPGA_STATE_REFLECTION_FAILED;
|
||||
@ -97,3 +117,4 @@ int board_early_init_r(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,6 +1,9 @@
|
||||
#ifndef __MPC8308_H_
|
||||
#define __MPC8308_H_
|
||||
|
||||
void setbits_gpio0_out(u32 mask);
|
||||
void clrbits_gpio0_out(u32 mask);
|
||||
|
||||
/* functions to be provided by board implementation */
|
||||
void mpc8308_init(void);
|
||||
void mpc8308_set_fpga_reset(unsigned state);
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
* board\freescale\mpc8315erdb\sdram.c
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_MPC83XX_SDRAM
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <spd_sdram.h>
|
||||
@ -34,7 +36,7 @@ static long fixed_sdram(void)
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
|
||||
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
|
||||
@ -62,7 +64,7 @@ static long fixed_sdram(void)
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
sync();
|
||||
|
||||
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
|
||||
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
@ -81,3 +83,5 @@ int dram_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_MPC83XX_SDRAM */
|
||||
|
||||
@ -50,7 +50,7 @@ enum {
|
||||
GPIO_MDIO = 1 << 15,
|
||||
};
|
||||
|
||||
unsigned int mclink_fpgacount;
|
||||
uint mclink_fpgacount;
|
||||
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
|
||||
|
||||
struct {
|
||||
@ -110,7 +110,7 @@ int checkboard(void)
|
||||
|
||||
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
|
||||
|
||||
if (s != NULL) {
|
||||
if (s) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
@ -123,17 +123,17 @@ int checkboard(void)
|
||||
int last_stage_init(void)
|
||||
{
|
||||
int slaves;
|
||||
unsigned int k;
|
||||
unsigned int mux_ch;
|
||||
unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
|
||||
uint k;
|
||||
uint mux_ch;
|
||||
uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
|
||||
#ifdef CONFIG_STRIDER_CPU
|
||||
unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
|
||||
uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
|
||||
#endif
|
||||
bool hw_type_cat = pca9698_get_value(0x20, 18);
|
||||
#ifdef CONFIG_STRIDER_CON_DP
|
||||
bool is_dh = pca9698_get_value(0x20, 25);
|
||||
#endif
|
||||
bool ch0_sgmii2_present = false;
|
||||
bool ch0_sgmii2_present;
|
||||
|
||||
/* Turn on Analog Devices ADV7611 */
|
||||
pca9698_direction_output(0x20, 8, 0);
|
||||
@ -146,8 +146,8 @@ int last_stage_init(void)
|
||||
|
||||
/* wait for FPGA done, then reset FPGA */
|
||||
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
|
||||
unsigned int ctr = 0;
|
||||
unsigned char *mclink_controllers = mclink_controllers_dvi;
|
||||
uint ctr = 0;
|
||||
uchar *mclink_controllers = mclink_controllers_dvi;
|
||||
|
||||
#ifdef CONFIG_STRIDER_CPU
|
||||
if (i2c_probe(mclink_controllers[k])) {
|
||||
@ -161,7 +161,7 @@ int last_stage_init(void)
|
||||
#endif
|
||||
while (!(pca953x_get_val(mclink_controllers[k])
|
||||
& MCFPGA_DONE)) {
|
||||
udelay(100000);
|
||||
mdelay(100);
|
||||
if (ctr++ > 5) {
|
||||
printf("no done for mclink_controller %d\n", k);
|
||||
break;
|
||||
@ -178,6 +178,7 @@ int last_stage_init(void)
|
||||
if (hw_type_cat) {
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
|
||||
@ -196,7 +197,7 @@ int last_stage_init(void)
|
||||
}
|
||||
|
||||
/* give slave-PLLs and Parade DP501 some time to be up and running */
|
||||
udelay(500000);
|
||||
mdelay(500);
|
||||
|
||||
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
|
||||
slaves = mclink_probe();
|
||||
@ -235,7 +236,7 @@ int last_stage_init(void)
|
||||
for (k = 1; k <= slaves; ++k)
|
||||
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
|
||||
|
||||
udelay(500000);
|
||||
mdelay(500);
|
||||
#endif
|
||||
|
||||
for (k = 1; k <= slaves; ++k) {
|
||||
@ -260,6 +261,7 @@ int last_stage_init(void)
|
||||
if (hw_type_cat) {
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
|
||||
@ -286,17 +288,17 @@ int last_stage_init(void)
|
||||
* provide access to fpga gpios (for I2C bitbang)
|
||||
* (these may look all too simple but make iocon.h much more readable)
|
||||
*/
|
||||
void fpga_gpio_set(unsigned int bus, int pin)
|
||||
void fpga_gpio_set(uint bus, int pin)
|
||||
{
|
||||
FPGA_SET_REG(bus, gpio.set, pin);
|
||||
}
|
||||
|
||||
void fpga_gpio_clear(unsigned int bus, int pin)
|
||||
void fpga_gpio_clear(uint bus, int pin)
|
||||
{
|
||||
FPGA_SET_REG(bus, gpio.clear, pin);
|
||||
}
|
||||
|
||||
int fpga_gpio_get(unsigned int bus, int pin)
|
||||
int fpga_gpio_get(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STRIDER_CON_DP
|
||||
void fpga_control_set(unsigned int bus, int pin)
|
||||
void fpga_control_set(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin)
|
||||
FPGA_SET_REG(bus, control, val | pin);
|
||||
}
|
||||
|
||||
void fpga_control_clear(unsigned int bus, int pin)
|
||||
void fpga_control_clear(uint bus, int pin)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
@ -328,7 +330,7 @@ void mpc8308_init(void)
|
||||
pca9698_direction_output(0x20, 26, 1);
|
||||
}
|
||||
|
||||
void mpc8308_set_fpga_reset(unsigned state)
|
||||
void mpc8308_set_fpga_reset(uint state)
|
||||
{
|
||||
pca9698_set_value(0x20, 26, state ? 0 : 1);
|
||||
}
|
||||
@ -340,11 +342,11 @@ void mpc8308_setup_hw(void)
|
||||
/*
|
||||
* set "startup-finished"-gpios
|
||||
*/
|
||||
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
|
||||
setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
|
||||
setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
|
||||
setbits_gpio0_out(BIT(31 - 12));
|
||||
}
|
||||
|
||||
int mpc8308_get_fpga_done(unsigned fpga)
|
||||
int mpc8308_get_fpga_done(uint fpga)
|
||||
{
|
||||
return pca9698_get_value(0x20, 20);
|
||||
}
|
||||
@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
*/
|
||||
|
||||
struct fpga_mii {
|
||||
unsigned fpga;
|
||||
uint fpga;
|
||||
int mdio;
|
||||
} fpga_mii[] = {
|
||||
{ 0, 1},
|
||||
@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
|
||||
},
|
||||
};
|
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
|
||||
sizeof(bb_miiphy_buses[0]);
|
||||
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|
||||
|
||||
@ -1,3 +1,10 @@
|
||||
config GDSYS_LEGACY_DRIVERS
|
||||
bool
|
||||
help
|
||||
Enable the gdsys legacy drivers under board/gdsys/common. If this
|
||||
option is not set, all relevant DM drivers must be configured for the
|
||||
device in question.
|
||||
|
||||
if TARGET_CONTROLCENTERD
|
||||
|
||||
config SYS_BOARD
|
||||
@ -9,4 +16,7 @@ config SYS_VENDOR
|
||||
config SYS_CONFIG_NAME
|
||||
default "controlcenterd"
|
||||
|
||||
config GDSYS_LEGACY_DRIVERS
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar,
|
||||
(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
|
||||
(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
|
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
|
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
|
||||
sync();
|
||||
@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config)
|
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
||||
/* now check the real size */
|
||||
disable_addr_trans();
|
||||
msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
|
||||
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
|
||||
enable_addr_trans();
|
||||
#endif
|
||||
return msize;
|
||||
@ -129,8 +129,8 @@ int dram_init(void)
|
||||
|
||||
msize = setup_sdram();
|
||||
|
||||
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
|
||||
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
|
||||
out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
|
||||
out_be32(&lbc->mrtpr, 0x20000000);
|
||||
sync();
|
||||
|
||||
gd->ram_size = msize;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user