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Merge git://git.denx.de/u-boot-mpc83xx

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- Update MPC83xx platform support to current best practices, etc.
This commit is contained in:
Tom Rini
2019-05-21 07:13:35 -04:00
parent ffbad25b32 d494cdb97e
commit e1a2ed7180
220 changed files with 20058 additions and 5906 deletions
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13
board/esd/vme8349/Kconfig
View File

@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "vme8349"
endif
if TARGET_CADDY2
config SYS_BOARD
default "vme8349"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "caddy2"
endif

10
board/esd/vme8349/vme8349.c
View File

@@ -38,7 +38,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main memory */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = spd_sdram();
@@ -60,7 +60,7 @@ int dram_init(void)
int checkboard(void)
{
#ifdef VME_CADDY2
#ifdef CONFIG_TARGET_CADDY2
puts("Board: esd VME-CADDY/2\n");
#else
puts("Board: esd VME-CPU/8349\n");
@@ -69,7 +69,7 @@ int checkboard(void)
return 0;
}
#ifdef VME_CADDY2
#ifdef CONFIG_TARGET_CADDY2
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
@@ -102,7 +102,7 @@ int misc_init_r()
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
* and VME-CADDY/2) have different SDRAM configurations.
*/
#ifdef VME_CADDY2
#ifdef CONFIG_TARGET_CADDY2
#define SMALL_RAM 0xff
#define LARGE_RAM 0x00
#else
@@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = {
SPD_VAL(0x7e, 0x1d), /* 63 */
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
SPD_VAL(0x00, 0x00), /* 72 */
#ifdef VME_CADDY2
#ifdef CONFIG_TARGET_CADDY2
{ "vme-caddy/2 ram " }
#else
{ "vme-cpu/2 ram " }

6
board/freescale/common/pq-mds-pib.c
View File

@@ -36,7 +36,7 @@ int pib_init(void)
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(CONFIG_MPC832XEMDS)
#if defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
@@ -55,7 +55,7 @@ int pib_init(void)
eieio();
#if defined(CONFIG_MPC832XEMDS)
#if defined(CONFIG_TARGET_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
@@ -76,7 +76,7 @@ int pib_init(void)
eieio();
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
#elif defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;

4
board/freescale/mpc8308rdb/sdram.c
View File

@@ -33,7 +33,7 @@ static long fixed_sdram(void)
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)

17
board/freescale/mpc8313erdb/Kconfig
View File

@@ -1,4 +1,4 @@
if TARGET_MPC8313ERDB
if TARGET_MPC8313ERDB_NOR
config SYS_BOARD
default "mpc8313erdb"
@@ -7,6 +7,19 @@ config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8313ERDB"
default "MPC8313ERDB_NOR"
endif
if TARGET_MPC8313ERDB_NAND
config SYS_BOARD
default "mpc8313erdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8313ERDB_NAND"
endif

13
board/freescale/mpc8313erdb/sdram.c
View File

@@ -47,7 +47,7 @@ static long fixed_sdram(void)
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -57,12 +57,12 @@ static long fixed_sdram(void)
*/
__udelay(50000);
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -109,8 +109,9 @@ int dram_init(void)
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
/* LB refresh timer prescal, 266MHz/32 */
lbc->mrtpr = 0x20000000;
sync();
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC

1
board/freescale/mpc8315erdb/MAINTAINERS
View File

@@ -4,3 +4,4 @@ S: Orphan (since 2018-05)
F: board/freescale/mpc8315erdb/
F: include/configs/MPC8315ERDB.h
F: configs/MPC8315ERDB_defconfig
F: configs/MPC8315ERDB_NANDSPL_defconfig

2
board/freescale/mpc8315erdb/sdram.c
View File

@@ -44,7 +44,7 @@ static long fixed_sdram(void)
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

2
board/freescale/mpc8323erdb/mpc8323erdb.c
View File

@@ -79,7 +79,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();

2
board/freescale/mpc832xemds/mpc832xemds.c
View File

@@ -98,7 +98,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();

13
board/freescale/mpc8349emds/Kconfig
View File

@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "MPC8349EMDS"
endif
if TARGET_MPC8349EMDS_SDRAM
config SYS_BOARD
default "mpc8349emds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8349EMDS_SDRAM"
endif

3
board/freescale/mpc8349emds/MAINTAINERS
View File

@@ -4,3 +4,6 @@ S: Orphan (since 2018-05)
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
F: configs/MPC8349EMDS_SDRAM_defconfig
F: configs/MPC8349EMDS_PCI64_defconfig
F: configs/MPC8349EMDS_SLAVE_defconfig

37
board/freescale/mpc8349emds/mpc8349emds.c
View File

@@ -56,7 +56,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
@@ -91,7 +91,7 @@ int fixed_sdram(void)
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@ int fixed_sdram(void)
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
@@ -183,28 +183,36 @@ void sdram_init(void)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->lbcr = 0x00000000;
/* LB refresh timer prescal, 266MHz/32 */
lbc->mrtpr = 0x20000000;
/* LB sdram refresh timer, about 6us */
lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
/* 0x68636733; precharge all the banks */
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
/* 0x48636733; auto refresh */
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -232,12 +240,13 @@ void sdram_init(void)
udelay(100);
/* 0x58636733; mode register write operation */
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);

12
board/freescale/mpc8349emds/pci.c
View File

@@ -77,11 +77,11 @@ void pib_init(void)
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(PCI_64BIT)
#if defined(CONFIG_PCI_64BIT)
val8 = 0xf4; /* PMC2:PCI1/64-bit */
#elif defined(PCI_ALL_PCI1)
#elif defined(CONFIG_PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
#elif defined(PCI_ONE_PCI1)
#elif defined(CONFIG_PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
#else
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
@@ -98,11 +98,11 @@ void pib_init(void)
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
#if defined(PCI_64BIT)
#if defined(CONFIG_PCI_64BIT)
printf("PCI1: 64-bit on PMC2\n");
#elif defined(PCI_ALL_PCI1)
#elif defined(CONFIG_PCI_ALL_PCI1)
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
#elif defined(PCI_ONE_PCI1)
#elif defined(CONFIG_PCI_ONE_PCI1)
printf("PCI1: 32-bit on PMC1\n");
printf("PCI2: 32-bit on PMC2, PMC3\n");
#else

15
board/freescale/mpc8349itx/mpc8349itx.c
View File

@@ -19,6 +19,9 @@
#include <linux/libfdt.h>
#endif
#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM
@@ -34,14 +37,14 @@ int fixed_sdram(void)
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -129,7 +132,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#ifdef CONFIG_SPD_EEPROM
msize = spd_sdram();
#else
@@ -152,7 +155,7 @@ int dram_init(void)
int checkboard(void)
{
#ifdef CONFIG_MPC8349ITX
#ifdef CONFIG_TARGET_MPC8349ITX
puts("Board: Freescale MPC8349E-mITX\n");
#else
puts("Board: Freescale MPC8349E-mITX-GP\n");

1
board/freescale/mpc837xemds/MAINTAINERS
View File

@@ -4,4 +4,5 @@ S: Orphan (since 2018-05)
F: board/freescale/mpc837xemds/
F: include/configs/MPC837XEMDS.h
F: configs/MPC837XEMDS_defconfig
F: configs/MPC837XEMDS_SLAVE_defconfig
F: configs/MPC837XEMDS_HOST_defconfig

2
board/freescale/mpc837xemds/mpc837xemds.c
View File

@@ -252,7 +252,7 @@ int fixed_sdram(void)
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CONFIG_SYS_DDR_SIZE != 512)

1
board/freescale/mpc837xerdb/MAINTAINERS
View File

@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
F: configs/MPC837XERDB_SLAVE_defconfig

2
board/freescale/mpc837xerdb/mpc837xerdb.c
View File

@@ -95,7 +95,7 @@ int fixed_sdram(void)
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

11
board/gdsys/common/Makefile
View File

@@ -5,16 +5,13 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
obj-$(CONFIG_STRIDER) += fanctrl.o
obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
ifdef CONFIG_OSD
obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o

4
board/gdsys/common/adv7611.c
View File

@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <i2c.h>
@@ -174,3 +176,5 @@ out:
return res;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

4
board/gdsys/common/ch7301.c
View File

@@ -6,6 +6,8 @@
/* Chrontel CH7301C DVI Transmitter */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -61,3 +63,5 @@ int ch7301_probe(unsigned screen, bool power)
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

376
board/gdsys/common/cmd_ioloop.c
View File

@@ -10,34 +10,53 @@
#include <gdsys_fpga.h>
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
#include <dm.h>
#include <misc.h>
#include <regmap.h>
#include <board.h>
#include "../../../drivers/misc/gdsys_soc.h"
#include "../../../drivers/misc/gdsys_ioep.h"
#include "../../../drivers/misc/ihs_fpga.h"
const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
enum status_print_type {
STATUS_LOUD = 0,
STATUS_SILENT = 1,
};
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
enum {
STATE_TX_PACKET_BUILDING = 1<<0,
STATE_TX_TRANSMITTING = 1<<1,
STATE_TX_BUFFER_FULL = 1<<2,
STATE_TX_ERR = 1<<3,
STATE_RECEIVE_TIMEOUT = 1<<4,
STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
STATE_RX_DIST_ERR = 1<<7,
STATE_RX_LENGTH_ERR = 1<<8,
STATE_RX_FRAME_CTR_ERR = 1<<9,
STATE_RX_FCS_ERR = 1<<10,
STATE_RX_PACKET_DROPPED = 1<<11,
STATE_RX_DATA_LAST = 1<<12,
STATE_RX_DATA_FIRST = 1<<13,
STATE_RX_DATA_AVAILABLE = 1<<15,
STATE_TX_PACKET_BUILDING = BIT(0),
STATE_TX_TRANSMITTING = BIT(1),
STATE_TX_BUFFER_FULL = BIT(2),
STATE_TX_ERR = BIT(3),
STATE_RECEIVE_TIMEOUT = BIT(4),
STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
STATE_RX_DIST_ERR = BIT(7),
STATE_RX_LENGTH_ERR = BIT(8),
STATE_RX_FRAME_CTR_ERR = BIT(9),
STATE_RX_FCS_ERR = BIT(10),
STATE_RX_PACKET_DROPPED = BIT(11),
STATE_RX_DATA_LAST = BIT(12),
STATE_RX_DATA_FIRST = BIT(13),
STATE_RX_DATA_AVAILABLE = BIT(15),
};
enum {
CTRL_PROC_RECEIVE_ENABLE = 1<<12,
CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
};
enum {
IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
CTRL_PROC_RECEIVE_ENABLE = BIT(12),
CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
};
struct io_generic_packet {
@@ -47,12 +66,17 @@ struct io_generic_packet {
u8 bc;
u16 packet_length;
} __attribute__((__packed__));
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
unsigned long long rx_ctr;
unsigned long long tx_ctr;
unsigned long long err_ctr;
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
struct udevice *dev;
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
static void io_check_status(unsigned int fpga, u16 status, bool silent)
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_check_status(uint fpga, u16 status, enum status_print_type type)
{
u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
@@ -66,7 +90,7 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent)
err_ctr++;
FPGA_SET_REG(fpga, ep.rx_tx_status, status);
if (silent)
if (type == STATUS_SILENT)
return;
if (status & STATE_RX_PACKET_DROPPED)
@@ -84,10 +108,42 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent)
if (status & STATE_TX_ERR)
printf("TX_ERR\n");
}
static void io_send(unsigned int fpga, unsigned int size)
#else
static void io_check_status(struct udevice *dev, enum status_print_type type)
{
unsigned int k;
u16 status = 0;
int ret;
ret = misc_call(dev, 0, NULL, 0, &status, 0);
if (!ret)
return;
err_ctr++;
if (type != STATUS_LOUD)
return;
if (status & STATE_RX_PACKET_DROPPED)
printf("RX_PACKET_DROPPED, status %04x\n", status);
if (status & STATE_RX_DIST_ERR)
printf("RX_DIST_ERR\n");
if (status & STATE_RX_LENGTH_ERR)
printf("RX_LENGTH_ERR\n");
if (status & STATE_RX_FRAME_CTR_ERR)
printf("RX_FRAME_CTR_ERR\n");
if (status & STATE_RX_FCS_ERR)
printf("RX_FCS_ERR\n");
if (status & STATE_TX_ERR)
printf("TX_ERR\n");
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_send(uint fpga, uint size)
{
uint k;
struct io_generic_packet packet = {
.source_address = 1,
.packet_type = 1,
@@ -106,10 +162,31 @@ static void io_send(unsigned int fpga, unsigned int size)
tx_ctr++;
}
static void io_receive(unsigned int fpga)
#else
static void io_send(struct udevice *dev, uint size)
{
uint k;
u16 buffer[HEADER_WORDS + 128];
struct io_generic_packet header = {
.source_address = 1,
.packet_type = 1,
.packet_length = size,
};
const uint words = (size + 1) / 2;
memcpy(buffer, &header, 2 * HEADER_WORDS);
for (k = 0; k < words; ++k)
buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
misc_write(dev, 0, buffer, HEADER_WORDS + words);
tx_ctr++;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_receive(uint fpga)
{
unsigned int k = 0;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
@@ -123,17 +200,25 @@ static void io_receive(unsigned int fpga)
FPGA_GET_REG(fpga, ep.receive_data, &rx);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
++k;
}
}
#else
static void io_receive(struct udevice *dev)
{
u16 buffer[HEADER_WORDS + 128];
static void io_reflect(unsigned int fpga)
if (!misc_read(dev, 0, buffer, 0))
rx_ctr++;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_reflect(uint fpga)
{
u16 buffer[128];
unsigned int k = 0;
unsigned int n;
uint k = 0;
uint n;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
@@ -157,7 +242,22 @@ static void io_reflect(unsigned int fpga)
tx_ctr++;
}
#else
static void io_reflect(struct udevice *dev)
{
u16 buffer[HEADER_WORDS + 128];
struct io_generic_packet *header;
if (misc_read(dev, 0, buffer, 0))
return;
header = (struct io_generic_packet *)&buffer;
misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint reflector
*
@@ -166,8 +266,8 @@ static void io_reflect(unsigned int fpga)
*/
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int fpga;
unsigned int rate = 0;
uint fpga;
uint rate = 0;
unsigned long long last_seen = 0;
if (argc < 2)
@@ -181,10 +281,10 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (argc > 2)
rate = simple_strtoul(argv[2], NULL, 10);
/* enable receive path */
/* Enable receive path */
FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
/* set device address to dummy 1*/
/* Set device address to dummy 1*/
FPGA_SET_REG(fpga, ep.device_address, 1);
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
@@ -196,7 +296,7 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
io_check_status(fpga, rx_tx_status, true);
io_check_status(fpga, rx_tx_status, STATUS_SILENT);
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
io_reflect(fpga);
@@ -214,19 +314,71 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#else
/*
* FPGA io-endpoint reflector
*
* Syntax:
* ioreflect {reportrate}
*/
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *fpga;
struct regmap *map;
uint rate = 0;
unsigned long long last_seen = 0;
if (!dev) {
printf("No device selected\n");
return 1;
}
gdsys_soc_get_fpga(dev, &fpga);
regmap_init_mem(dev_ofnode(dev), &map);
/* Enable receive path */
misc_set_enabled(dev, true);
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
while (1) {
uint top_int;
ihs_fpga_get(map, top_interrupt, &top_int);
io_check_status(dev, STATUS_SILENT);
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
io_reflect(dev);
if (rate) {
if (!(tx_ctr % rate) && (tx_ctr != last_seen))
printf("refl %llu, err %llu\n", tx_ctr,
err_ctr);
last_seen = tx_ctr;
}
if (ctrlc())
break;
}
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#define DISP_LINE_LEN 16
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint looptest
*
* Syntax:
* ioloop {fpga} {size} {rate}
*/
#define DISP_LINE_LEN 16
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int fpga;
unsigned int size;
unsigned int rate = 0;
uint fpga;
uint size;
uint rate = 0;
if (argc < 3)
return CMD_RET_USAGE;
@@ -262,7 +414,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
io_check_status(fpga, rx_tx_status, false);
io_check_status(fpga, rx_tx_status, STATUS_LOUD);
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
io_send(fpga, size);
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
@@ -273,7 +425,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
break;
udelay(1000000 / rate);
if (!(tx_ctr % rate))
printf("d %lld, tx %llu, rx %llu, err %llu\n",
printf("d %llu, tx %llu, rx %llu, err %llu\n",
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
err_ctr);
}
@@ -281,7 +433,122 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#else
/*
* FPGA io-endpoint looptest
*
* Syntax:
* ioloop {size} {rate}
*/
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint size;
uint rate = 0;
struct udevice *fpga;
struct regmap *map;
if (!dev) {
printf("No device selected\n");
return 1;
}
gdsys_soc_get_fpga(dev, &fpga);
regmap_init_mem(dev_ofnode(dev), &map);
if (argc < 2)
return CMD_RET_USAGE;
/*
* packet size is specified since argc > 1
*/
size = simple_strtoul(argv[2], NULL, 10);
/*
* If another parameter, it is the test rate in packets per second.
*/
if (argc > 2)
rate = simple_strtoul(argv[3], NULL, 10);
/* Enable receive path */
misc_set_enabled(dev, true);
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
while (1) {
uint top_int;
if (ctrlc())
break;
ihs_fpga_get(map, top_interrupt, &top_int);
io_check_status(dev, STATUS_LOUD);
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
io_send(dev, size);
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
io_receive(dev);
if (rate) {
udelay(1000000 / rate);
if (!(tx_ctr % rate))
printf("d %llu, tx %llu, rx %llu, err %llu\n",
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
err_ctr);
}
}
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *ioep = NULL;
struct udevice *board;
char name[8];
int ret;
if (board_get(&board))
return CMD_RET_FAILURE;
if (argc > 1) {
int i = simple_strtoul(argv[1], NULL, 10);
snprintf(name, sizeof(name), "ioep%d", i);
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
if (ret || !ioep) {
printf("Invalid IOEP %d\n", i);
return CMD_RET_FAILURE;
}
dev = ioep;
} else {
int i = 0;
while (1) {
snprintf(name, sizeof(name), "ioep%d", i);
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
if (ret || !ioep)
break;
printf("IOEP %d:\t%s\n", i++, ioep->name);
}
if (dev)
printf("\nSelected IOEP: %s\n", dev->name);
else
puts("\nNo IOEP selected.\n");
}
return 0;
}
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
U_BOOT_CMD(
ioloop, 4, 0, do_ioloop,
"fpga io-endpoint looptest",
@@ -293,3 +560,22 @@ U_BOOT_CMD(
"fpga io-endpoint reflector",
"fpga reportrate"
);
#else
U_BOOT_CMD(
ioloop, 3, 0, do_ioloop,
"fpga io-endpoint looptest",
"packetsize [packets/sec]"
);
U_BOOT_CMD(
ioreflect, 2, 0, do_ioreflect,
"fpga io-endpoint reflector",
"reportrate"
);
U_BOOT_CMD(
iodev, 2, 0, do_iodev,
"fpga io-endpoint listing/selection",
"[ioep device to select]"
);
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

4
board/gdsys/common/dp501.c
View File

@@ -6,6 +6,8 @@
/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -155,3 +157,5 @@ int dp501_probe(unsigned screen, bool power)
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

4
board/gdsys/common/fanctrl.c
View File

@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <i2c.h>
@@ -29,3 +31,5 @@ void init_fan_controller(u8 addr)
val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
i2c_reg_write(addr, FAN_CONFIG, val);
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

4
board/gdsys/common/fpga.c
View File

@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <gdsys_fpga.h>
@@ -22,3 +24,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

5
board/gdsys/common/ihs_mdio.c
View File

@@ -11,6 +11,7 @@
#include <gdsys_fpga.h>
#else
#include <fdtdec.h>
#include <dm.h>
#include <regmap.h>
#endif
@@ -28,7 +29,7 @@ static inline u16 read_reg(struct udevice *fpga, uint base, uint addr)
struct regmap *map;
u8 *ptr;
regmap_init_mem(fpga, &map);
regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
return in_le16((u16 *)(ptr + base + addr));
@@ -40,7 +41,7 @@ static inline void write_reg(struct udevice *fpga, uint base, uint addr,
struct regmap *map;
u8 *ptr;
regmap_init_mem(fpga, &map);
regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
out_le16((u16 *)(ptr + base + addr), val);

663
board/gdsys/common/ioep-fpga.c
View File

@@ -4,233 +4,586 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <gdsys_fpga.h>
enum {
UNITTYPE_MAIN_SERVER = 0,
UNITTYPE_MAIN_USER = 1,
UNITTYPE_VIDEO_SERVER = 2,
UNITTYPE_VIDEO_USER = 3,
enum pcb_video_type {
PCB_DVI_SL,
PCB_DP_165MPIX,
PCB_DP_300MPIX,
PCB_HDMI,
PCB_DP_1_2,
PCB_HDMI_2_0,
};
enum {
UNITTYPEPCB_DVI = 0,
UNITTYPEPCB_DP_165 = 1,
UNITTYPEPCB_DP_300 = 2,
UNITTYPEPCB_HDMI = 3,
enum pcb_transmission_type {
PCB_CAT_1G,
PCB_FIBER_3G,
PCB_CAT_10G,
PCB_FIBER_10G,
};
enum {
COMPRESSION_NONE = 0,
COMPRESSION_TYPE_1 = 1,
COMPRESSION_TYPE_1_2 = 3,
COMPRESSION_TYPE_1_2_3 = 7,
enum carrier_speed {
CARRIER_SPEED_1G,
CARRIER_SPEED_3G,
CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
CARRIER_SPEED_10G,
};
enum {
AUDIO_NONE = 0,
AUDIO_TX = 1,
AUDIO_RX = 2,
AUDIO_RXTX = 3,
enum ram_config {
RAM_DDR2_32BIT_295MBPS,
RAM_DDR3_32BIT_590MBPS,
RAM_DDR3_48BIT_590MBPS,
RAM_DDR3_64BIT_1800MBPS,
RAM_DDR3_48BIT_1800MBPS,
};
enum {
SYSCLK_147456 = 0,
enum sysclock {
SYSCLK_147456,
};
enum {
RAM_DDR2_32 = 0,
RAM_DDR3_32 = 1,
RAM_DDR3_48 = 2,
struct fpga_versions {
bool video_channel;
bool con_side;
enum pcb_video_type pcb_video_type;
enum pcb_transmission_type pcb_transmission_type;
unsigned int hw_version;
};
enum {
CARRIER_SPEED_1G = 0,
CARRIER_SPEED_2_5G = 1,
struct fpga_features {
u8 video_channels;
u8 carriers;
enum carrier_speed carrier_speed;
enum ram_config ram_config;
enum sysclock sysclock;
bool pcm_tx;
bool pcm_rx;
bool spdif_tx;
bool spdif_rx;
bool usb2;
bool rs232;
bool compression_type1;
bool compression_type2;
bool compression_type3;
bool interlace;
bool osd;
bool compression_pipes;
};
#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
static int get_versions(unsigned int fpga, struct fpga_versions *versions)
{
enum {
VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
VERSIONS_FPGA_CON_SIDE = BIT(13),
VERSIONS_FPGA_SC = BIT(14),
VERSIONS_PCB_CON = BIT(9),
VERSIONS_PCB_SC = BIT(8),
VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
VERSIONS_HW_VER_MASK = 0xf << 0,
};
u16 raw_versions;
memset(versions, 0, sizeof(struct fpga_versions));
FPGA_GET_REG(fpga, versions, &raw_versions);
versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
case VERSIONS_PCB_VIDEO_DP_1_2:
versions->pcb_video_type = PCB_DP_1_2;
break;
case VERSIONS_PCB_VIDEO_HDMI_2_0:
versions->pcb_video_type = PCB_HDMI_2_0;
break;
}
switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
versions->pcb_transmission_type = PCB_FIBER_10G;
break;
case VERSIONS_PCB_TRANSMISSION_CAT_10G:
versions->pcb_transmission_type = PCB_CAT_10G;
break;
case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
versions->pcb_transmission_type = PCB_FIBER_3G;
break;
case VERSIONS_PCB_TRANSMISSION_CAT_1G:
versions->pcb_transmission_type = PCB_CAT_1G;
break;
}
versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
return 0;
}
static int get_features(unsigned int fpga, struct fpga_features *features)
{
enum {
FEATURE_SPDIF_RX = BIT(15),
FEATURE_SPDIF_TX = BIT(14),
FEATURE_PCM_RX = BIT(13),
FEATURE_PCM_TX = BIT(12),
FEATURE_RAM_MASK = GENMASK(11, 8),
FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
FEATURE_CARRIERS_MASK = GENMASK(5, 4),
FEATURE_CARRIERS_0 = 0x0 << 4,
FEATURE_CARRIERS_1 = 0x1 << 4,
FEATURE_CARRIERS_2 = 0x2 << 4,
FEATURE_CARRIERS_4 = 0x3 << 4,
FEATURE_USB2 = BIT(3),
FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
};
enum {
EXT_FEATURE_OSD = BIT(15),
EXT_FEATURE_ETHERNET = BIT(9),
EXT_FEATURE_INTERLACE = BIT(8),
EXT_FEATURE_RS232 = BIT(7),
EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
};
u16 raw_features;
u16 raw_extended_features;
memset(features, 0, sizeof(struct fpga_features));
FPGA_GET_REG(fpga, fpga_features, &raw_features);
FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
case FEATURE_VIDEOCHANNELS_0:
features->video_channels = 0;
break;
case FEATURE_VIDEOCHANNELS_1:
features->video_channels = 1;
break;
case FEATURE_VIDEOCHANNELS_1_1:
case FEATURE_VIDEOCHANNELS_2:
features->video_channels = 2;
break;
};
switch (raw_features & FEATURE_CARRIERS_MASK) {
case FEATURE_CARRIERS_0:
features->carriers = 0;
break;
case FEATURE_CARRIERS_1:
features->carriers = 1;
break;
case FEATURE_CARRIERS_2:
features->carriers = 2;
break;
case FEATURE_CARRIERS_4:
features->carriers = 4;
break;
}
switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
case FEATURE_CARRIER_SPEED_1G:
features->carrier_speed = CARRIER_SPEED_1G;
break;
case FEATURE_CARRIER_SPEED_2_5G:
features->carrier_speed = CARRIER_SPEED_2_5G;
break;
case FEATURE_CARRIER_SPEED_10G:
features->carrier_speed = CARRIER_SPEED_10G;
break;
}
switch (raw_features & FEATURE_RAM_MASK) {
case FEATURE_RAM_DDR2_32BIT_295MBPS:
features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
case FEATURE_RAM_DDR3_32BIT_590MBPS:
features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
case FEATURE_RAM_DDR3_48BIT_590MBPS:
features->ram_config = RAM_DDR3_48BIT_590MBPS;
break;
case FEATURE_RAM_DDR3_64BIT_1800MBPS:
features->ram_config = RAM_DDR3_64BIT_1800MBPS;
break;
case FEATURE_RAM_DDR3_48BIT_1800MBPS:
features->ram_config = RAM_DDR3_48BIT_1800MBPS;
break;
}
features->pcm_tx = raw_features & FEATURE_PCM_TX;
features->pcm_rx = raw_features & FEATURE_PCM_RX;
features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
features->usb2 = raw_features & FEATURE_USB2;
features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
features->osd = raw_extended_features & EXT_FEATURE_OSD;
features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
return 0;
}
#else
static int get_versions(unsigned int fpga, struct fpga_versions *versions)
{
enum {
/* HW version encoding is a mess, leave it for the moment */
VERSIONS_HW_VER_MASK = 0xf << 0,
VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
VERSIONS_SFP = BIT(5),
VERSIONS_VIDEO_MASK = 0x7 << 6,
VERSIONS_VIDEO_DVI = 0x0 << 6,
VERSIONS_VIDEO_DP_165 = 0x1 << 6,
VERSIONS_VIDEO_DP_300 = 0x2 << 6,
VERSIONS_VIDEO_HDMI = 0x3 << 6,
VERSIONS_UT_MASK = 0xf << 12,
VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
VERSIONS_UT_MAIN_USER = 0x1 << 12,
VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
VERSIONS_UT_VIDEO_USER = 0x3 << 12,
};
u16 raw_versions;
memset(versions, 0, sizeof(struct fpga_versions));
FPGA_GET_REG(fpga, versions, &raw_versions);
switch (raw_versions & VERSIONS_UT_MASK) {
case VERSIONS_UT_MAIN_SERVER:
versions->video_channel = false;
versions->con_side = false;
break;
case VERSIONS_UT_MAIN_USER:
versions->video_channel = false;
versions->con_side = true;
break;
case VERSIONS_UT_VIDEO_SERVER:
versions->video_channel = true;
versions->con_side = false;
break;
case VERSIONS_UT_VIDEO_USER:
versions->video_channel = true;
versions->con_side = true;
break;
}
switch (raw_versions & VERSIONS_VIDEO_MASK) {
case VERSIONS_VIDEO_DVI:
versions->pcb_video_type = PCB_DVI_SL;
break;
case VERSIONS_VIDEO_DP_165:
versions->pcb_video_type = PCB_DP_165MPIX;
break;
case VERSIONS_VIDEO_DP_300:
versions->pcb_video_type = PCB_DP_300MPIX;
break;
case VERSIONS_VIDEO_HDMI:
versions->pcb_video_type = PCB_HDMI;
break;
}
versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
if (raw_versions & VERSIONS_SFP)
versions->pcb_transmission_type = PCB_FIBER_3G;
else
versions->pcb_transmission_type = PCB_CAT_1G;
return 0;
}
static int get_features(unsigned int fpga, struct fpga_features *features)
{
enum {
FEATURE_CARRIER_SPEED_2_5 = BIT(4),
FEATURE_RAM_MASK = 0x7 << 5,
FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
FEATURE_PCM_AUDIO_TX = BIT(9),
FEATURE_PCM_AUDIO_RX = BIT(10),
FEATURE_OSD = BIT(11),
FEATURE_USB20 = BIT(12),
FEATURE_COMPRESSION_MASK = 7 << 13,
FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
};
enum {
EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
EXTENDED_FEATURE_RS232 = BIT(2),
EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
EXTENDED_FEATURE_INTERLACE = BIT(4),
};
u16 raw_features;
#ifdef GDSYS_LEGACY_DRIVERS
u16 raw_extended_features;
#endif
memset(features, 0, sizeof(struct fpga_features));
FPGA_GET_REG(fpga, fpga_features, &raw_features);
#ifdef GDSYS_LEGACY_DRIVERS
FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
#endif
features->video_channels = raw_features & 0x3;
features->carriers = (raw_features >> 2) & 0x3;
features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
switch (raw_features & FEATURE_RAM_MASK) {
case FEATURE_RAM_DDR2_32BIT:
features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
case FEATURE_RAM_DDR3_32BIT:
features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
case FEATURE_RAM_DDR3_48BIT:
features->ram_config = RAM_DDR3_48BIT_590MBPS;
break;
}
features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
#ifdef GDSYS_LEGACY_DRIVERS
features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
#endif
features->usb2 = raw_features & FEATURE_USB20;
#ifdef GDSYS_LEGACY_DRIVERS
features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
#endif
features->compression_type1 = false;
features->compression_type2 = false;
features->compression_type3 = false;
switch (raw_features & FEATURE_COMPRESSION_MASK) {
case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
features->compression_type3 = true;
case FEATURE_COMPRESSION_TYPE1_TYPE2:
features->compression_type2 = true;
case FEATURE_COMPRESSION_TYPE1:
features->compression_type1 = true;
break;
}
#ifdef GDSYS_LEGACY_DRIVERS
features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
#endif
features->osd = raw_features & FEATURE_OSD;
#ifdef GDSYS_LEGACY_DRIVERS
features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
#endif
return 0;
}
#endif
bool ioep_fpga_has_osd(unsigned int fpga)
{
u16 fpga_features;
unsigned feature_osd;
struct fpga_features features;
FPGA_GET_REG(0, fpga_features, &fpga_features);
feature_osd = fpga_features & (1<<11);
get_features(fpga, &features);
return feature_osd;
return features.osd;
}
void ioep_fpga_print_info(unsigned int fpga)
{
u16 versions;
u16 fpga_version;
u16 fpga_features;
unsigned unit_type;
unsigned unit_type_pcb_video;
unsigned feature_compression;
unsigned feature_osd;
unsigned feature_audio;
unsigned feature_sysclock;
unsigned feature_ramconfig;
unsigned feature_carrier_speed;
unsigned feature_carriers;
unsigned feature_video_channels;
struct fpga_versions versions;
struct fpga_features features;
FPGA_GET_REG(fpga, versions, &versions);
FPGA_GET_REG(fpga, fpga_version, &fpga_version);
FPGA_GET_REG(fpga, fpga_features, &fpga_features);
get_versions(fpga, &versions);
get_features(fpga, &features);
unit_type = (versions & 0xf000) >> 12;
unit_type_pcb_video = (versions & 0x01c0) >> 6;
feature_compression = (fpga_features & 0xe000) >> 13;
feature_osd = fpga_features & (1<<11);
feature_audio = (fpga_features & 0x0600) >> 9;
feature_sysclock = (fpga_features & 0x0180) >> 7;
feature_ramconfig = (fpga_features & 0x0060) >> 5;
feature_carrier_speed = fpga_features & (1<<4);
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
switch (unit_type) {
case UNITTYPE_MAIN_SERVER:
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
break;
case UNITTYPE_VIDEO_SERVER:
case UNITTYPE_VIDEO_USER:
if (versions.video_channel)
printf("Videochannel");
break;
else
printf("Mainchannel");
default:
printf("UnitType %d(not supported)", unit_type);
break;
}
switch (unit_type) {
case UNITTYPE_MAIN_SERVER:
case UNITTYPE_VIDEO_SERVER:
if (versions.con_side)
printf(" User");
else
printf(" Server");
// FIXME
#if 0
if (versions & (1<<4))
printf(" UC");
break;
#endif
case UNITTYPE_MAIN_USER:
case UNITTYPE_VIDEO_USER:
printf(" User");
break;
default:
break;
}
if (versions & (1<<5))
printf(" Fiber");
else
switch(versions.pcb_transmission_type) {
case PCB_CAT_1G:
case PCB_CAT_10G:
printf(" CAT");
break;
case PCB_FIBER_3G:
case PCB_FIBER_10G:
printf(" Fiber");
break;
};
switch (unit_type_pcb_video) {
case UNITTYPEPCB_DVI:
switch (versions.pcb_video_type) {
case PCB_DVI_SL:
printf(" DVI,");
break;
case UNITTYPEPCB_DP_165:
case PCB_DP_165MPIX:
printf(" DP 165MPix/s,");
break;
case UNITTYPEPCB_DP_300:
case PCB_DP_300MPIX:
printf(" DP 300MPix/s,");
break;
case UNITTYPEPCB_HDMI:
case PCB_HDMI:
printf(" HDMI,");
break;
case PCB_DP_1_2:
printf(" DP 1.2,");
break;
case PCB_HDMI_2_0:
printf(" HDMI 2.0,");
break;
}
printf(" FPGA V %d.%02d\n features:",
printf(" FPGA V %d.%02d\n features: ",
fpga_version / 100, fpga_version % 100);
if (!features.compression_type1 &&
!features.compression_type2 &&
!features.compression_type3)
printf("no compression, ");
switch (feature_compression) {
case COMPRESSION_NONE:
printf(" no compression");
break;
if (features.compression_type1)
printf("type1, ");
case COMPRESSION_TYPE_1:
printf(" compression type1(delta)");
break;
if (features.compression_type2)
printf("type2, ");
case COMPRESSION_TYPE_1_2:
printf(" compression type1(delta), type2(inline)");
break;
if (features.compression_type3)
printf("type3, ");
case COMPRESSION_TYPE_1_2_3:
printf(" compression type1(delta), type2(inline), type3(intempo)");
break;
printf("%sosd", features.osd ? "" : "no ");
default:
printf(" compression %d(not supported)", feature_compression);
break;
}
if (features.pcm_rx && features.pcm_tx)
printf(", pcm rx+tx");
else if(features.pcm_rx)
printf(", pcm rx");
else if(features.pcm_tx)
printf(", pcm tx");
printf(", %sosd", feature_osd ? "" : "no ");
switch (feature_audio) {
case AUDIO_NONE:
printf(", no audio");
break;
case AUDIO_TX:
printf(", audio tx");
break;
case AUDIO_RX:
printf(", audio rx");
break;
case AUDIO_RXTX:
printf(", audio rx+tx");
break;
default:
printf(", audio %d(not supported)", feature_audio);
break;
}
if (features.spdif_rx && features.spdif_tx)
printf(", spdif rx+tx");
else if(features.spdif_rx)
printf(", spdif rx");
else if(features.spdif_tx)
printf(", spdif tx");
puts(",\n ");
switch (feature_sysclock) {
switch (features.sysclock) {
case SYSCLK_147456:
printf("clock 147.456 MHz");
break;
default:
printf("clock %d(not supported)", feature_sysclock);
break;
}
switch (feature_ramconfig) {
case RAM_DDR2_32:
switch (features.ram_config) {
case RAM_DDR2_32BIT_295MBPS:
printf(", RAM 32 bit DDR2");
break;
case RAM_DDR3_32:
case RAM_DDR3_32BIT_590MBPS:
printf(", RAM 32 bit DDR3");
break;
case RAM_DDR3_48:
case RAM_DDR3_48BIT_590MBPS:
case RAM_DDR3_48BIT_1800MBPS:
printf(", RAM 48 bit DDR3");
break;
default:
printf(", RAM %d(not supported)", feature_ramconfig);
case RAM_DDR3_64BIT_1800MBPS:
printf(", RAM 64 bit DDR3");
break;
}
printf(", %d carrier(s) %s", feature_carriers,
feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
printf(", %d carrier(s)", features.carriers);
printf(", %d video channel(s)\n", feature_video_channels);
switch(features.carrier_speed) {
case CARRIER_SPEED_1G:
printf(", 1Gbit/s");
break;
case CARRIER_SPEED_3G:
printf(", 3Gbit/s");
break;
case CARRIER_SPEED_10G:
printf(", 10Gbit/s");
break;
}
printf(", %d video channel(s)\n", features.video_channels);
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

4
board/gdsys/common/mclink.c
View File

@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -134,3 +136,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data)
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

127
board/gdsys/common/miiphybb.c
View File

@@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#include <common.h>
#include <miiphy.h>
#include <asm/io.h>
struct io_bb_pinset {
int mdio;
int mdc;
};
static int io_bb_mii_init(struct bb_miiphy_bus *bus)
{
return 0;
}
static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct io_bb_pinset *pins = bus->priv;
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) | pins->mdio);
return 0;
}
static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct io_bb_pinset *pins = bus->priv;
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) & ~pins->mdio);
return 0;
}
static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct io_bb_pinset *pins = bus->priv;
if (v)
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | pins->mdio);
else
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~pins->mdio);
return 0;
}
static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct io_bb_pinset *pins = bus->priv;
*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
return 0;
}
static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct io_bb_pinset *pins = bus->priv;
if (v)
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | pins->mdc);
else
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~pins->mdc);
return 0;
}
static int io_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(1);
return 0;
}
struct io_bb_pinset io_bb_pinsets[] = {
{
.mdio = CONFIG_SYS_MDIO_PIN,
.mdc = CONFIG_SYS_MDC_PIN,
},
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
{
.mdio = CONFIG_SYS_MDIO1_PIN,
.mdc = CONFIG_SYS_MDC1_PIN,
},
#endif
};
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = CONFIG_SYS_GBIT_MII_BUSNAME,
.init = io_bb_mii_init,
.mdio_active = io_bb_mdio_active,
.mdio_tristate = io_bb_mdio_tristate,
.set_mdio = io_bb_set_mdio,
.get_mdio = io_bb_get_mdio,
.set_mdc = io_bb_set_mdc,
.delay = io_bb_delay,
.priv = &io_bb_pinsets[0],
},
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
{
.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
.init = io_bb_mii_init,
.mdio_active = io_bb_mdio_active,
.mdio_tristate = io_bb_mdio_tristate,
.set_mdio = io_bb_set_mdio,
.get_mdio = io_bb_get_mdio,
.set_mdc = io_bb_set_mdc,
.delay = io_bb_delay,
.priv = &io_bb_pinsets[1],
},
#endif
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);

4
board/gdsys/common/osd.c
View File

@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <i2c.h>
#include <malloc.h>
@@ -497,3 +499,5 @@ U_BOOT_CMD(
"size_x(max. " __stringify(MAX_X_CHARS)
") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
);
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

2
board/gdsys/common/phy.c
View File

@@ -45,8 +45,6 @@ struct mii_setupcmd fixup_88e1518[] = {
{ MIICMD_SET, 16, 0x214d },
{ MIICMD_SET, 17, 0xcc0c },
{ MIICMD_SET, 16, 0x2159 },
{ MIICMD_SET, 22, 0x00fb },
{ MIICMD_SET, 7, 0xc00d },
{ MIICMD_SET, 22, 0x0000 },
};

83
board/gdsys/mpc8308/Kconfig
View File

@@ -4,6 +4,35 @@ config GDSYS_LEGACY_OSD_CMDS
Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
gdsys devices.
config GDSYS_LEGACY_DRIVERS
bool
help
Enable the gdsys legacy drivers under board/gdsys/common. If this
option is not set, all relevant DM drivers must be configured for the
device in question.
config SYS_FPGA0_BASE
hex
default E0600000
help
The base address of the first FPGA's register map.
config SYS_FPGA0_SIZE
hex
default 1
help
The base address of the first FPGA's register map.
config SYS_FPGA1_BASE
hex
help
The base address of the second FPGA's register map.
config SYS_FPGA1_SIZE
hex
help
The base address of the second FPGA's register map.
if TARGET_HRCON
config SYS_BOARD
@@ -18,6 +47,9 @@ config SYS_CONFIG_NAME
config GDSYS_LEGACY_OSD_CMDS
default y
config GDSYS_LEGACY_DRIVERS
default y
endif
if TARGET_STRIDER
@@ -33,9 +65,60 @@ config SYS_CONFIG_NAME
config GDSYS_LEGACY_OSD_CMDS
default y
config GDSYS_LEGACY_DRIVERS
default y
endif
if TARGET_GAZERBEAM
config SYS_BOARD
default "mpc8308"
config SYS_VENDOR
default "gdsys"
config SYS_CONFIG_NAME
default "gazerbeam"
config SYS_FPGA1_BASE
default E0700000
config SYS_FPGA1_SIZE
default 1
config GDSYS_LEGACY_OSD_CMDS
default y
endif
if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
choice
prompt "FPGA flavor selection"
config SYS_FPGA_FLAVOR_LEGACY
bool "Legacy flavor"
help
This enables support for the gdsys pre-Gazerbeam FPGA memory layout.
config SYS_FPGA_FLAVOR_GAZERBEAM
bool "Gazerbeam flavor"
help
This enables support for the gdsys FPGA memory layout of the
Gazerbeam board.
endchoice
config EXTENDED_FEATURES
bool "FPGA extended features"
depends on GDSYS_LEGACY_DRIVERS
help
Enable support for the extended features field of the IHS FPGA.
config CMD_IOLOOP
bool "Enable 'ioloop' and 'ioreflect' commands"
help
These commands provide FPGA tests.
endif

2
board/gdsys/mpc8308/MAINTAINERS
View File

@@ -6,7 +6,9 @@ F: include/configs/hrcon.h
F: configs/hrcon_defconfig
F: configs/hrcon_dh_defconfig
F: include/configs/strider.h
F: configs/strider_defconfig
F: configs/strider_cpu_defconfig
F: configs/strider_cpu_dp_defconfig
F: configs/strider_con_defconfig
F: configs/strider_con_dp_defconfig
F: configs/gazerbeam_defconfig

5
board/gdsys/mpc8308/Makefile
View File

@@ -4,5 +4,6 @@
# Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
obj-y := mpc8308.o sdram.o
obj-$(CONFIG_HRCON) += hrcon.o
obj-$(CONFIG_STRIDER) += strider.o
obj-$(CONFIG_TARGET_HRCON) += hrcon.o
obj-$(CONFIG_TARGET_STRIDER) += strider.o
obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o

179
board/gdsys/mpc8308/gazerbeam.c Normal file
View File

@@ -0,0 +1,179 @@
/*
* (C) Copyright 2015
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <board.h>
#include <dm.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <misc.h>
#include <tpm-v1.h>
#include <video_osd.h>
#include "../common/ihs_mdio.h"
#include "../../../drivers/board/gazerbeam.h"
DECLARE_GLOBAL_DATA_PTR;
struct ihs_mdio_info ihs_mdio_info[] = {
{ .fpga = NULL, .name = "ihs0", .base = 0x58 },
{ .fpga = NULL, .name = "ihs1", .base = 0x58 },
};
static int get_tpm(struct udevice **devp)
{
int rc;
rc = uclass_first_device_err(UCLASS_TPM, devp);
if (rc) {
printf("Could not find TPM (ret=%d)\n", rc);
return CMD_RET_FAILURE;
}
return 0;
}
int board_early_init_r(void)
{
struct udevice *board;
struct udevice *serdes;
int mc = 0;
int con = 0;
if (board_get(&board))
puts("Could not find board information device.\n");
/* Initialize serdes */
uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
if (board_detect(board))
puts("Device information detection failed.\n");
board_get_int(board, BOARD_MULTICHANNEL, &mc);
board_get_int(board, BOARD_VARIANT, &con);
if (mc == 2 || mc == 1)
dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
if (mc == 4) {
dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
dev_enable_by_path("/fpga1bus");
}
if (mc == 2 || con == VAR_CON) {
dev_enable_by_path("/fpga0bus/fpga0_video1");
dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
}
if (con == VAR_CON) {
dev_enable_by_path("/fpga0bus/fpga0_video0");
dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
}
return 0;
}
int checkboard(void)
{
struct udevice *board;
char *s = env_get("serial#");
int mc = 0;
int con = 0;
if (board_get(&board))
puts("Could not find board information device.\n");
board_get_int(board, BOARD_MULTICHANNEL, &mc);
board_get_int(board, BOARD_VARIANT, &con);
puts("Board: Gazerbeam ");
printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
printf("%s", con == VAR_CON ? "CON" : "CPU");
if (s) {
puts(", serial# ");
puts(s);
}
puts("\n");
return 0;
}
static void display_osd_info(struct udevice *osd,
struct video_osd_info *osd_info)
{
printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
osd->name, osd_info->major_version, osd_info->minor_version,
osd_info->width, osd_info->height);
}
int last_stage_init(void)
{
int fpga_hw_rev = 0;
int i;
struct udevice *board;
struct udevice *osd;
struct video_osd_info osd_info;
struct udevice *tpm;
int ret;
if (board_get(&board))
puts("Could not find board information device.\n");
if (board) {
int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
if (res)
printf("Could not determind FPGA HW revision (res = %d)\n", res);
}
env_set_ulong("fpga_hw_rev", fpga_hw_rev);
ret = get_tpm(&tpm);
if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
tpm_continue_self_test(tpm)) {
printf("TPM init failed\n");
}
if (fpga_hw_rev >= 4) {
for (i = 0; i < 4; i++) {
struct udevice *rxaui;
char name[8];
snprintf(name, sizeof(name), "rxaui%d", i);
/* Disable RXAUI polarity inversion */
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
if (!ret)
misc_set_enabled(rxaui, false);
}
}
for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
osd;
uclass_next_device(&osd)) {
video_osd_get_info(osd, &osd_info);
display_osd_info(osd, &osd_info);
}
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
}
#endif

55
board/gdsys/mpc8308/hrcon.c
View File

@@ -35,11 +35,11 @@
#define MAX_MUX_CHANNELS 2
enum {
MCFPGA_DONE = 1 << 0,
MCFPGA_INIT_N = 1 << 1,
MCFPGA_PROGRAM_N = 1 << 2,
MCFPGA_UPDATE_ENABLE_N = 1 << 3,
MCFPGA_RESET_N = 1 << 4,
MCFPGA_DONE = BIT(0),
MCFPGA_INIT_N = BIT(1),
MCFPGA_PROGRAM_N = BIT(2),
MCFPGA_UPDATE_ENABLE_N = BIT(3),
MCFPGA_RESET_N = BIT(4),
};
enum {
@@ -47,7 +47,7 @@ enum {
GPIO_MDIO = 1 << 15,
};
unsigned int mclink_fpgacount;
uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
@@ -107,7 +107,7 @@ int checkboard(void)
printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
if (s != NULL) {
if (s) {
puts(", serial# ");
puts(s);
}
@@ -120,12 +120,11 @@ int checkboard(void)
int last_stage_init(void)
{
int slaves;
unsigned int k;
unsigned int mux_ch;
unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
uint k;
uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
u16 fpga_features;
bool hw_type_cat = pca9698_get_value(0x20, 20);
bool ch0_rgmii2_present = false;
bool ch0_rgmii2_present;
FPGA_GET_REG(0, fpga_features, &fpga_features);
@@ -137,16 +136,16 @@ int last_stage_init(void)
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
uint ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
printf("no done for mclink_controller %u\n", k);
break;
}
}
@@ -159,8 +158,10 @@ int last_stage_init(void)
}
if (hw_type_cat) {
uint mux_ch;
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
@@ -179,7 +180,7 @@ int last_stage_init(void)
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
@@ -207,6 +208,7 @@ int last_stage_init(void)
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
@@ -233,17 +235,17 @@ int last_stage_init(void)
* provide access to fpga gpios and controls (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
void fpga_gpio_set(unsigned int bus, int pin)
void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
}
void fpga_gpio_clear(unsigned int bus, int pin)
void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
}
int fpga_gpio_get(unsigned int bus, int pin)
int fpga_gpio_get(uint bus, int pin)
{
u16 val;
@@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
return val & pin;
}
void fpga_control_set(unsigned int bus, int pin)
void fpga_control_set(uint bus, int pin)
{
u16 val;
@@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin)
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
}
void fpga_control_clear(unsigned int bus, int pin)
void fpga_control_clear(uint bus, int pin)
{
u16 val;
@@ -273,7 +275,7 @@ void mpc8308_init(void)
pca9698_direction_output(0x20, 4, 1);
}
void mpc8308_set_fpga_reset(unsigned state)
void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 4, state ? 0 : 1);
}
@@ -285,11 +287,11 @@ void mpc8308_setup_hw(void)
/*
* set "startup-finished"-gpios
*/
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
setbits_gpio0_out(BIT(31 - 12));
}
int mpc8308_get_fpga_done(unsigned fpga)
int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 19);
}
@@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd)
*/
struct fpga_mii {
unsigned fpga;
uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
@@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
},
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

33
board/gdsys/mpc8308/mpc8308.c
View File

@@ -24,14 +24,34 @@
DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev)
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/* as gpio output status cannot be read back, we have to buffer it locally */
u32 gpio0_out;
void setbits_gpio0_out(u32 mask)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
gpio0_out |= mask;
out_be32(&immr->gpio[0].dat, gpio0_out);
}
void clrbits_gpio0_out(u32 mask)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
gpio0_out &= ~mask;
out_be32(&immr->gpio[0].dat, gpio0_out);
}
int get_fpga_state(uint dev)
{
return gd->arch.fpga_state[dev];
}
int board_early_init_f(void)
{
unsigned k;
uint k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
@@ -41,8 +61,8 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
unsigned k;
unsigned ctr;
uint k;
uint ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
@@ -59,7 +79,7 @@ int board_early_init_r(void)
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ctr = 0;
while (!mpc8308_get_fpga_done(k)) {
udelay(100000);
mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_DONE_FAILED;
@@ -86,7 +106,7 @@ int board_early_init_r(void)
if (val == REFLECTION_TESTPATTERN_INV)
break;
udelay(100000);
mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
@@ -97,3 +117,4 @@ int board_early_init_r(void)
return 0;
}
#endif

3
board/gdsys/mpc8308/mpc8308.h
View File

@@ -1,6 +1,9 @@
#ifndef __MPC8308_H_
#define __MPC8308_H_
void setbits_gpio0_out(u32 mask);
void clrbits_gpio0_out(u32 mask);
/* functions to be provided by board implementation */
void mpc8308_init(void);
void mpc8308_set_fpga_reset(unsigned state);

8
board/gdsys/mpc8308/sdram.c
View File

@@ -11,6 +11,8 @@
* board\freescale\mpc8315erdb\sdram.c
*/
#ifndef CONFIG_MPC83XX_SDRAM
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
@@ -34,7 +36,7 @@ static long fixed_sdram(void)
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -62,7 +64,7 @@ static long fixed_sdram(void)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
@@ -81,3 +83,5 @@ int dram_init(void)
return 0;
}
#endif /* !CONFIG_MPC83XX_SDRAM */

49
board/gdsys/mpc8308/strider.c
View File

@@ -50,7 +50,7 @@ enum {
GPIO_MDIO = 1 << 15,
};
unsigned int mclink_fpgacount;
uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
@@ -110,7 +110,7 @@ int checkboard(void)
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
if (s != NULL) {
if (s) {
puts(", serial# ");
puts(s);
}
@@ -123,17 +123,17 @@ int checkboard(void)
int last_stage_init(void)
{
int slaves;
unsigned int k;
unsigned int mux_ch;
unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
uint k;
uint mux_ch;
uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
#ifdef CONFIG_STRIDER_CPU
unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
#ifdef CONFIG_STRIDER_CON_DP
bool is_dh = pca9698_get_value(0x20, 25);
#endif
bool ch0_sgmii2_present = false;
bool ch0_sgmii2_present;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
@@ -146,8 +146,8 @@ int last_stage_init(void)
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
unsigned int ctr = 0;
unsigned char *mclink_controllers = mclink_controllers_dvi;
uint ctr = 0;
uchar *mclink_controllers = mclink_controllers_dvi;
#ifdef CONFIG_STRIDER_CPU
if (i2c_probe(mclink_controllers[k])) {
@@ -161,7 +161,7 @@ int last_stage_init(void)
#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
@@ -178,6 +178,7 @@ int last_stage_init(void)
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
@@ -196,7 +197,7 @@ int last_stage_init(void)
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
@@ -235,7 +236,7 @@ int last_stage_init(void)
for (k = 1; k <= slaves; ++k)
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
udelay(500000);
mdelay(500);
#endif
for (k = 1; k <= slaves; ++k) {
@@ -260,6 +261,7 @@ int last_stage_init(void)
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
@@ -286,17 +288,17 @@ int last_stage_init(void)
* provide access to fpga gpios (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
void fpga_gpio_set(unsigned int bus, int pin)
void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.set, pin);
}
void fpga_gpio_clear(unsigned int bus, int pin)
void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.clear, pin);
}
int fpga_gpio_get(unsigned int bus, int pin)
int fpga_gpio_get(uint bus, int pin)
{
u16 val;
@@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
}
#ifdef CONFIG_STRIDER_CON_DP
void fpga_control_set(unsigned int bus, int pin)
void fpga_control_set(uint bus, int pin)
{
u16 val;
@@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin)
FPGA_SET_REG(bus, control, val | pin);
}
void fpga_control_clear(unsigned int bus, int pin)
void fpga_control_clear(uint bus, int pin)
{
u16 val;
@@ -328,7 +330,7 @@ void mpc8308_init(void)
pca9698_direction_output(0x20, 26, 1);
}
void mpc8308_set_fpga_reset(unsigned state)
void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 26, state ? 0 : 1);
}
@@ -340,11 +342,11 @@ void mpc8308_setup_hw(void)
/*
* set "startup-finished"-gpios
*/
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
setbits_gpio0_out(BIT(31 - 12));
}
int mpc8308_get_fpga_done(unsigned fpga)
int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 20);
}
@@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd)
*/
struct fpga_mii {
unsigned fpga;
uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
@@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
},
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

10
board/gdsys/p1022/Kconfig
View File

@@ -1,3 +1,10 @@
config GDSYS_LEGACY_DRIVERS
bool
help
Enable the gdsys legacy drivers under board/gdsys/common. If this
option is not set, all relevant DM drivers must be configured for the
device in question.
if TARGET_CONTROLCENTERD
config SYS_BOARD
@@ -9,4 +16,7 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "controlcenterd"
config GDSYS_LEGACY_DRIVERS
default y
endif

8
board/ids/ids8313/ids8313.c
View File

@@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
sync();
@@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/* now check the real size */
disable_addr_trans();
msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
#endif
return msize;
@@ -129,8 +129,8 @@ int dram_init(void)
msize = setup_sdram();
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
out_be32(&lbc->mrtpr, 0x20000000);
sync();
gd->ram_size = msize;

95
board/keymile/km83xx/Kconfig
View File

@@ -1,4 +1,4 @@
if TARGET_KM8360
if TARGET_KMETER1
config SYS_BOARD
default "km83xx"
@@ -7,7 +7,46 @@ config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "km8360"
default "kmeter1"
endif
if TARGET_KMCOGE5NE
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmcoge5ne"
endif
if TARGET_KMVECT1
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmvect1"
endif
if TARGET_KMTEGR1
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmtegr1"
endif
@@ -36,3 +75,55 @@ config SYS_CONFIG_NAME
default "tuxx1"
endif
if TARGET_KMSUPX5
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmsupx5"
endif
if TARGET_TUGE1
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "tuge1"
endif
if TARGET_KMOPTI2
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmopti2"
endif
if TARGET_KMTEPR2
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmtepr2"
endif

12
board/keymile/km83xx/km83xx.c
View File

@@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
@@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
#elif !defined(CONFIG_MPC8309)
#elif !defined(CONFIG_ARCH_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
@@ -148,7 +148,7 @@ int board_early_init_r(void)
u32 *mxmr = &lbc->mamr;
#endif
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved
@@ -271,7 +271,7 @@ int last_stage_init(void)
}
#endif
#if defined(CONFIG_KMCOGE5NE)
#if defined(CONFIG_TARGET_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
@@ -311,7 +311,7 @@ static int fixed_sdram(void)
msize = CONFIG_SYS_DDR_SIZE << 20;
disable_addr_trans();
msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
msize /= (1024 * 1024);
if (CONFIG_SYS_DDR_SIZE != msize) {
@@ -338,7 +338,7 @@ int dram_init(void)
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)

4
board/mpc8308_p1m/sdram.c
View File

@@ -29,7 +29,7 @@ static long fixed_sdram(void)
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -57,7 +57,7 @@ static long fixed_sdram(void)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)

35
board/sbc8349/sbc8349.c
View File

@@ -45,7 +45,7 @@ int dram_init(void)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
@@ -79,19 +79,19 @@ int fixed_sdram(void)
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
@@ -147,6 +147,9 @@ void sdram_init(void)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
LSDMR_WRC3 | LSDMR_CL3;
puts("\n SDRAM on Local Bus: ");
print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@@ -156,22 +159,27 @@ void sdram_init(void)
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->lbcr = 0x00000000;
/* LB refresh timer prescal, 266MHz/32 */
lbc->mrtpr = 0x20000000;
/* LB sdram refresh timer, about 6us */
lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
/* 0x68636733; precharge all the banks */
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
/* 0x48636733; auto refresh */
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -199,12 +207,13 @@ void sdram_init(void)
udelay(100);
/* 0x58636733; mode register write operation */
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);

2
board/tqc/tqm834x/pci.c
View File

@@ -71,7 +71,7 @@ pci_init_board(void)
reg32 = 0xff000000;
#endif
if (clk->spmr & SPMR_CKID) {
/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
/* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);

10
board/tqc/tqm834x/tqm834x.c
View File

@@ -72,13 +72,13 @@ int dram_init(void)
int cs;
/* during size detection, set up the max DDRLAW size */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */
for(cs = 0; cs < 4; ++cs) {
set_cs_bounds(cs,
CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG);
@@ -102,7 +102,7 @@ int dram_init(void)
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
(long *)(CONFIG_SYS_DDR_BASE + size));
(long *)(CONFIG_SYS_SDRAM_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
@@ -235,8 +235,8 @@ static int detect_num_flash_banks(void)
debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
/* set OR0 and BR0 */
set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM));
set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V));

14
board/ve8313/ve8313.c
View File

@@ -38,7 +38,7 @@ static long fixed_sdram(void)
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -48,12 +48,12 @@ static long fixed_sdram(void)
*/
__udelay(50000);
#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
out_be32(&im->ddr.csbnds[0].csbnds,
((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA));
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
@@ -80,7 +80,7 @@ static long fixed_sdram(void)
/* now check the real size */
disable_addr_trans ();
msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans ();
#endif
@@ -100,8 +100,8 @@ int dram_init(void)
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
out_be32(&lbc->lbcr, 0x00040000);
out_be32(&lbc->mrtpr, 0x20000000);
sync();
/* return total bus SDRAM size(bytes) -- DDR */