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phy: marvell: a3700: Set USB3 RX wait depending on ref clock

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According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Marek Behún 2018-04-24 17:21:19 +02:00 committed by Stefan Roese
parent 8609358261
commit de49bd0e73
1 changed files with 3 additions and 5 deletions
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8
drivers/phy/marvell/comphy_a3700.c
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@ -382,20 +382,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
/* /*
* 3. Check crystal jumper setting and program the Power and PLL * 3. Check crystal jumper setting and program the Power and PLL
* Control accordingly * Control accordingly
* 4. Change RX wait
*/ */
if (get_ref_clk() == 40) { if (get_ref_clk() == 40) {
/* 40 MHz */ /* 40 MHz */
usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
} else { } else {
/* 25 MHz */ /* 25 MHz */
usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
} }
/*
* 4. Change RX wait
*/
usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
/* /*
* 5. Enable idle sync * 5. Enable idle sync
*/ */