phy: marvell: a3700: Access USB3 register indirectly on lane 2
When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. This is the case of the Turris Mox board from CZ.NIC. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Marek Behún
Stefan Roese
parent
a2745c8803
commit
8609358261
@ -132,7 +132,7 @@ static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
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*/
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static int comphy_pcie_power_up(u32 speed, u32 invert)
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{
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int ret;
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int ret;
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debug_enter();
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@ -299,14 +299,36 @@ static int comphy_sata_power_up(void)
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return ret;
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}
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/*
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* usb3_reg_set16
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*
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* return: void
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*/
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static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)
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{
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/*
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* When Lane 2 PHY is for USB3, access the PHY registers
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* through indirect Address and Data registers INDIR_ACC_PHY_ADDR
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* (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
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* within the SATA Host Controller registers, Lane 2 base register
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* offset is 0x200
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*/
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if (lane == 2)
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reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,
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mask);
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else
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reg_set16(phy_addr(USB3, reg), data, mask);
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}
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/*
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* comphy_usb3_power_up
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*
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* return: 1 if PLL locked (OK), 0 otherwise (FAIL)
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*/
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static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
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static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
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{
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int ret;
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int ret;
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debug_enter();
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@ -324,39 +346,38 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
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/* 0xd005c300 = 0x1001 */
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/* set PRD_TXDEEMPH (3.5db de-emph) */
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reg_set16(phy_addr(USB3, LANE_CFG0), 0x1, 0xFF);
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usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
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/*
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* unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
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* low impedance mode during electrical idle
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* low impedance mode during electrical idle
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* unset BIT4: set G2 Tx Datapath with no Delayed Latency
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* unset BIT6: set Tx Detect Rx Mode at LoZ mode
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*/
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/* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
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/* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
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reg_set16(phy_addr(USB3, LANE_CFG1), 0x0, 0xFFFF);
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usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF, lane);
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/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
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reg_set16(phy_addr(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80);
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/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
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usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
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/*
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* set Override Margining Controls From the MAC: Use margining signals
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* from lane configuration
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*/
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reg_set16(phy_addr(USB3, TEST_MODE_CTRL), rb_mode_margin_override,
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0xFFFF);
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usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);
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/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
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/* set Mode Clock Source = PCLK is generated from REFCLK */
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reg_set16(phy_addr(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF);
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usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);
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/* set G2 Spread Spectrum Clock Amplitude at 4K */
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reg_set16(phy_addr(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000);
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usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);
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/*
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* unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
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* Master Current Select
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*/
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reg_set16(phy_addr(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF);
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usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);
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/*
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* 3. Check crystal jumper setting and program the Power and PLL
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@ -364,62 +385,72 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
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*/
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if (get_ref_clk() == 40) {
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/* 40 MHz */
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reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF);
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usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
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} else {
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/* 25 MHz */
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reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF);
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usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
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}
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/*
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* 4. Change RX wait
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*/
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reg_set16(phy_addr(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF);
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usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
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/*
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* 5. Enable idle sync
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*/
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reg_set16(phy_addr(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
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usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);
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/*
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* 6. Enable the output of 500M clock
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*/
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reg_set16(phy_addr(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF);
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usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);
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/*
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* 7. Set 20-bit data width
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*/
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reg_set16(phy_addr(USB3, DIG_LB_EN), 0x0400, 0xFFFF);
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usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);
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/*
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* 8. Override Speed_PLL value and use MAC PLL
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*/
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reg_set16(phy_addr(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
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0xFFFF);
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usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF,
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lane);
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/*
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* 9. Check the Polarity invert bit
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*/
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if (invert & PHY_POLARITY_TXD_INVERT)
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reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_txd_inv, 0);
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usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
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if (invert & PHY_POLARITY_RXD_INVERT)
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reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_rxd_inv, 0);
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usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
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/*
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* 10. Release SW reset
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*/
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reg_set16(phy_addr(USB3, GLOB_PHY_CTRL0),
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rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,
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0xFFFF);
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usb3_reg_set16(GLOB_PHY_CTRL0,
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rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
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| 0x20, 0xFFFF, lane);
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/* Wait for > 55 us to allow PCLK be enabled */
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udelay(PLL_SET_DELAY_US);
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/* Assert PCLK enabled */
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ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
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rb_txdclk_pclk_en, /* value */
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rb_txdclk_pclk_en, /* mask */
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POLL_16B_REG); /* 16bit */
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if (lane == 2) {
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reg_set(rh_vsreg_addr,
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LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET,
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0xFFFFFFFF);
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ret = comphy_poll_reg(rh_vsreg_data, /* address */
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rb_txdclk_pclk_en, /* value */
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rb_txdclk_pclk_en, /* mask */
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POLL_32B_REG); /* 32bit */
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} else {
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ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
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rb_txdclk_pclk_en, /* value */
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rb_txdclk_pclk_en, /* mask */
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POLL_16B_REG); /* 16bit */
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}
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if (!ret)
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printf("Failed to lock USB3 PLL\n");
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@ -455,7 +486,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
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*/
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static int comphy_usb2_power_up(u8 usb32)
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{
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int ret;
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int ret;
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debug_enter();
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@ -620,7 +651,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
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*/
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static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
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{
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int ret;
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int ret;
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debug_enter();
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@ -906,7 +937,8 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
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case PHY_TYPE_USB3_HOST0:
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case PHY_TYPE_USB3_DEVICE:
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ret = comphy_usb3_power_up(comphy_map->type,
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ret = comphy_usb3_power_up(lane,
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comphy_map->type,
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comphy_map->speed,
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comphy_map->invert);
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break;
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@ -59,6 +59,7 @@
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#define USB2PHY2_BASE MVEBU_REG(0x05F000)
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#define USB32_CTRL_BASE MVEBU_REG(0x05D800)
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#define USB3PHY_SHFT 2
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#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200
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static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr)
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{
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