Enable Icache
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
John Rigby
parent
b9bf3de377
commit
ddd104f1ed
@ -31,7 +31,6 @@
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#define _START _start
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#define _FAULT _fault
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#define SAVE_ALL \
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move.w #0x2700,%sr; /* disable intrs */ \
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subl #60,%sp; /* space for 15 regs */ \
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@ -42,7 +41,6 @@
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addl #60,%sp; /* space for 15 regs */ \
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rte;
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.text
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/*
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* Vector table. This is used for initial platform startup.
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@ -50,35 +48,35 @@
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*/
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_vectors:
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INITSP: .long 0x00000000 /* Initial SP */
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INITPC: .long _START /* Initial PC */
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vector02: .long _FAULT /* Access Error */
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vector03: .long _FAULT /* Address Error */
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vector04: .long _FAULT /* Illegal Instruction */
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vector05: .long _FAULT /* Reserved */
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vector06: .long _FAULT /* Reserved */
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vector07: .long _FAULT /* Reserved */
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vector08: .long _FAULT /* Privilege Violation */
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vector09: .long _FAULT /* Trace */
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vector0A: .long _FAULT /* Unimplemented A-Line */
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vector0B: .long _FAULT /* Unimplemented F-Line */
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vector0C: .long _FAULT /* Debug Interrupt */
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vector0D: .long _FAULT /* Reserved */
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vector0E: .long _FAULT /* Format Error */
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vector0F: .long _FAULT /* Unitialized Int. */
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INITSP: .long 0x00000000 /* Initial SP */
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INITPC: .long _START /* Initial PC */
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vector02: .long _FAULT /* Access Error */
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vector03: .long _FAULT /* Address Error */
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vector04: .long _FAULT /* Illegal Instruction */
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vector05: .long _FAULT /* Reserved */
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vector06: .long _FAULT /* Reserved */
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vector07: .long _FAULT /* Reserved */
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vector08: .long _FAULT /* Privilege Violation */
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vector09: .long _FAULT /* Trace */
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vector0A: .long _FAULT /* Unimplemented A-Line */
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vector0B: .long _FAULT /* Unimplemented F-Line */
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vector0C: .long _FAULT /* Debug Interrupt */
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vector0D: .long _FAULT /* Reserved */
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vector0E: .long _FAULT /* Format Error */
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vector0F: .long _FAULT /* Unitialized Int. */
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/* Reserved */
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/* Reserved */
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vector10_17:
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.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
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vector18: .long _FAULT /* Spurious Interrupt */
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vector19: .long _FAULT /* Autovector Level 1 */
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vector1A: .long _FAULT /* Autovector Level 2 */
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vector1B: .long _FAULT /* Autovector Level 3 */
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vector1C: .long _FAULT /* Autovector Level 4 */
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vector1D: .long _FAULT /* Autovector Level 5 */
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vector1E: .long _FAULT /* Autovector Level 6 */
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vector1F: .long _FAULT /* Autovector Level 7 */
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vector18: .long _FAULT /* Spurious Interrupt */
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vector19: .long _FAULT /* Autovector Level 1 */
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vector1A: .long _FAULT /* Autovector Level 2 */
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vector1B: .long _FAULT /* Autovector Level 3 */
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vector1C: .long _FAULT /* Autovector Level 4 */
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vector1D: .long _FAULT /* Autovector Level 5 */
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vector1E: .long _FAULT /* Autovector Level 6 */
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vector1F: .long _FAULT /* Autovector Level 7 */
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/* TRAP #0 - #15 */
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vector20_2F:
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@ -126,9 +124,9 @@ vector192_255:
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_start:
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nop
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nop
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move.w #0x2700,%sr /* Mask off Interrupt */
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move.w #0x2700,%sr /* Mask off Interrupt */
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/* Set vector base register at the beginning of the Flash */
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/* Set vector base register at the beginning of the Flash */
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move.l #CFG_FLASH_BASE, %d0
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movec %d0, %VBR
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@ -149,14 +147,15 @@ _start:
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move.l %d0, (%a1)
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move.l %d0, (%a2)
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/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
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/* set stackpointer to end of internal ram to get some stackspace for the
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first c-code */
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move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
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clr.l %sp@-
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move.l #__got_start, %a5 /* put relocation table address to a5 */
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move.l #__got_start, %a5 /* put relocation table address to a5 */
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bsr cpu_init_f /* run low-level CPU init code (from flash) */
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bsr board_init_f /* run low-level board init code (from flash) */
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bsr cpu_init_f /* run low-level CPU init code (from flash) */
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bsr board_init_f /* run low-level board init code (from flash) */
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/* board_init_f() does not return */
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@ -269,14 +268,14 @@ _int_handler:
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icache_enable:
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move.l #0x01000000, %d0 /* Invalidate cache cmd */
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movec %d0, %CACR /* Invalidate cache */
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move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
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move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
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movec %d0, %ACR0 /* Enable cache */
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move.l #(CFG_CS0_BASE + 0xc000), %d0 /* Setup cache mask */
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move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */
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movec %d0, %ACR1 /* Enable cache */
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/*move.l #0x81000100, %d0*/ /* Setup cache mask */
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move.l #0x81000100, %d0 /* Setup cache mask */
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move.l #0x80000200, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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nop
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move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
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moveq #1, %d0
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@ -304,7 +303,7 @@ icache_status:
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.globl icache_invalid
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icache_invalid:
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move.l #0x00000100, %d0 /* Setup cache mask */
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move.l #0x01000000, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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rts
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