Merge branch '2019-05-19-master-imports'

- Convert SYS_[DI]CACHE_OFF to Kconfig, introduce SPL variant.
- Various bcm96* fixes.
- Import include/android_bootloader_message.h from AOSP
- Assorted other small fixes.

Kconfig

@@ -278,7 +278,7 @@ config FIT
 if FIT
 
 config FIT_EXTERNAL_OFFSET
-	hex "Text Base"
+	hex "FIT external data offset"
 	default 0x0
 	help
 	  This specifies a data offset in fit image.

Makefile

@@ -1071,7 +1071,7 @@ ifneq ($(EXT_DTB),)
 u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
 		$(call if_changed,cat)
 else
-u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob $(FINAL_DTB_CONTAINER)
 	$(call if_changed,cat)
 endif
 

README

@@ -634,8 +634,6 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration:
-		CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
-		CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
 		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
 
 - Cache Configuration for ARM:

arch/arc/Kconfig

@@ -109,12 +109,30 @@ config CPU_BIG_ENDIAN
 	  Build kernel for Big Endian Mode of ARC CPU
 
 config SYS_ICACHE_OFF
-	bool "Do not use Instruction Cache"
+	bool "Do not enable icache"
 	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
 
 config SYS_DCACHE_OFF
-	bool "Do not use Data Cache"
+	bool "Do not enable dcache"
 	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
 
 menuconfig ARC_DBG
 	bool "ARC debugging"

arch/arc/lib/start.S

@@ -16,7 +16,7 @@ ENTRY(_start)
 	lr	r5, [ARC_BCR_IC_BUILD]
 	breq	r5, 0, 1f		; I$ doesn't exist
 	lr	r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	bclr	r5, r5, 0		; 0 - Enable, 1 is Disable
 #else
 	bset	r5, r5, 0		; I$ exists, but is not used
@@ -37,7 +37,7 @@ ENTRY(_start)
 	breq	r5, 0, 1f		; D$ doesn't exist
 	lr	r5, [ARC_AUX_DC_CTRL]
 	bclr	r5, r5, 6		; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	bclr	r5, r5, 0		; Enable (+Inv)
 #else
 	bset	r5, r5, 0		; Disable (+Inv)

arch/arm/Kconfig

@@ -74,6 +74,32 @@ config ARM_ASM_UNIFIED
 config THUMB2_KERNEL
 	bool
 
+config SYS_ICACHE_OFF
+	bool "Do not enable icache"
+	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+	bool "Do not enable dcache"
+	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
 config SYS_ARM_CACHE_CP15
 	bool "CP15 based cache enabling support"
 	help

arch/arm/cpu/arm11/cpu.c

@@ -51,7 +51,7 @@ static void cache_flush(void)
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
 	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -95,15 +95,15 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	dcache_enable();
 #endif
 }

arch/arm/cpu/arm926ejs/cache.c

@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
 	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
 	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -54,7 +54,7 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {}
 __weak void invalidate_l2_cache(void) {}
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {
@@ -80,10 +80,10 @@ void invalidate_icache_all(void) {}
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	dcache_enable();
 #endif
 }

arch/arm/cpu/arm926ejs/cpu.c

@@ -44,7 +44,7 @@ int cleanup_before_linux (void)
 /* flush I/D-cache */
 static void cache_flush (void)
 {
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 	unsigned long i = 0;
 
 	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));

arch/arm/cpu/arm926ejs/start.S

@@ -84,7 +84,7 @@ flush_dcache:
 
 	/*
 	 * disable MMU and D cache
-	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+	 * enable I cache if SYS_ICACHE_OFF is not defined
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@ flush_dcache:
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
 #endif
 	orr	r0, r0, #0x00000002	/* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 #endif
 	mcr	p15, 0, r0, c1, c0, 0

arch/arm/cpu/armv7/cache_v7.c

@@ -12,7 +12,7 @@
 #define ARMV7_DCACHE_INVAL_RANGE	1
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	2
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /* Asm functions from cache_v7_asm.S */
 void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 	flush_dcache_range(start, stop);
 	v7_inval_tlb();
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void arm_init_domains(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {

arch/arm/cpu/armv7/iproc-common/hwinit-common.c

@@ -5,7 +5,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/cpu/armv7/kona-common/hwinit-common.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <linux/sizes.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -26,7 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  * Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@ void enable_caches(void)
 	invalidate_dcache_all();
 	set_cr(get_cr() | CR_C);
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 
 uint get_svr(void)

arch/arm/cpu/armv7/start.S

@@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
  */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c5, 4	@ ISB
@@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15)
 	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
 	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
 	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
 #else
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache

arch/arm/cpu/armv7/vf610/generic.c

@@ -360,7 +360,7 @@ int get_clocks(void)
 	return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

arch/arm/cpu/armv7m/cache.c

@@ -54,7 +54,7 @@ enum cache_action {
 	FLUSH_INVAL_SET_WAY,	/* d-cache clean & invalidate by set/ways */
 };
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 struct dcache_config {
 	u32 ways;
 	u32 sets;
@@ -292,7 +292,7 @@ void invalidate_dcache_all(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void invalidate_icache_all(void)
 {
@@ -349,10 +349,10 @@ int icache_status(void)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	dcache_enable();
 #endif
 }

arch/arm/cpu/armv8/cache_v8.c

@@ -13,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  *  With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
 	__asm_invalidate_tlb_all();
 }
 
-#else	/* CONFIG_SYS_DCACHE_OFF */
+#else	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 {
 }
 
-#endif	/* CONFIG_SYS_DCACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void icache_enable(void)
 {
@@ -720,7 +720,7 @@ void invalidate_icache_all(void)
 	__asm_invalidate_l3_icache();
 }
 
-#else	/* CONFIG_SYS_ICACHE_OFF */
+#else	/* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 void icache_enable(void)
 {
@@ -739,7 +739,7 @@ void invalidate_icache_all(void)
 {
 }
 
-#endif	/* CONFIG_SYS_ICACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 /*
  * Enable dCache & iCache, whether cache is actually enabled

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -388,7 +388,7 @@ void cpu_name(char *name)
 		strcpy(name, "unknown");
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@ void enable_caches(void)
 	icache_enable();
 	dcache_enable();
 }
-#endif	/* CONFIG_SYS_DCACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #ifdef CONFIG_TFABOOT
 enum boot_src __get_boot_src(u32 porsr1)

arch/arm/cpu/armv8/s32v234/cpu.c

@@ -16,7 +16,7 @@ u32 cpu_mask(void)
 	return readl(MC_ME_CS);
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 #define S32V234_IRAM_BASE        0x3e800000UL
 #define S32V234_IRAM_SIZE        0x800000UL

arch/arm/cpu/pxa/cache.c

@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
 	/* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 	return invalidate_dcache_range(start, stop);
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -43,7 +43,7 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * Stub implementations for l2 cache operations

arch/arm/cpu/pxa/pxa2xx.c

@@ -286,10 +286,10 @@ void reset_cpu(ulong ignored)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	dcache_enable();
 #endif
 }

arch/arm/dts/bcm63158.dtsi

@@ -66,6 +66,12 @@
 			clock-frequency = <0xbebc200>;
 			u-boot,dm-pre-reloc;
 		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
 	};
 
 	ubus {
@@ -92,13 +98,13 @@
 		wdt1: watchdog@ff800480 {
 			compatible = "brcm,bcm6345-wdt";
 			reg = <0x0 0xff800480 0x0 0x14>;
-			clocks = <&periph_osc>;
+			clocks = <&refclk50mhz>;
 		};
 
 		wdt2: watchdog@ff8004c0 {
 			compatible = "brcm,bcm6345-wdt";
 			reg = <0x0 0xff8004c0 0x0 0x14>;
-			clocks = <&periph_osc>;
+			clocks = <&refclk50mhz>;
 		};
 
 		wdt-reboot {

arch/arm/dts/bcm6858.dtsi

@@ -66,6 +66,12 @@
 			clock-frequency = <200000000>;
 			u-boot,dm-pre-reloc;
 		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
 	};
 
 	ubus {
@@ -92,13 +98,13 @@
 		wdt1: watchdog@ff802780 {
 			compatible = "brcm,bcm6345-wdt";
 			reg = <0x0 0xff802780 0x0 0x14>;
-			clocks = <&periph_osc>;
+			clocks = <&refclk50mhz>;
 		};
 
 		wdt2: watchdog@ff8027c0 {
 			compatible = "brcm,bcm6345-wdt";
 			reg = <0x0 0xff8027c0 0x0 0x14>;
-			clocks = <&periph_osc>;
+			clocks = <&refclk50mhz>;
 		};
 
 		wdt-reboot {

arch/arm/include/asm/global_data.h

@@ -35,7 +35,7 @@ struct arch_global_data {
 	unsigned int tbl;
 	unsigned long lastinc;
 	unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 	unsigned long tlb_addr;
 	unsigned long tlb_size;
 #if defined(CONFIG_ARM64)

arch/arm/lib/cache-cp15.c

@@ -10,7 +10,7 @@
 #include <linux/compiler.h>
 #include <asm/armv7_mpu.h>
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit)
 }
 #endif
 
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 void icache_enable (void)
 {
 	return;
@@ -278,7 +278,7 @@ int icache_status(void)
 }
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void dcache_enable (void)
 {
 	return;

arch/arm/lib/cache.c

@@ -87,7 +87,7 @@ void noncached_init(void)
 	noncached_end = end;
 	noncached_next = start;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
 #endif
 }

arch/arm/mach-exynos/soc.c

@@ -25,7 +25,7 @@ void reset_cpu(ulong addr)
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-imx/cache.c

@@ -37,7 +37,7 @@ static void enable_ca7_smp(void)
 	}
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

arch/arm/mach-imx/imx8/cpu.c

@@ -446,7 +446,7 @@ void enable_caches(void)
 	dcache_enable();
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 u64 get_page_table_size(void)
 {
 	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);

arch/arm/mach-imx/mx5/soc.c

@@ -62,7 +62,7 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-keystone/init.c

@@ -204,7 +204,7 @@ void reset_cpu(ulong addr)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 #endif

arch/arm/mach-kirkwood/include/mach/config.h

@@ -26,12 +26,6 @@
 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
 #define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
-/*
- * Disable the dcache. Currently the network driver (mvgbe.c) and USB
- * EHCI driver (ehci-marvell.c) and possibly others rely on the data
- * cache being disabled.
- */
-#define CONFIG_SYS_DCACHE_OFF
 
 /*
  * By default kwbimage.cfg from board specific folder is used

arch/arm/mach-mediatek/mt8516/init.c

@@ -14,14 +14,10 @@
 #include <asm/armv8/mmu.h>
 #include <asm/sections.h>
 #include <dm/uclass.h>
-#include <linux/io.h>
 #include <dt-bindings/clock/mt8516-clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define WDOG_SWRST		0x10007014
-#define WDOG_SWRST_KEY		0x1209
-
 int dram_init(void)
 {
 	int ret;
@@ -87,10 +83,7 @@ int mtk_soc_early_init(void)
 
 void reset_cpu(ulong addr)
 {
-	while (1) {
-		writel(WDOG_SWRST_KEY, WDOG_SWRST);
-		mdelay(5);
-	}
+	psci_system_reset();
 }
 
 int print_cpuinfo(void)

arch/arm/mach-omap2/Makefile

@@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 endif
 
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
 obj-y	+= omap-cache.o
 endif
 

arch/arm/mach-omap2/omap5/sec_entry_cpu1.S

@@ -16,7 +16,7 @@
 
 .arch_extension sec
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 .global flush_dcache_range
 #endif
 
@@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1)
 	push	{r4, r5, lr}
 	ldr	r4, =omap_smc_sec_cpu1_args
 	stm	r4, {r0,r1,r2,r3}	@ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	mov	r0, r4
 	mov	r1, #CONFIG_SYS_CACHELINE_SIZE
 	add	r1, r0, r1		@ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1)
  */
 .section .data
 omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	.balign CONFIG_SYS_CACHELINE_SIZE
 	.rept  CONFIG_SYS_CACHELINE_SIZE/4
 	.word 0

arch/arm/mach-omap2/sec-common.c

@@ -333,7 +333,7 @@ int secure_tee_install(u32 addr)
 	debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
 	debug("tee_file_size = %d\n", tee_file_size);
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	flush_dcache_range(
 		rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
 		roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@ int secure_tee_install(u32 addr)
 		/* Reuse the tee_info buffer for SMC params */
 		smc_cpu1_params = (u32 *)&tee_info;
 		smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 		flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
 				roundup(sizeof(u32), ARCH_DMA_MINALIGN));
 #endif

arch/arm/mach-rmobile/cpu_info.c

@@ -17,7 +17,7 @@ int arch_cpu_init(void)
 
 /* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
 #ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	dcache_enable();

arch/arm/mach-rockchip/rk3036-board.c

@@ -48,7 +48,7 @@ int dram_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-rockchip/rk3128-board.c

@@ -57,7 +57,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-rockchip/rk3188-board.c

@@ -75,7 +75,7 @@ err:
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-rockchip/rk322x-board.c

@@ -58,7 +58,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-rockchip/rk3288-board.c

@@ -186,7 +186,7 @@ err:
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-rockchip/rv1108/rv1108.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-s5pc1xx/cache.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	dcache_enable();

arch/arm/mach-socfpga/misc.c

@@ -48,10 +48,10 @@ int dram_init(void)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	dcache_enable();
 #endif
 }

arch/arm/mach-sunxi/board.c

@@ -300,7 +300,7 @@ void reset_cpu(ulong addr)
 #endif
 }
 
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-tegra/board.c

@@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = {
 };
 #endif
 
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/arm/mach-zynq/cpu.c

@@ -83,7 +83,7 @@ void reset_cpu(ulong addr)
 		;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

arch/nds32/Kconfig

@@ -16,6 +16,32 @@ config TARGET_ADP_AE3XX
 
 endchoice
 
+config SYS_ICACHE_OFF
+	bool "Do not enable icache"
+	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+	bool "Do not enable dcache"
+	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
 source "board/AndesTech/adp-ag101p/Kconfig"
 source "board/AndesTech/adp-ae3xx/Kconfig"
 

arch/nds32/cpu/n1213/start.S

@@ -129,7 +129,7 @@ set_ivb:
 	mfsr	$r1, $mr8
 	and	$r1, $r1, $r0
 	mtsr	$r1, $mr8
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 /*
  * MMU_CTL NTC0 Cacheable/Write-Back
  */
@@ -139,7 +139,7 @@ set_ivb:
 	mtsr	$r1, $mr0
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_ARCH_MAP_SYSMEM
 /*
  * MMU_CTL NTC1 Non-cacheable
@@ -158,14 +158,14 @@ set_ivb:
 #endif
 #endif
 
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	li	$r0, 0x1
 	mfsr	$r1, $mr8
 	or	$r1, $r1, $r0
 	mtsr	$r1, $mr8
 #endif
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	li	$r0, 0x2
 	mfsr	$r1, $mr8
 	or	$r1, $r1, $r0

arch/nds32/lib/cache.c

@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 static inline unsigned long CACHE_SET(unsigned char cache)
 {
 	if (cache == ICACHE)
@@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
 }
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 void invalidate_icache_all(void)
 {
 	unsigned long end, line_size;
@@ -133,7 +133,7 @@ int icache_status(void)
 
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void dcache_wbinval_all(void)
 {
 	unsigned long end, line_size;

arch/riscv/Kconfig

@@ -19,6 +19,32 @@ config TARGET_SIFIVE_FU540
 
 endchoice
 
+config SYS_ICACHE_OFF
+	bool "Do not enable icache"
+	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+	bool "Do not enable dcache"
+	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
 # board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"

arch/riscv/cpu/ax25/cache.c

@@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
@@ -43,7 +43,7 @@ void icache_enable(void)
 
 void icache_disable(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"fence.i\n\t"
@@ -57,7 +57,7 @@ void icache_disable(void)
 
 void dcache_enable(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
@@ -70,7 +70,7 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"fence\n\t"

arch/xtensa/Kconfig

@@ -16,6 +16,32 @@ config TARGET_XTFPGA
 
 endchoice
 
+config SYS_ICACHE_OFF
+	bool "Do not enable icache"
+	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+	bool "Do not enable dcache"
+	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
 source "board/cadence/xtfpga/Kconfig"
 
 endmenu

arch/xtensa/cpu/start.S

@@ -164,19 +164,19 @@ _start:
 	 * enable data/instruction cache for relocated image.
 	 */
 #if XCHAL_HAVE_SPANNING_WAY && \
-	(!defined(CONFIG_SYS_DCACHE_OFF) || \
-	 !defined(CONFIG_SYS_ICACHE_OFF))
+	!(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+	  CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
 	srli	a7, a4, 29
 	slli	a7, a7, 29
 	addi	a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	rdtlb1	a8, a7
 	srli	a8, a8, 4
 	slli	a8, a8, 4
 	addi	a8, a8, CA_WRITEBACK
 	wdtlb	a8, a7
 #endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	ritlb1	a8, a7
 	srli	a8, a8, 4
 	slli	a8, a8, 4

board/st/stih410-b2260/board.c

@@ -26,7 +26,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */

cmd/bdinfo.c

@@ -321,7 +321,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 	print_eths();
 #endif
 	print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 	print_num("TLB addr", gd->arch.tlb_addr);
 #endif
 	print_num("relocaddr", gd->relocaddr);

common/board_f.c

@@ -381,7 +381,7 @@ static int reserve_round_4k(void)
 #ifdef CONFIG_ARM
 __weak int reserve_mmu(void)
 {
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 	/* reserve TLB table */
 	gd->arch.tlb_size = PGTABLE_SIZE;
 	gd->relocaddr -= gd->arch.tlb_size;

common/lcd.c

@@ -61,7 +61,7 @@ void lcd_sync(void)
 	 * architectures do not actually implement it. Is there a way to find
 	 * out whether it exists? For now, ARM is safe.
 	 */
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	int line_length;
 
 	if (lcd_flush_dcache)

common/spl/spl.c

@@ -195,10 +195,12 @@ static int spl_load_fit_image(struct spl_image_info *spl_image,
 #ifdef CONFIG_SPL_FIT_SIGNATURE
 	images.verify = 1;
 #endif
-	fit_image_load(&images, (ulong)header,
+	ret = fit_image_load(&images, (ulong)header,
 		       &fit_uname_fdt, &fit_uname_config,
 		       IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
 		       FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
+	if (ret >= 0)
+		spl_image->fdt_addr = (void *)dt_data;
 
 	conf_noffset = fit_conf_get_node((const void *)header,
 					 fit_uname_config);

configs/SBx81LIFKW_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFKW=y

configs/SBx81LIFXCAT_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFXCAT=y

configs/armadillo-800eva_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 # CONFIG_SYS_THUMB_BUILD is not set
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_TEXT_BASE=0xE80C0000

configs/axm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set

configs/bcm23550_w1d_defconfig

@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM23550_W1D=y
 CONFIG_SYS_TEXT_BASE=0x9f000000

configs/bcm963158_ram_defconfig

@@ -16,7 +16,6 @@ CONFIG_IMAGE_FORMAT_LEGACY=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
 # CONFIG_CMD_LZMADEC is not set
 # CONFIG_CMD_UNZIP is not set
 # CONFIG_CMD_FLASH is not set

configs/bcm968580xref_ram_defconfig

@@ -14,7 +14,6 @@ CONFIG_IMAGE_FORMAT_LEGACY=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y

configs/bitmain_antminer_s9_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="bitmain"
 CONFIG_SYS_BOARD="antminer_s9"
 CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_SPL_STACK_R_ADDR=0x200000

configs/colibri_pxa270_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_TARGET_COLIBRI_PXA270=y
 CONFIG_SYS_TEXT_BASE=0x0
 CONFIG_NR_DRAM_BANKS=1

configs/d2net_v2_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NET2BIG_V2=y

configs/da850evm_defconfig

@@ -47,6 +47,7 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPL_BLOCK_CACHE=y
 CONFIG_DM_GPIO=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_I2C=y

configs/db-88f6281-bp-nand_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000

configs/db-88f6281-bp-spi_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000

configs/devkit3250_defconfig

@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_LPC32XX=y
 CONFIG_SYS_TEXT_BASE=0x83F00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/dns325_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DNS325=y

configs/dockstar_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DOCKSTAR=y

configs/dreamplug_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DREAMPLUG=y

configs/ds109_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_DS109=y

configs/evb-ast2500_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ASPEED=y
 CONFIG_SYS_TEXT_BASE=0x0
 CONFIG_ASPEED_AST2500=y

configs/flea3_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_SYS_TEXT_BASE=0xA0000000
 CONFIG_NR_DRAM_BANKS=1

configs/goflexhome_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_GOFLEXHOME=y

configs/gplugd_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_TARGET_GPLUGD=y
 CONFIG_SYS_TEXT_BASE=0x00f00000
 CONFIG_NR_DRAM_BANKS=2

configs/guruplug_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_GURUPLUG=y

configs/highbank_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_SYS_TEXT_BASE=0x00008000

configs/ib62x0_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_IB62X0=y

configs/iconnect_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_ICONNECT=y

configs/imx8mq_evk_defconfig

@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_IMX8MQ_EVK=y

configs/imx8qm_mek_defconfig

@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx8qxp_mek_defconfig

@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/inetspace_v2_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_TARGET_NETSPACE_V2=y

configs/k2e_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ISW_ENTRY_ADDR=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000000

configs/k2e_hs_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_ISW_ENTRY_ADDR=0xC100000

configs/k2g_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ISW_ENTRY_ADDR=0xC0A0000
 CONFIG_SYS_TEXT_BASE=0xC000000

configs/k2g_hs_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_ISW_ENTRY_ADDR=0xC0A0000

configs/k2hk_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ISW_ENTRY_ADDR=0xC200000
 CONFIG_SYS_TEXT_BASE=0xC000000

configs/k2hk_hs_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_ISW_ENTRY_ADDR=0xC200000

configs/k2l_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ISW_ENTRY_ADDR=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000000

configs/k2l_hs_evm_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_ISW_ENTRY_ADDR=0xC100000

configs/km_kirkwood_128m16_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x07d00000
 CONFIG_TARGET_KM_KIRKWOOD=y