fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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@ -79,7 +79,7 @@ config TARGET_SOCFPGA_STRATIX10
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select ARMV8_MULTIENTRY
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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select ARMV8_SET_SMPEN
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select ARMV8_SPIN_TABLE
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select ARMV8_SPIN_TABLE
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select FPGA_STRATIX10
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select FPGA_INTEL_SDM_MAILBOX
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choice
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choice
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prompt "Altera SOCFPGA board select"
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prompt "Altera SOCFPGA board select"
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@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
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static Altera_desc altera_fpga[] = {
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static Altera_desc altera_fpga[] = {
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{
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{
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/* Family */
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/* Family */
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Intel_FPGA_Stratix10,
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Intel_FPGA_SDM_Mailbox,
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/* Interface type */
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/* Interface type */
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secure_device_manager_mailbox,
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secure_device_manager_mailbox,
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/* No limitation as additional data will be ignored */
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/* No limitation as additional data will be ignored */
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@ -31,16 +31,16 @@ config FPGA_CYCLON2
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Enable FPGA driver for loading bitstream in BIT and BIN format
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Enable FPGA driver for loading bitstream in BIT and BIN format
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on Altera Cyclone II device.
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on Altera Cyclone II device.
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config FPGA_STRATIX10
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config FPGA_INTEL_SDM_MAILBOX
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bool "Enable Altera FPGA driver for Stratix 10"
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bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
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depends on TARGET_SOCFPGA_STRATIX10
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depends on TARGET_SOCFPGA_STRATIX10
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select FPGA_ALTERA
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select FPGA_ALTERA
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help
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help
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Say Y here to enable the Altera Stratix 10 FPGA specific driver
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Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
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This provides common functionality for Altera Stratix 10 devices.
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This provides common functionality for Intel FPGA devices.
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Enable FPGA driver for writing bitstream into Altera Stratix10
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Enable FPGA driver for writing full bitstream into Intel FPGA
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device.
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devices through SDM (Secure Device Manager) Mailbox.
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config FPGA_XILINX
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config FPGA_XILINX
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bool "Enable Xilinx FPGA drivers"
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bool "Enable Xilinx FPGA drivers"
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@ -16,9 +16,9 @@ ifdef CONFIG_FPGA_ALTERA
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obj-y += altera.o
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obj-y += altera.o
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obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
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obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
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obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
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obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
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obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
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obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
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obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
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obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
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obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
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obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
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obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
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obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
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@ -40,12 +40,13 @@ static const struct altera_fpga {
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#if defined(CONFIG_FPGA_STRATIX_V)
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#if defined(CONFIG_FPGA_STRATIX_V)
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{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
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{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
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#endif
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#endif
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#if defined(CONFIG_FPGA_STRATIX10)
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{ Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
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#endif
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#if defined(CONFIG_FPGA_SOCFPGA)
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#if defined(CONFIG_FPGA_SOCFPGA)
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{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
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{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
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#endif
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#endif
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#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
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{ Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
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NULL },
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#endif
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};
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};
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static int altera_validate(Altera_desc *desc, const char *fn)
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static int altera_validate(Altera_desc *desc, const char *fn)
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@ -247,7 +247,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
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* This is the interface used by FPGA driver.
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* This is the interface used by FPGA driver.
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* Return 0 for success, non-zero for error.
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* Return 0 for success, non-zero for error.
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*/
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*/
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int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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{
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int ret;
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int ret;
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u32 resp_len = 2;
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u32 resp_len = 2;
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@ -56,10 +56,10 @@ enum altera_family {
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Altera_StratixII,
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Altera_StratixII,
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/* StratixV Family */
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/* StratixV Family */
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Altera_StratixV,
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Altera_StratixV,
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/* Stratix10 Family */
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Intel_FPGA_Stratix10,
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/* SoCFPGA Family */
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/* SoCFPGA Family */
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Altera_SoCFPGA,
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Altera_SoCFPGA,
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/* Intel FPGA Family with SDM (Secure Device Manager) Mailbox */
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Intel_FPGA_SDM_Mailbox,
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/* Add new models here */
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/* Add new models here */
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@ -120,8 +120,9 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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#endif
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#endif
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#ifdef CONFIG_FPGA_STRATIX10
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#ifdef CONFIG_FPGA_INTEL_SDM_MAILBOX
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int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
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int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data,
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size_t rbf_size);
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#endif
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#endif
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#endif /* _ALTERA_H_ */
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#endif /* _ALTERA_H_ */
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