x86: qemu: Turn on legacy segments decode
By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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@ -7,6 +7,8 @@
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#include <common.h>
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#include <pci.h>
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#include <pci_rom.h>
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#include <asm/pci.h>
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#include <asm/arch/qemu.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -50,6 +52,8 @@ int board_pci_post_scan(struct pci_controller *hose)
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ulong start;
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pci_dev_t bdf;
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struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } };
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u16 device;
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int pam, i;
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/*
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* QEMU emulated graphic card shows in the PCI configuration space with
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@ -67,5 +71,21 @@ int board_pci_post_scan(struct pci_controller *hose)
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debug("BIOS ran in %lums\n", get_timer(start));
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}
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
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pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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return ret;
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}
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@ -7,6 +7,12 @@
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#ifndef _ARCH_QEMU_H_
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#define _ARCH_QEMU_H_
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/* Programmable Attribute Map (PAM) Registers */
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#define I440FX_PAM 0x59
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#define Q35_PAM 0x90
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#define PAM_NUM 7
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#define PAM_RW 0x33
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/* I/O Ports */
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#define CMOS_ADDR_PORT 0x70
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#define CMOS_DATA_PORT 0x71
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