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Merge https://source.denx.de/u-boot/custodians/u-boot-spi

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This commit is contained in:
Tom Rini 2021-12-26 14:07:41 -05:00
commit c9964879ab
3 changed files with 22 additions and 6 deletions
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6
drivers/mtd/spi/Kconfig
View File

@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL
For legacy reasons, this option default to y. But if you intend to
actually use the software protection bits you should say n here.
config SF_DUAL_FLASH
bool "SPI DUAL flash memory support"
help
Enable this option to support two flash memories connected to a single
controller. Currently Xilinx Zynq qspi supports this.
config SPI_FLASH_ATMEL
bool "Atmel SPI flash support"
help

5
drivers/mtd/spi/spi-nor-ids.c
View File

@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

17
drivers/spi/cadence_qspi_apb.c
View File

@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
/* Check indirect done status */
ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
if (ret) {
printf("Indirect read clear completion error (%i)\n", ret);
goto failrd;
}
return 0;
failrd:
@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
/* Check indirect done status */
ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
if (ret) {
printf("Indirect write clear completion error (%i)\n", ret);
goto failwr;
}
if (bounce_buf)
free(bounce_buf);
return 0;