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For 2022.01

Browse Source 
-----------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083
 
 - Fix UART
 - moved to binman (MX8 boards)
 - Toradex: sync DTS with Linux
 - Gateworks: fixes
 - New boards : MSC SM2S iMX8MP
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Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2022.01
-----------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083

- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP
This commit is contained in:
Tom Rini 2022-11-14 07:29:51 -05:00
commit c4ee4fe92e
126 changed files with 5780 additions and 1560 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
MAINTAINERS
View File

@ -413,6 +413,15 @@ F: drivers/timer/atmel_tcb_timer.c
F: include/dt-bindings/mfd/atmel-flexcom.h
F: drivers/timer/mchp-pit64b-timer.c
ARM MSC SM2S IMX8MP SOM
M: Martyn Welch <martyn.welch@collabora.com>
M: Ian Ray <ian.ray@ge.com>
S: Maintained
F: arch/arm/dts/imx8mp-msc-sm2s*
F: board/msc/sm2s_imx8mp/
F: configs/msc_sm2s_imx8mp_defconfig
F: include/configs/msc_sm2s_imx8mp.h
ARM NEXELL S5P4418
M: Stefan Bosch <stefan_b@posteo.net>
S: Maintained

1
arch/arm/dts/Makefile
View File

@ -979,6 +979,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \

2
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2019 Toradex AG
*/
#include "imx8qm-u-boot.dtsi"
&mu {
u-boot,dm-pre-proper;
};

2
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2018, 2021 NXP
*/
#include "imx8qm-u-boot.dtsi"
&{/imx8qm-pm} {
u-boot,dm-spl;

2
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2019 Toradex AG
*/
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
u-boot,dm-pre-proper;

2
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2018, 2021 NXP
*/
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
u-boot,dm-spl;

1
arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi Normal file
View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

1
arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi Normal file
View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

16
arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
View File

@ -15,6 +15,22 @@
};
};
&soc {
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-pre-reloc;
};
&pinctrl_microsom_uart1 {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};

9
arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
};
};

1
arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi Normal file
View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

4
arch/arm/dts/imx8mm-beacon-baseboard.dtsi
View File

@ -285,14 +285,14 @@
&usbotg1 {
vbus-supply = <&reg_usbotg1>;
disable-over-current;
dr_mode="otg";
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
dr_mode="host";
dr_mode = "host";
status = "okay";
};

18
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
View File

@ -13,6 +13,10 @@
};
};
&aips4 {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@ -77,12 +81,24 @@
u-boot,dm-spl;
};
&reg_usbotg1 {
};
&uart2 {
u-boot,dm-spl;
};
&usbmisc1 {
u-boot,dm-spl;
};
&usbotg1 {
dr_mode="host";
u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
};
&usdhc2 {

43
arch/arm/dts/imx8mm-evk.dtsi
View File

@ -75,6 +75,11 @@
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@ -83,6 +88,25 @@
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@ -346,6 +370,16 @@
status = "okay";
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -494,6 +528,15 @@
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6

14
arch/arm/dts/imx8mm-icore-mx8mm.dtsi
View File

@ -2,7 +2,7 @@
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
* Copyright (c) 2020 Amarula Solutions(India)
*/
/ {
@ -84,42 +84,42 @@
};
reg_buck1: buck1 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck2: buck2 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck3: buck3 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck4: buck4 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck5: buck5 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck6: buck6 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;

14
arch/arm/dts/imx8mm-mx8menlo.dts
View File

@ -20,13 +20,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user1 {
led-1 {
label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
user2 {
led-2 {
label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@ -152,11 +152,11 @@
* CPLD_reset is RESET_SOFT in schematic
*/
gpio-line-names =
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[0]", "", "",
"", "", "", "CPLD_D[2]",
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
"CPLD_D[7]", "", "", "",
"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[7]", "", "",
"", "", "", "CPLD_D[5]",
"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
"CPLD_D[0]", "", "", "",
"", "", "", "",
"", "", "", "KBD_intK",
"", "", "", "";

2
arch/arm/dts/imx8mm-u-boot.dtsi
View File

@ -9,7 +9,7 @@
};
};
&{/soc@0} {
&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};

24
arch/arm/dts/imx8mm-venice-gw700x.dtsi
View File

@ -16,13 +16,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -36,14 +36,14 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@ -286,8 +286,8 @@
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-boot-on;
regulator-always-on;
};
@ -297,8 +297,8 @@
regulator-name = "buck2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
@ -308,8 +308,8 @@
regulator-name = "buck3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-always-on;
};
@ -318,8 +318,8 @@
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};

12
arch/arm/dts/imx8mm-venice-gw7901.dts
View File

@ -38,13 +38,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -58,14 +58,14 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@ -626,24 +626,28 @@
lan1: port@0 {
reg = <0>;
label = "lan1";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan2: port@1 {
reg = <1>;
label = "lan2";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan3: port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan4: port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};

14
arch/arm/dts/imx8mm-venice-gw7902.dts
View File

@ -42,13 +42,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -62,14 +62,14 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@ -222,7 +222,6 @@
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&can20m>;
oscillator-frequency = <20000000>;
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;
@ -651,7 +650,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -742,9 +741,6 @@
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */

6
arch/arm/dts/imx8mm-venice-gw7903.dts
View File

@ -33,13 +33,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -53,7 +53,7 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;

4
arch/arm/dts/imx8mm-venice-gw7904.dts
View File

@ -617,6 +617,10 @@
status = "okay";
};
&pgc_mipi {
status = "disabled";
};
/* off-board RS232 */
&uart1 {
pinctrl-names = "default";

50
arch/arm/dts/imx8mm-verdin.dtsi
View File

@ -32,10 +32,10 @@
};
/* Fixed clock dedicated to SPI CAN controller */
clk20m: oscillator {
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
clock-frequency = <40000000>;
};
gpio-keys {
@ -43,7 +43,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
wakeup {
key-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
@ -53,6 +53,21 @@
};
};
hdmi_connector: hdmi-connector {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c2>;
label = "hdmi";
type = "a";
status = "disabled";
};
panel_lvds: panel-lvds {
compatible = "panel-lvds";
backlight = <&backlight>;
data-mapping = "vesa-24";
status = "disabled";
};
/* Carrier Board Supplies */
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
@ -154,6 +169,14 @@
cpu-supply = <&reg_vdd_arm>;
};
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <105000>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
@ -194,8 +217,8 @@
can1: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&clk20m>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk40m>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_int>;
reg = <0>;
@ -359,8 +382,8 @@
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <805000>;
regulator-name = "On-module +VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
};
@ -368,8 +391,8 @@
reg_vdd_dram: BUCK3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <805000>;
regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
};
@ -408,7 +431,7 @@
reg_vdd_snvs: LDO2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-max-microvolt = <800000>;
regulator-min-microvolt = <800000>;
regulator-name = "On-module +V0.8_SNVS (LDO2)";
};
@ -553,8 +576,8 @@
status = "disabled";
};
lvds_ti_sn65dsi83: bridge@2c {
compatible = "ti,sn65dsi83";
lvds_ti_sn65dsi84: bridge@2c {
compatible = "ti,sn65dsi84";
/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
@ -595,7 +618,7 @@
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
reg = <0x4a>;
/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@ -737,6 +760,7 @@
};
&usbphynop2 {
power-domains = <&pgc_otg2>;
vcc-supply = <&reg_vdd_3v3>;
};

4
arch/arm/dts/imx8mn-beacon-baseboard.dtsi
View File

@ -146,7 +146,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
@ -182,7 +182,7 @@
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode="otg";
dr_mode = "otg";
status = "okay";
};

45
arch/arm/dts/imx8mn-evk.dtsi
View File

@ -47,6 +47,11 @@
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@ -57,6 +62,25 @@
clock-names = "mclk";
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
@ -78,7 +102,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
@ -183,6 +207,16 @@
};
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -354,6 +388,15 @@
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6

6
arch/arm/dts/imx8mn-var-som-symphony.dts
View File

@ -26,19 +26,19 @@
gpio-keys {
compatible = "gpio-keys";
back {
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
home {
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
menu {
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;

9
arch/arm/dts/imx8mn-venice-gw7902.dts
View File

@ -39,13 +39,13 @@
gpio-keys {
compatible = "gpio-keys";
user-pb {
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@ -59,14 +59,14 @@
interrupts = <1>;
};
eeprom-wp {
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@ -213,7 +213,6 @@
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&can20m>;
oscillator-frequency = <20000000>;
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;

14
arch/arm/dts/imx8mn.dtsi
View File

@ -212,7 +212,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@ -269,7 +269,7 @@
arm,no-tick-in-suspend;
};
soc@0 {
soc: soc@0 {
compatible = "fsl,imx8mn-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -422,7 +422,7 @@
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
@ -672,7 +672,6 @@
<&clk IMX8MN_CLK_GPU_SHADER>,
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
<&clk IMX8MN_CLK_GPU_AHB>;
resets = <&src IMX8MQ_RESET_GPU_RESET>;
};
pgc_dispmix: power-domain@3 {
@ -857,6 +856,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sec_jr1: jr@2000 {
@ -941,7 +941,7 @@
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -955,7 +955,7 @@
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -969,7 +969,7 @@
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};

29
arch/arm/dts/imx8mp-dhcom-pdk2.dts
View File

@ -17,14 +17,13 @@
/ {
model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
"fsl,imx8mp";
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
gpio-keys {
#size-cells = <0>;
compatible = "gpio-keys";
button-0 {
@ -67,7 +66,7 @@
led {
compatible = "gpio-leds";
led-5 {
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@ -76,7 +75,7 @@
pinctrl-names = "default";
};
led-6 {
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@ -85,7 +84,7 @@
pinctrl-names = "default";
};
led-7 {
led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@ -94,7 +93,7 @@
pinctrl-names = "default";
};
led-8 {
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@ -123,10 +122,11 @@
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
compatible = "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
max-speed = <100>;
reg = <7>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
@ -143,7 +143,6 @@
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
max-speed = <100>;
};
};
};
@ -155,3 +154,15 @@
&usb3_1 {
fsl,over-current-active-low;
};
&iomuxc {
/*
* GPIO_A,B,C,D are connected to buttons.
* GPIO_E,F,H,I are connected to LEDs.
* GPIO_M is connected to CLKOUT2.
*/
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_g &pinctrl_dhcom_j
&pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_int>;
};

20
arch/arm/dts/imx8mp-dhcom-som.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
*/
@ -224,10 +224,6 @@
};
&i2c3 {
/*
* iMX8MP 1P33A Errata ERR007805
* I2C is limited to 384 kHz due to SoC bug.
*/
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
@ -393,10 +389,6 @@
};
&i2c4 {
/*
* iMX8MP 1P33A Errata ERR007805
* I2C is limited to 384 kHz due to SoC bug.
*/
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
@ -407,10 +399,6 @@
};
&i2c5 { /* HDMI EDID bus */
/*
* iMX8MP 1P33A Errata ERR007805
* I2C is limited to 384 kHz due to SoC bug.
*/
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
@ -802,8 +790,8 @@
pinctrl_i2c5: dhcom-i2c5-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084
MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
>;
};
@ -830,7 +818,7 @@
pinctrl_rtc: dhcom-rtc-grp {
fsl,pins = <
/* RTC_#INT Interrupt */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
>;
};

179
arch/arm/dts/imx8mp-evk.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
/ {
@ -33,6 +34,12 @@
<0x1 0x00000000 0 0xc0000000>;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
@ -55,6 +62,17 @@
enable-active-high;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -67,18 +85,20 @@
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
&A53_0 {
cpu-supply = <&reg_arm>;
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "disabled";/* can2 pin conflict with pdm */
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
&eqos {
@ -197,6 +217,20 @@
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "disabled";/* can2 pin conflict with pdm */
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -221,7 +255,7 @@
regulator-ramp-delay = <3125>;
};
BUCK2 {
reg_arm: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1025000>;
@ -334,6 +368,28 @@
*/
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -395,41 +451,41 @@
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
>;
};
@ -461,28 +517,41 @@
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
>;
};
@ -500,20 +569,20 @@
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
@ -525,7 +594,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@ -537,7 +606,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@ -549,7 +618,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};

2
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
View File

@ -2,7 +2,7 @@
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;

2
arch/arm/dts/imx8mp-icore-mx8mp.dtsi
View File

@ -2,7 +2,7 @@
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
* Copyright (c) 2020 Amarula Solutions(India)
*/
/ {

65
arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi Normal file
View File

@ -0,0 +1,65 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include "imx8mp-u-boot.dtsi"
/ {
model = "MSC SM2S-IMX8MPLUS";
compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&i2c4 {
u-boot,dm-spl;
};
&i2c5 {
u-boot,dm-spl;
};
&i2c6 {
u-boot,dm-spl;
};
&pinctrl_i2c6 {
u-boot,dm-spl;
};
&pmic {
u-boot,dm-spl;
};

820
arch/arm/dts/imx8mp-msc-sm2s.dts Normal file
View File

@ -0,0 +1,820 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 Avnet Embedded GmbH
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
rtc0 = &sys_rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart2;
};
reg_usb0_host_vbus: regulator-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0_host_vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_vbus>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_host_vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
reg_flexcan1_xceiver: regulator-flexcan1 {
compatible = "regulator-fixed";
regulator-name = "flexcan1-xceiver";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_flexcan2_xceiver: regulator-flexcan2 {
compatible = "regulator-fixed";
regulator-name = "flexcan2-xceiver";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
lcd0_backlight: backlight-0 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_backlight>;
pwms = <&pwm1 0 100000 0>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <255>;
enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
lcd1_backlight: backlight-1 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd1_backlight>;
pwms = <&pwm2 0 100000 0>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <255>;
enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
status = "okay";
led-sw {
label = "sw-led";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
extcon_usb0: extcon-usb0 {
compatible = "linux,extcon-usb-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_extcon>;
id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
&A53_0 {
cpu-supply = <&vcc_arm>;
};
&A53_1 {
cpu-supply = <&vcc_arm>;
};
&A53_2 {
cpu-supply = <&vcc_arm>;
};
&A53_3 {
cpu-supply = <&vcc_arm>;
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
id_eeprom: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <400000>;
status = "disabled";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <400000>;
status = "disabled";
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5>;
clock-frequency = <400000>;
status = "disabled";
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6>;
clock-frequency = <400000>;
status = "okay";
tca6424: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tca6424>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
"CHARGER_PRSNT#";
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
dsi_lvds_bridge: bridge@2d {
compatible = "ti,sn65dsi83";
reg = <0x2d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_bridge>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
pmic: pmic@30 {
compatible = "ricoh,rn5t567";
reg = <0x30>;
interrupt-parent = <&tca6424>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
regulators {
DCDC1 {
regulator-name = "VCC_SOC";
regulator-always-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
};
DCDC2 {
regulator-name = "VCC_DRAM";
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
vcc_arm: DCDC3 {
regulator-name = "VCC_ARM";
regulator-always-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
};
DCDC4 {
regulator-name = "VCC_1V8";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
LDO1 {
regulator-name = "VCC_LDO1_2V5";
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
LDO2 {
regulator-name = "VCC_LDO2_1V8";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
LDO3 {
regulator-name = "VCC_ETH_2V5";
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
LDO4 {
regulator-name = "VCC_DDR4_2V5";
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
LDO5 {
regulator-name = "VCC_LDO5_1V8";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
LDORTC1 {
regulator-name = "VCC_SNVS_1V8";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
LDORTC2 {
regulator-name = "VCC_SNVS_3V3";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
sys_rtc: rtc@32 {
compatible = "ricoh,r2221tl";
reg = <0x32>;
interrupt-parent = <&tca6424>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
};
tmp_sensor: temperature-sensor@71 {
compatible = "ti,tmp103";
reg = <0x71>;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_flexcan1_xceiver>;
status = "disabled";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_flexcan2_xceiver>;
status = "disabled";
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
qspi_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "disabled";
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usb3_phy0 {
vbus-supply = <&reg_usb0_host_vbus>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_usb1_host_vbus>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
extcon = <&extcon_usb0>;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins =
<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>,
<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>,
<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>,
<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>,
<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins =
<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>,
<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>,
<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>,
<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>,
<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>;
};
pinctrl_eqos: eqosgrp {
fsl,pins =
<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
};
pinctrl_fec: fecgrp {
fsl,pins =
<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>,
<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>,
<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>,
<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>,
<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>,
<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>,
<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>,
<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>,
<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>,
<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>,
<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>,
<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>,
<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>,
<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>,
<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>,
<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins =
<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>,
<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>,
<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins =
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins =
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins =
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins =
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>,
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>,
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>;
};
pinctrl_lcd0_backlight: lcd0-backlightgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>;
};
pinctrl_lcd1_backlight: lcd1-backlightgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>;
};
pinctrl_leds: ledsgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>;
};
pinctrl_lvds_bridge: lvds-bridgegrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins =
<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins =
<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>;
};
pinctrl_tca6424: tca6424grp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>;
};
pinctrl_uart1: uart1grp {
fsl,pins =
<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>,
<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>;
};
pinctrl_uart2: uart2grp {
fsl,pins =
<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>,
<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>,
<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>,
<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>;
};
pinctrl_uart3: uart3grp {
fsl,pins =
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>,
<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>,
<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>,
<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>;
};
pinctrl_uart4: uart4grp {
fsl,pins =
<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>,
<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>;
};
pinctrl_usb0_extcon: usb0-extcongrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>;
};
pinctrl_usb0_vbus: usb0-vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>;
};
pinctrl_usb1_vbus: usb1-vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>,
<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>,
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>,
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
};
pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
fsl,pins =
<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>,
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins =
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins =
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>,
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>,
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>,
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>,
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>,
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>,
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>,
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>,
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>,
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>;
};
pinctrl_wdog: wdoggrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>;
};
};

48
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
View File

@ -116,48 +116,48 @@
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
@ -175,7 +175,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@ -187,7 +187,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@ -199,7 +199,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
};

2
arch/arm/dts/imx8mp-u-boot.dtsi
View File

@ -10,7 +10,7 @@
};
};
&{/soc@0} {
&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};

290
arch/arm/dts/imx8mp-venice-gw74xx.dts
View File

@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
@ -100,6 +101,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
@ -123,8 +130,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_can>;
regulator-name = "can2_stby";
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
@ -135,13 +141,29 @@
compatible = "regulator-fixed";
regulator-name = "wl";
gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
startup-delay-us = <70000>;
enable-active-high;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
@ -200,8 +222,8 @@
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "",
"", "", "", "", "", "", "pcie3_wdis#", "",
"", "", "pcie2_wdis#", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@ -362,7 +384,7 @@
regulator-ramp-delay = <3125>;
};
BUCK2 {
reg_arm: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1025000>;
@ -484,35 +506,40 @@
lan1: port@0 {
reg = <0>;
label = "lan1";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan2: port@1 {
reg = <1>;
label = "lan2";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan3: port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan4: port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
lan5: port@4 {
reg = <4>;
label = "lan5";
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
port@6 {
reg = <6>;
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec>;
phy-mode = "rgmii-id";
@ -542,6 +569,28 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
status = "okay";
};
/* GPS / off-board header */
&uart1 {
pinctrl-names = "default";
@ -556,6 +605,21 @@
status = "okay";
};
/* bluetooth HCI */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
@ -563,22 +627,37 @@
};
/* USB1 - Type C front panel */
&usb3_phy0 {
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
/* dual role is implemented but not a full featured OTG */
adp-disable;
hnp-disable;
srp-disable;
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "peripheral";
status = "okay";
connector {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbcon1>;
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
label = "Type-C";
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
};
/* USB2 - USB3.0 Hub */
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
@ -596,6 +675,25 @@
status = "okay";
};
/* SDIO WiFi */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_wifi_en>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@0 {
compatible = "cypress,cyw4373-fmac";
reg = <0>;
};
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
@ -622,15 +720,14 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
@ -639,47 +736,47 @@
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
>;
};
@ -692,61 +789,67 @@
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
>;
};
@ -758,22 +861,22 @@
pinctrl_reg_usb2: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
>;
};
pinctrl_reg_wifi: regwifigrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
>;
};
@ -811,7 +914,7 @@
pinctrl_uart3_gpio: uart3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
>;
};
@ -825,7 +928,12 @@
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140
>;
};
pinctrl_usbcon1: usb1congrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};
@ -840,6 +948,28 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190

32
arch/arm/dts/imx8mp-verdin.dtsi
View File

@ -49,7 +49,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
wakeup {
button-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
@ -146,6 +146,30 @@
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <105000>;
};
/* Verdin SPI_1 */
&ecspi1 {
#address-cells = <1>;
@ -445,7 +469,7 @@
regulator-ramp-delay = <3125>;
};
BUCK2 {
reg_vdd_arm: BUCK2 {
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
@ -619,7 +643,7 @@
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reg = <0x4a>;
/* Verdin GPIO_2 (SODIMM 208) */
reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "disabled";
};
};
@ -696,7 +720,7 @@
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
reg = <0x4a>;
/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
status = "disabled";
};

147
arch/arm/dts/imx8mp.dtsi
View File

@ -5,8 +5,10 @@
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interconnect/fsl,imx8mp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
@ -195,7 +197,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@ -293,7 +295,7 @@
arm,no-tick-in-suspend;
};
soc@0 {
soc: soc@0 {
compatible = "fsl,imx8mp-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -469,6 +471,11 @@
wakeup-source;
status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
compatible = "fsl,imx8mp-snvs-lpgpr",
"fsl,imx7d-snvs-lpgpr";
};
};
clk: clock-controller@30380000 {
@ -595,7 +602,34 @@
pgc_ispdwp: power-domain@18 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
};
pgc_vpumix: power-domain@19 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_vpu_g1: power-domain@20 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
pgc_vpu_g2: power-domain@21 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
};
pgc_vpu_vc8000e: power-domain@22 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
};
};
@ -791,6 +825,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sec_jr1: jr@2000 {
@ -903,7 +938,7 @@
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -917,7 +952,7 @@
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -931,7 +966,7 @@
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -1018,6 +1053,26 @@
};
};
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
clocks = <&clk IMX8MP_CLK_NOC>;
#interconnect-cells = <1>;
operating-points-v2 = <&noc_opp_table>;
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200M {
opp-hz = /bits/ 64 <200000000>;
};
opp-1000M {
opp-hz = /bits/ 64 <1000000000>;
};
};
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
@ -1043,6 +1098,18 @@
"lcdif1", "isi", "mipi-csi2",
"lcdif2", "isp", "dwe",
"mipi-dsi2";
interconnects =
<&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
<&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
"isi1", "isi2", "isp0", "isp1",
"dwe";
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
@ -1063,6 +1130,17 @@
#power-domain-cells = <1>;
};
pcie_phy: pcie-phy@32f00000 {
compatible = "fsl,imx8mp-pcie-phy";
reg = <0x32f00000 0x10000>;
resets = <&src IMX8MP_RESET_PCIEPHY>,
<&src IMX8MP_RESET_PCIEPHY_PERST>;
reset-names = "pciephy", "perst";
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
#phy-cells = <0>;
status = "disabled";
};
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
@ -1074,10 +1152,46 @@
<&pgc_hsiomix>, <&pgc_pcie_phy>;
power-domain-names = "bus", "usb", "usb-phy1",
"usb-phy2", "pcie", "pcie-phy";
interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
<&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
<&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
#power-domain-cells = <1>;
};
};
pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <3>;
linux,pci-domain = <0>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
};
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
@ -1109,6 +1223,23 @@
power-domains = <&pgc_gpu2d>;
};
vpumix_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
#power-domain-cells = <1>;
power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
<&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
power-domain-names = "bus", "g1", "g2", "vc8000e";
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
<&clk IMX8MP_CLK_VPU_G2_ROOT>,
<&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
clock-names = "g1", "g2", "vc8000e";
interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
interconnect-names = "g1", "g2", "vc8000e";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
@ -1168,7 +1299,7 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u2-freeclk-exists-quirk;
snps,gfladj-refclk-lpm-sel-quirk;
};
};
@ -1210,7 +1341,7 @@
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis-u2-freeclk-exists-quirk;
snps,gfladj-refclk-lpm-sel-quirk;
};
};

43
arch/arm/dts/imx8mq-evk.dts
View File

@ -71,12 +71,36 @@
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai3>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@ -386,6 +410,16 @@
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -548,6 +582,15 @@
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6

45
arch/arm/dts/imx8mq-librem5-r3.dtsi Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
/*
* This file describes hardware that is shared among r3 ("Dogwood") and
* later revisions of the Librem 5 so it has to be included in dts there.
*/
#include "imx8mq-librem5.dtsi"
/ {
model = "Purism Librem 5r3";
compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
};
&accel_gyro {
mount-matrix = "1", "0", "0",
"0", "1", "0",
"0", "0", "-1";
};
&bq25895 {
ti,battery-regulation-voltage = <4200000>; /* uV */
ti,charge-current = <1500000>; /* uA */
ti,termination-current = <144000>; /* uA */
};
&camera_front {
pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>;
shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
};
&iomuxc {
pinctrl_r3_camera_pwr: r3camerapwrgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83
>;
};
};
&proximity {
proximity-near-level = <25>;
};

20
arch/arm/dts/imx8mq-librem5-r4.dts
View File

@ -1,35 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2020 Purism SPC <kernel@puri.sm>
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
#include "imx8mq-librem5.dtsi"
#include "imx8mq-librem5-r3.dtsi"
/ {
model = "Purism Librem 5r4";
compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
};
&accel_gyro {
mount-matrix = "1", "0", "0",
"0", "1", "0",
"0", "0", "-1";
};
&bat {
maxim,rsns-microohm = <1667>;
};
&bq25895 {
ti,battery-regulation-voltage = <4200000>; /* uV */
ti,charge-current = <1500000>; /* uA */
ti,termination-current = <144000>; /* uA */
};
&led_backlight {
led-max-microamp = <25000>;
};
&lcd_panel {
compatible = "ys,ys57pss36bh5gq";
};
&proximity {
proximity-near-level = <10>;
};

153
arch/arm/dts/imx8mq-librem5.dtsi
View File

@ -7,6 +7,7 @@
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "imx8mq.dtsi"
@ -14,6 +15,7 @@
/ {
model = "Purism Librem 5";
compatible = "purism,librem5", "fsl,imx8mq";
chassis-type = "handset";
backlight_dsi: backlight-dsi {
compatible = "led-backlight";
@ -36,18 +38,45 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keys>;
vol-down {
key-vol-down {
label = "VOL_DOWN";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <50>;
wakeup-source;
};
vol-up {
key-vol-up {
label = "VOL_UP";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <50>;
wakeup-source;
};
};
led-controller {
compatible = "pwm-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
max-brightness = <248>;
pwms = <&pwm2 0 50000 0>;
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
max-brightness = <248>;
pwms = <&pwm4 0 50000 0>;
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
max-brightness = <248>;
pwms = <&pwm3 0 50000 0>;
};
};
@ -62,6 +91,40 @@
enable-active-high;
};
/*
* the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC
* since we can't have it twice in the 2 different regulator nodes.
*/
reg_csi_1v8: regulator-csi-1v8 {
compatible = "regulator-fixed";
regulator-name = "CAMERA_VDDIO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_vdd_3v3>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* controlled by the CAMERA_POWER_KEY HKS */
reg_vcam_1v2: regulator-vcam-1v2 {
compatible = "regulator-fixed";
regulator-name = "CAMERA_VDDD_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&reg_vdd_1v8>;
enable-active-high;
};
reg_vcam_2v8: regulator-vcam-2v8 {
compatible = "regulator-fixed";
regulator-name = "CAMERA_VDDA_2V8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&reg_vdd_3v3>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_gnss: regulator-gnss {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -237,8 +300,13 @@
cpu-supply = <&buck2_reg>;
};
&csi1 {
status = "okay";
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
status = "okay";
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
@ -283,15 +351,10 @@
};
partition@30000 {
label = "protected1";
reg = <0x30000 0x10000>;
label = "firmware";
reg = <0x30000 0x1d0000>;
read-only;
};
partition@40000 {
label = "rw";
reg = <0x40000 0x1C0000>;
};
};
};
@ -329,12 +392,24 @@
>;
};
pinctrl_camera_pwr: camerapwrgrp {
fsl,pins = <
/* CAMERA_PWR_EN_3V3 */
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
/* CSI1_NRST */
MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83
>;
};
pinctrl_charger_in: chargeringrp {
fsl,pins = <
/* CHRG_INT */
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80
/* CHG_STATUS_B */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80
>;
};
@ -698,6 +773,10 @@
interrupt-names = "irq";
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -725,7 +804,7 @@
compatible = "rohm,bd71837";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
@ -958,6 +1037,31 @@
>;
};
camera_front: camera@20 {
compatible = "hynix,hi846";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-rates = <25000000>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
vdda-supply = <&reg_vcam_2v8>;
vddd-supply = <&reg_vcam_1v2>;
vddio-supply = <&reg_csi_1v8>;
rotation = <90>;
orientation = <0>;
port {
camera1_ep: endpoint {
data-lanes = <1 2>;
link-frequencies = /bits/ 64
<80000000 200000000 300000000>;
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
backlight@36 {
compatible = "ti,lm36922";
reg = <0x36>;
@ -996,6 +1100,12 @@
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
vcm@c {
compatible = "dongwoon,dw9714";
reg = <0x0c>;
vcc-supply = <&reg_csi_1v8>;
};
bat: fuel-gauge@36 {
compatible = "maxim,max17055";
reg = <0x36>;
@ -1003,6 +1113,7 @@
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gauge>;
power-supplies = <&bq25895>;
maxim,over-heat-temp = <700>;
maxim,over-volt = <4500>;
maxim,rsns-microohm = <5000>;
@ -1019,7 +1130,7 @@
ti,precharge-current = <130000>; /* uA */
ti,minimum-sys-voltage = <3700000>; /* uV */
ti,boost-voltage = <5000000>; /* uV */
ti,boost-max-current = <500000>; /* uA */
ti,boost-max-current = <1500000>; /* uA */
ti,use-vinmin-threshold = <1>; /* enable VINDPM */
ti,vinmin-threshold = <3900000>; /* uV */
monitored-battery = <&bat>;
@ -1031,6 +1142,21 @@
status = "okay";
};
&mipi_csi1 {
status = "okay";
ports {
port@0 {
reg = <0>;
mipi1_sensor_ep: endpoint {
remote-endpoint = <&camera1_ep>;
data-lanes = <1 2>;
};
};
};
};
&mipi_dsi {
#address-cells = <1>;
#size-cells = <0>;
@ -1174,6 +1300,7 @@
#size-cells = <0>;
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
usb-role-switch;
status = "okay";
port@0 {

10
arch/arm/dts/imx8mq-u-boot.dtsi
View File

@ -10,23 +10,23 @@
};
&{/soc@0} {
&soc {
u-boot,dm-spl;
};
&{/soc@0/bus@30000000} {
&aips1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30400000} {
&aips2 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000} {
&aips3 {
u-boot,dm-spl;
};
&{/soc@0/bus@32c00000} {
&aips4 {
u-boot,dm-spl;
};

19
arch/arm/dts/imx8mq.dtsi
View File

@ -94,7 +94,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@ -320,7 +320,7 @@
arm,no-tick-in-suspend;
};
soc@0 {
soc: soc@0 {
compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -329,7 +329,7 @@
nvmem-cells = <&imx8mq_uid>;
nvmem-cell-names = "soc_unique_id";
bus@30000000 { /* AIPS1 */
aips1: bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
@ -507,7 +507,7 @@
<0x00030005 0x00000053>,
<0x00030006 0x0000005f>,
<0x00030007 0x00000071>;
#thermal-sensor-cells = <1>;
#thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
@ -534,7 +534,7 @@
status = "disabled";
};
sdma2: sdma@302c0000 {
sdma2: dma-controller@302c0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@ -784,7 +784,7 @@
};
};
bus@30400000 { /* AIPS2 */
aips2: bus@30400000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
@ -844,7 +844,7 @@
};
};
bus@30800000 { /* AIPS3 */
aips3: bus@30800000 { /* AIPS3 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
@ -1018,6 +1018,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sec_jr1: jr@2000 {
@ -1301,7 +1302,7 @@
status = "disabled";
};
sdma1: sdma@30bd0000 {
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@ -1369,7 +1370,7 @@
};
};
bus@32c00000 { /* AIPS4 */
aips4: bus@32c00000 { /* AIPS4 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;

1
arch/arm/dts/imx8qm-cgtqmx8.dts
View File

@ -12,6 +12,7 @@
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
#include "imx8qm-u-boot.dtsi"
/ {
model = "Congatec QMX8 Qseven series";

1
arch/arm/dts/imx8qm-rom7720-a1.dts
View File

@ -10,6 +10,7 @@
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
#include "imx8qm-u-boot.dtsi"
/ {
model = "Advantech iMX8QM Qseven series";

135
arch/arm/dts/imx8qm-u-boot.dtsi Normal file
View File

@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 NXP
*/
/ {
binman: binman {
multiple-images;
};
};
&binman {
#ifdef CONFIG_SPL_BUILD
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
#endif
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x00910000>;
load = <0x00091000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
scfw {
arch = "arm64";
compression = "none";
description = "System Controler Firmware";
type = "firmware";
scfw_blob {
filename = "mx8qm-val-scfw-tcm.bin";
type = "blob-ext";
};
};
seco {
arch = "arm64";
compression = "none";
description = "Seco Firmware";
type = "firmware";
seco_blob {
filename = "mx8qm-ahab-container.img";
type = "blob-ext";
};
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
};
};

2
arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2019 Siemens AG
*/
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
u-boot,dm-spl;

133
arch/arm/dts/imx8qxp-u-boot.dtsi Normal file
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@ -0,0 +1,133 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018, 2021 NXP
*/
/ {
binman: binman {
multiple-images;
};
};
&binman {
#ifdef CONFIG_SPL_BUILD
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
#endif
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x00910000>;
load = <0x00091000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
scfw {
arch = "arm64";
compression = "none";
description = "System Controler Firmware";
type = "firmware";
scfw_blob {
filename = "mx8qx-mek-scfw-tcm.bin";
type = "blob-ext";
};
};
seco {
arch = "arm64";
compression = "none";
description = "Seco Firmware";
type = "firmware";
seco_blob {
filename = "mx8qxc0-ahab-container.img";
type = "blob-ext";
};
};
fdt {
type = "flat_dt";
compression = "none";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "conf";
conf {
fdt = "fdt";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
};
};

15
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
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@ -3,7 +3,16 @@
* Copyright 2021 NXP
*/
&{/soc@0} {
/ {
mu@27020000 {
compatible = "fsl,imx8ulp-mu";
reg = <0 0x27020000 0 0x10000>;
status = "okay";
u-boot,dm-spl;
};
};
&soc {
u-boot,dm-spl;
};
@ -23,10 +32,6 @@
u-boot,dm-spl;
};
&s400_mu {
u-boot,dm-spl;
};
&lpuart5 {
u-boot,dm-spl;
};

242
arch/arm/dts/imx8ulp-evk.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
@ -8,17 +8,31 @@
#include "imx8ulp.dtsi"
/ {
model = "FSL i.MX8ULP EVK";
model = "NXP i.MX8ULP EVK";
compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
chosen {
stdout-path = &lpuart5;
bootargs = "console=ttyLP1,115200 earlycon";
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
clock_ext_rmii: clock-ext-rmii {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "ext_rmii_clk";
#clock-cells = <0>;
};
clock_ext_ts: clock-ext-ts {
compatible = "fixed-clock";
/* External ts clock is 50MHZ from PHY on EVK board. */
clock-frequency = <50000000>;
clock-output-names = "ext_ts_clk";
#clock-cells = <0>;
};
};
@ -30,24 +44,67 @@
status = "okay";
};
&usdhc0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
non-removable;
bus-width = <8>;
status = "okay";
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet>;
pinctrl-1 = <&pinctrl_enet>;
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&pcc4 IMX8ULP_CLK_ENET>,
<&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
<&clock_ext_rmii>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
assigned-clock-parents = <&clock_ext_ts>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <1>;
};
};
};
&iomuxc1 {
pinctrl_lpuart5: lpuart5grp {
pinctrl_enet: enetgrp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x03
MX8ULP_PAD_PTF15__LPUART5_RX 0x03
MX8ULP_PAD_PTE15__ENET0_MDC 0x43
MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
MX8ULP_PAD_PTE17__ENET0_RXER 0x43
MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
pinctrl_lpi2c7: lpi2c7grp {
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27
MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
MX8ULP_PAD_PTD10__SDHC0_D0 0x43
@ -61,163 +118,4 @@
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
>;
};
pinctrl_usdhc2_pte: usdhc2ptegrp {
fsl,pins = <
MX8ULP_PAD_PTE1__SDHC2_D0 0x43
MX8ULP_PAD_PTE0__SDHC2_D1 0x43
MX8ULP_PAD_PTE5__SDHC2_D2 0x43
MX8ULP_PAD_PTE4__SDHC2_D3 0x43
MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
MX8ULP_PAD_PTE7__PTE7 0x10003
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
MX8ULP_PAD_PTE15__ENET0_MDC 0x43
MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTE17__ENET0_RXER 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
>;
};
pinctrl_usbotg0_id: otg0idgrp {
fsl,pins = <
MX8ULP_PAD_PTF2__USB0_ID 0x10003
>;
};
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
>;
};
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2_pte>;
pinctrl-1 = <&pinctrl_usdhc2_pte>;
pinctrl-2 = <&pinctrl_usdhc2_pte>;
pinctrl-3 = <&pinctrl_usdhc2_pte>;
mmc-pwrseq = <&usdhc2_pwrseq>;
max-frequency = <100000000>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
wakeup-source;
status = "okay";
wifi_wake_host {
compatible = "nxp,wifi-wake-host";
interrupt-parent = <&gpioe>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&lpi2c7 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
status = "okay";
pcal6408: gpio@21 {
compatible = "ti,tca6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&flexspi0 {
status = "okay";
flash0: atxp032@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
};
};
&flexspi2 {
status = "okay";
flash1: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <1>;
};
};
};
&usbotg0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg0_id>;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbphy0 {
fsl,tx-d-cal = <88>;
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <88>;
};

4
arch/arm/dts/imx8ulp-pinfunc.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Copyright 2020 NXP
* Copyright 2021 NXP
*/
#ifndef __DTS_IMX8ULP_PINFUNC_H

594
arch/arm/dts/imx8ulp.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
@ -6,6 +6,8 @@
#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
#include "imx8ulp-pinfunc.h"
/ {
@ -14,49 +16,29 @@
#size-cells = <2>;
aliases {
ethernet0 = &fec;
gpio0 = &gpiod;
gpio1 = &gpioe;
gpio2 = &gpiof;
serial0 = &lpuart5;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
spi0 = &flexspi0;
spi2 = &flexspi2;
ethernet0 = &fec;
i2c7 = &lpi2c7;
usbphy0 = &usbphy0;
usb0 = &usbotg0;
usbphy1 = &usbphy1;
usb1 = &usbotg1;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
};
cpus: cpus {
cpus {
#address-cells = <2>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
/* We have 1 clusters with 4 Cortex-A35 cores */
A35_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
};
A35_1: cpu@1 {
@ -65,7 +47,6 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
};
A35_L2: l2-cache0 {
@ -73,37 +54,6 @@
};
};
a35_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-504000000 {
opp-hz = /bits/ 64 <504000000>;
opp-microvolt = <800000>;
clock-latency-ns = <150000>;
};
opp-744000000 {
opp-hz = /bits/ 64 <744000000>;
opp-microvolt = <900000>;
clock-latency-ns = <150000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
s400_mu: mu@27020000 {
u-boot,dm-spl;
compatible = "fsl,imx8ulp-mu";
reg = <0 0x27020000 0 0x10000>;
status = "okay";
};
gic: interrupt-controller@2d400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
@ -113,6 +63,14 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pmu {
compatible = "arm,cortex-a35-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A35_0>, <&A35_1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -154,7 +112,7 @@
#clock-cells = <0>;
};
sram@0x2201f000 {
sram@2201f000 {
compatible = "mmio-sram";
reg = <0x0 0x2201f000 0x0 0x1000>;
@ -162,10 +120,9 @@
#size-cells = <1>;
ranges = <0 0x0 0x2201f000 0x1000>;
/* TODO: split or unify */
scmi_pd: scmi_pd@0 {
scmi_buf: scmi-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
reg = <0x0 0x400>;
};
};
@ -175,41 +132,31 @@
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
shmem = <&scmi_pd>;
shmem = <&scmi_buf>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_perf: protocol@13 {
reg = <0x13>;
scmi_sensor: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
};
};
soc@0 {
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x80000000>;
ranges = <0x0 0x0 0x0 0x40000000>;
per_bridge0: bus@28000000 {
compatible = "simple-bus";
reg = <0x28000000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
flexspi0: flexspi@28039000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8ulp-fspi";
reg = <0x28039000 0x10000>,
<0x04000000 0x7ffffff>;
reg-names = "fspi_base", "fspi_mmap";
status = "disabled";
};
s4muap: mailbox@27020000 {
compatible = "fsl,imx8ulp-mu-s4";
reg = <0x27020000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
per_bridge3: bus@29000000 {
@ -219,110 +166,21 @@
#size-cells = <1>;
ranges;
edma1: dma-controller@29010000 {
compatible = "fsl,imx8ulp-edma";
reg = <0x29010000 0x10000>,
<0x29020000 0x10000>, <0x29030000 0x10000>,
<0x29040000 0x10000>, <0x29050000 0x10000>,
<0x29060000 0x10000>, <0x29070000 0x10000>,
<0x29080000 0x10000>, <0x29090000 0x10000>,
<0x290a0000 0x10000>, <0x290b0000 0x10000>,
<0x290c0000 0x10000>, <0x290d0000 0x10000>,
<0x290e0000 0x10000>, <0x290f0000 0x10000>,
<0x29100000 0x10000>, <0x29110000 0x10000>,
<0x29120000 0x10000>, <0x29130000 0x10000>,
<0x29140000 0x10000>, <0x29150000 0x10000>,
<0x29160000 0x10000>, <0x29170000 0x10000>,
<0x29180000 0x10000>, <0x29190000 0x10000>,
<0x291a0000 0x10000>, <0x291b0000 0x10000>,
<0x291c0000 0x10000>, <0x291d0000 0x10000>,
<0x291e0000 0x10000>, <0x291f0000 0x10000>,
<0x29200000 0x10000>, <0x29210000 0x10000>;
#dma-cells = <3>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
"edma1-chan2-tx", "edma1-chan3-tx",
"edma1-chan4-tx", "edma1-chan5-tx",
"edma1-chan6-tx", "edma1-chan7-tx",
"edma1-chan8-tx", "edma1-chan9-tx",
"edma1-chan10-tx", "edma1-chan11-tx",
"edma1-chan12-tx", "edma1-chan13-tx",
"edma1-chan14-tx", "edma1-chan15-tx",
"edma1-chan16-tx", "edma1-chan17-tx",
"edma1-chan18-tx", "edma1-chan19-tx",
"edma1-chan20-tx", "edma1-chan21-tx",
"edma1-chan22-tx", "edma1-chan23-tx",
"edma1-chan24-tx", "edma1-chan25-tx",
"edma1-chan26-tx", "edma1-chan27-tx",
"edma1-chan28-tx", "edma1-chan29-tx",
"edma1-chan30-tx", "edma1-chan31-tx";
clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
<&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
<&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
<&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
<&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
<&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
<&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
<&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
<&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
<&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
<&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
<&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
<&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
<&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
<&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
<&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
<&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
clock-names = "edma-mp-clk",
"edma1-chan0-clk", "edma1-chan1-clk",
"edma1-chan2-clk", "edma1-chan3-clk",
"edma1-chan4-clk", "edma1-chan5-clk",
"edma1-chan6-clk", "edma1-chan7-clk",
"edma1-chan8-clk", "edma1-chan9-clk",
"edma1-chan10-clk", "edma1-chan11-clk",
"edma1-chan12-clk", "edma1-chan13-clk",
"edma1-chan14-clk", "edma1-chan15-clk",
"edma1-chan16-clk", "edma1-chan17-clk",
"edma1-chan18-clk", "edma1-chan19-clk",
"edma1-chan20-clk", "edma1-chan21-clk",
"edma1-chan22-clk", "edma1-chan23-clk",
"edma1-chan24-clk", "edma1-chan25-clk",
"edma1-chan26-clk", "edma1-chan27-clk",
"edma1-chan28-clk", "edma1-chan29-clk",
"edma1-chan30-clk", "edma1-chan31-clk";
status = "okay";
mu: mailbox@29220000 {
compatible = "fsl,imx8ulp-mu";
reg = <0x29220000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
mu3: mailbox@29230000 {
compatible = "fsl,imx8ulp-mu";
reg = <0x29230000 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
#mbox-cells = <2>;
status = "disabled";
};
wdog3: watchdog@292a0000 {
@ -331,15 +189,13 @@
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
timeout-sec = <40>;
};
cgc1: clock-controller@292c0000 {
compatible = "fsl,imx8ulp-cgc1";
reg = <0x292c0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
clock-names = "rosc", "sosc", "frosc", "lposc";
#clock-cells = <1>;
};
@ -347,6 +203,7 @@
compatible = "fsl,imx8ulp-pcc3";
reg = <0x292d0000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
tpm5: tpm@29340000 {
@ -356,6 +213,33 @@
clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
<&pcc3 IMX8ULP_CLK_TPM5>;
clock-names = "ipg", "per";
status = "disabled";
};
lpi2c4: i2c@29370000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29370000 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
<&pcc3 IMX8ULP_CLK_LPI2C4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c5: i2c@29380000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29380000 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
<&pcc3 IMX8ULP_CLK_LPI2C5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart4: serial@29390000 {
@ -370,10 +254,41 @@
lpuart5: serial@293a0000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x293a0000 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
clock-names = "ipg";
status = "disabled";
};
lpspi4: spi@293b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
reg = <0x293b0000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
<&pcc3 IMX8ULP_CLK_LPSPI4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi5: spi@293c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
reg = <0x293c0000 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
<&pcc3 IMX8ULP_CLK_LPSPI5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
};
per_bridge4: bus@29800000 {
@ -387,77 +302,84 @@
compatible = "fsl,imx8ulp-pcc4";
reg = <0x29800000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
lpi2c6: lpi2c6@29840000 {
lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
<&pcc4 IMX8ULP_CLK_LPI2C6>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c7: lpi2c7@29850000 {
lpi2c7: i2c@29850000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29850000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
<&pcc4 IMX8ULP_CLK_LPI2C7>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
flexspi2: flexspi@29810000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8ulp-fspi";
reg = <0x29810000 0x10000>,
<0x60000000 0xfffffff>;
reg-names = "fspi_base", "fspi_mmap";
lpuart6: serial@29860000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x29860000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
clock-names = "ipg";
status = "disabled";
};
flexspi2_nand: flexspi2_nand@29810000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8-fspi-nand";
reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
reg-names = "FlexSPI", "FlexSPI-memory";
lpuart7: serial@29870000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x29870000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
clock-names = "ipg";
status = "disabled";
};
iomuxc1: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
fsl,mux_mask = <0xf00>;
};
usdhc0: mmc@298d0000 {
compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298d0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>,
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
usdhc1: mmc@298e0000 {
compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298e0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>,
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@ -470,117 +392,50 @@
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>;
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
assigned-clock-rates = <396000000>, <396000000>;
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
usbotg0: usb@29900000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
"fsl,imx27-usb";
reg = <0x29900000 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc0: usbmisc@29900200 {
#index-cells = <1>;
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29900200 0x200>;
};
usbphy0: usbphy@29910000 {
compatible = "fsl,imx8ulp-usbphy",
"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
reg = <0x29910000 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
};
usbotg1: usb@29920000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
"fsl,imx27-usb";
reg = <0x29920000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc1: usbmisc@29920200 {
#index-cells = <1>;
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29920200 0x200>;
};
usbphy1: usbphy@29930000 {
compatible = "fsl,imx8ulp-usbphy",
"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
reg = <0x29930000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
};
fec: ethernet@29950000 {
compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec";
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x29950000 0x10000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_ENET>,
<&pcc4 IMX8ULP_CLK_ENET>,
<&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>,
<&pcc4 IMX8ULP_CLK_ENET>,
<&pcc4 IMX8ULP_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
interrupt-names = "int0";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
status = "disabled";
};
};
gpioe: gpio@2d000000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x2d000080 0x1000 0x2d000040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
<&pcc4 IMX8ULP_CLK_PCTLE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 32 24>;
gpioe: gpio@2d000080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
<&pcc4 IMX8ULP_CLK_PCTLE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 32 24>;
};
gpiof: gpio@2d010000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x2d010080 0x1000 0x2d010040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
<&pcc4 IMX8ULP_CLK_PCTLF>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 64 24>;
gpiof: gpio@2d010080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
<&pcc4 IMX8ULP_CLK_PCTLF>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 64 32>;
};
per_bridge5: bus@2d800000 {
@ -590,117 +445,9 @@
#size-cells = <1>;
ranges;
edma2: dma-controller@2d800000 {
compatible = "fsl,imx8ulp-edma";
reg = <0x2d800000 0x10000>,
<0x2d810000 0x10000>, <0x2d820000 0x10000>,
<0x2d830000 0x10000>, <0x2d840000 0x10000>,
<0x2d850000 0x10000>, <0x2d860000 0x10000>,
<0x2d870000 0x10000>, <0x2d880000 0x10000>,
<0x2d890000 0x10000>, <0x2d8a0000 0x10000>,
<0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>,
<0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>,
<0x2d8f0000 0x10000>, <0x2d900000 0x10000>,
<0x2d910000 0x10000>, <0x2d920000 0x10000>,
<0x2d930000 0x10000>, <0x2d940000 0x10000>,
<0x2d950000 0x10000>, <0x2d960000 0x10000>,
<0x2d970000 0x10000>, <0x2d980000 0x10000>,
<0x2d990000 0x10000>, <0x2d9a0000 0x10000>,
<0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>,
<0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>,
<0x2d9f0000 0x10000>, <0x2da00000 0x10000>;
#dma-cells = <3>;
dma-channels = <32>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
"edma2-chan2-tx", "edma2-chan3-tx",
"edma2-chan4-tx", "edma2-chan5-tx",
"edma2-chan6-tx", "edma2-chan7-tx",
"edma2-chan8-tx", "edma2-chan9-tx",
"edma2-chan10-tx", "edma2-chan11-tx",
"edma2-chan12-tx", "edma2-chan13-tx",
"edma2-chan14-tx", "edma2-chan15-tx",
"edma2-chan16-tx", "edma2-chan17-tx",
"edma2-chan18-tx", "edma2-chan19-tx",
"edma2-chan20-tx", "edma2-chan21-tx",
"edma2-chan22-tx", "edma2-chan23-tx",
"edma2-chan24-tx", "edma2-chan25-tx",
"edma2-chan26-tx", "edma2-chan27-tx",
"edma2-chan28-tx", "edma2-chan29-tx",
"edma2-chan30-tx", "edma2-chan31-tx";
clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
<&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
<&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
<&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
<&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
<&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
<&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
<&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
<&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
<&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
<&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
<&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
<&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
<&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
<&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
<&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
<&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
clock-names = "edma-mp-clk",
"edma2-chan0-clk", "edma2-chan1-clk",
"edma2-chan2-clk", "edma2-chan3-clk",
"edma2-chan4-clk", "edma2-chan5-clk",
"edma2-chan6-clk", "edma2-chan7-clk",
"edma2-chan8-clk", "edma2-chan9-clk",
"edma2-chan10-clk", "edma2-chan11-clk",
"edma2-chan12-clk", "edma2-chan13-clk",
"edma2-chan14-clk", "edma2-chan15-clk",
"edma2-chan16-clk", "edma2-chan17-clk",
"edma2-chan18-clk", "edma2-chan19-clk",
"edma2-chan20-clk", "edma2-chan21-clk",
"edma2-chan22-clk", "edma2-chan23-clk",
"edma2-chan24-clk", "edma2-chan25-clk",
"edma2-chan26-clk", "edma2-chan27-clk",
"edma2-chan28-clk", "edma2-chan29-clk",
"edma2-chan30-clk", "edma2-chan31-clk";
status = "okay";
};
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
clocks = <&sosc>, <&frosc>;
clock-names = "sosc", "frosc";
#clock-cells = <1>;
};
@ -708,12 +455,13 @@
compatible = "fsl,imx8ulp-pcc5";
reg = <0x2da70000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
gpiod: gpio@2e200000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x2e200080 0x1000 0x2e200040 0x40>;
gpiod: gpio@2e200080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

7
arch/arm/dts/imxrt1020-evk-u-boot.dtsi
View File

@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
pinctrl_lpuart1: lpuart1grp {
u-boot,dm-spl;
};
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@ -81,6 +78,10 @@
};
};
&pinctrl_lpuart1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

1
arch/arm/dts/imxrt1020-evk.dts
View File

@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
#include "imxrt1020-pinfunc.h"
/ {

280
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
View File

@ -4,9 +4,18 @@
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <dt-bindings/memory/imxrt-sdram.h>
#include "imxrt1050-pinfunc.h"
/ {
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
};
chosen {
u-boot,dm-spl;
tick-timer = &gpt;
};
clocks {
@ -15,6 +24,92 @@
soc {
u-boot,dm-spl;
usbphy1: usbphy@400d9000 {
compatible = "fsl,imxrt-usbphy";
reg = <0x400d9000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
usbmisc: usbmisc@402e0800 {
#index-cells = <1>;
compatible = "fsl,imxrt-usbmisc";
reg = <0x402e0800 0x200>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
};
usbotg1: usb@402e0000 {
compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
reg = <0x402e0000 0x200>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
lcdif: lcdif@402b8000 {
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
<&clks IMXRT1050_CLK_LCDIF_APB>;
clock-names = "pix", "axi";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
semc: semc@402f0000 {
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
pinctrl-0 = <&pinctrl_semc>;
pinctrl-names = "default";
status = "okay";
};
};
};
&semc {
u-boot,dm-spl;
/*
* Memory configuration from sdram datasheet IS42S16160J-6BLI
*/
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS1
0
0
0
0>;
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8
COL_9BITS
CL_3>;
fsl,sdram-timing = /bits/ 8 <0x2
0x2
0x9
0x1
0x5
0x6
0x20
0x09
0x01
0x00
0x04
0x0A
0x21
0x50>;
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
u-boot,dm-spl;
};
};
@ -31,60 +126,205 @@
};
&gpio1 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio2 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio3 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio4 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpio5 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
&gpt1 {
&gpt {
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
compatible = "fsl,imxrt-lpuart";
clock-names = "per";
u-boot,dm-spl;
};
&semc {
u-boot,dm-spl;
bank1: bank@0 {
u-boot,dm-spl;
};
};
&iomuxc {
u-boot,dm-spl;
compatible = "fsl,imxrt-iomuxc";
pinctrl-0 = <&pinctrl_lpuart1>;
imxrt1050-evk {
pinctrl_semc: semcgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
0xf1 /* SEMC_A1 */
MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
0xf1 /* SEMC_A2 */
MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
0xf1 /* SEMC_A3 */
MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
0xf1 /* SEMC_A4 */
MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
0xf1 /* SEMC_A5 */
MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
0xf1 /* SEMC_A6 */
MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
0xf1 /* SEMC_A7 */
MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
0xf1 /* SEMC_A8 */
MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
0xf1 /* SEMC_A9 */
MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
0xf1 /* SEMC_A11 */
MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
0xf1 /* SEMC_A12 */
MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
0xf1 /* SEMC_BA0 */
MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
0xf1 /* SEMC_BA1 */
MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
0xf1 /* SEMC_A10 */
MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
0xf1 /* SEMC_CAS */
MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
0xf1 /* SEMC_RAS */
MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
0xf1 /* SEMC_CLK */
MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
0xf1 /* SEMC_CKE */
MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
0xf1 /* SEMC_WE */
MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
0xf1 /* SEMC_CS0 */
MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
0xf1 /* SEMC_D8 */
MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
0xf1 /* SEMC_D9 */
MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
0xf1 /* SEMC_D10 */
MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
0xf1 /* SEMC_D11 */
MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
0xf1 /* SEMC_D12 */
MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
0xf1 /* SEMC_D13 */
MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
0xf1 /* SEMC_D14 */
MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
0xf1 /* SEMC_D15 */
MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
0xf1 /* SEMC_DM1 */
MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>;
u-boot,dm-spl;
pinctrl_lpuart1: lpuart1grp {
u-boot,dm-spl;
};
};
pinctrl_semc: semcgrp {
u-boot,dm-spl;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>;
};
pinctrl_usdhc0: usdhc0grp {
u-boot,dm-spl;
pinctrl_lpuart1: lpuart1grp {
u-boot,dm-spl;
};
pinctrl_usdhc0: usdhc0grp {
u-boot,dm-spl;
};
};
&usdhc1 {
compatible = "fsl,imxrt-usdhc";
u-boot,dm-spl;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
timing0: timing0 {
clock-frequency = <9300000>;
hactive = <480>;
vactive = <272>;
hback-porch = <4>;
hfront-porch = <8>;
vback-porch = <4>;
vfront-porch = <8>;
hsync-len = <41>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&usdhc1 {
u-boot,dm-spl;
&usbotg1 {
dr_mode = "host";
status = "okay";
};

257
arch/arm/dts/imxrt1050-evk.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-evk-u-boot.dtsi"
#include "imxrt1050-pinfunc.h"
/ {
@ -14,210 +13,52 @@
compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
tick-timer = &gpt1;
stdout-path = &lpuart1;
};
memory {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
mmc0 = &usdhc1;
serial0 = &lpuart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x2000000>;
};
};
&lpuart1 { /* console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&semc {
/*
* Memory configuration from sdram datasheet IS42S16160J-6BLI
*/
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS1
0
0
0
0>;
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8
COL_9BITS
CL_3>;
fsl,sdram-timing = /bits/ 8 <0x2
0x2
0x9
0x1
0x5
0x6
0x20
0x09
0x01
0x00
0x04
0x0A
0x21
0x50>;
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
imxrt1050-evk {
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
0xf1
MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
0xf1
>;
};
pinctrl_semc: semcgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
0xf1 /* SEMC_A1 */
MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
0xf1 /* SEMC_A2 */
MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
0xf1 /* SEMC_A3 */
MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
0xf1 /* SEMC_A4 */
MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
0xf1 /* SEMC_A5 */
MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
0xf1 /* SEMC_A6 */
MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
0xf1 /* SEMC_A7 */
MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
0xf1 /* SEMC_A8 */
MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
0xf1 /* SEMC_A9 */
MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
0xf1 /* SEMC_A11 */
MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
0xf1 /* SEMC_A12 */
MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
0xf1 /* SEMC_BA0 */
MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
0xf1 /* SEMC_BA1 */
MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
0xf1 /* SEMC_A10 */
MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
0xf1 /* SEMC_CAS */
MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
0xf1 /* SEMC_RAS */
MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
0xf1 /* SEMC_CLK */
MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
0xf1 /* SEMC_CKE */
MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
0xf1 /* SEMC_WE */
MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
0xf1 /* SEMC_CS0 */
MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
0xf1 /* SEMC_D8 */
MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
0xf1 /* SEMC_D9 */
MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
0xf1 /* SEMC_D10 */
MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
0xf1 /* SEMC_D11 */
MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
0xf1 /* SEMC_D12 */
MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
0xf1 /* SEMC_D13 */
MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
0xf1 /* SEMC_D14 */
MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
0xf1 /* SEMC_D15 */
MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
0xf1 /* SEMC_DM1 */
MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
0x1B000
MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
0xB069
MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
0x17061
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
>;
};
};
&gpt1 {
status = "okay";
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
>;
};
};
&usdhc1 {
@ -226,42 +67,6 @@
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
status = "okay";
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
timing0: timing0 {
clock-frequency = <9300000>;
hactive = <480>;
vactive = <272>;
hback-porch = <4>;
hfront-porch = <8>;
vback-porch = <4>;
vfront-porch = <8>;
hsync-len = <41>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
};

2
arch/arm/dts/imxrt1050-pinfunc.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>

164
arch/arm/dts/imxrt1050.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
@ -8,53 +8,37 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
display0 = &lcdif;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
mmc0 = &usdhc1;
serial0 = &lpuart1;
usbphy0 = &usbphy1;
};
clocks {
osc: osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
osc3M: osc3M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
};
soc {
semc: semc@402f0000 {
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
pinctrl-0 = <&pinctrl_semc>;
pinctrl-names = "default";
status = "okay";
};
lpuart1: serial@40184000 {
compatible = "fsl,imxrt-lpuart";
compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <20>;
clocks = <&clks IMXRT1050_CLK_LPUART1>;
clock-names = "per";
clock-names = "ipg";
status = "disabled";
};
iomuxc: iomuxc@401f8000 {
compatible = "fsl,imxrt-iomuxc";
iomuxc: pinctrl@401f8000 {
compatible = "fsl,imxrt1050-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
@ -64,31 +48,61 @@
reg = <0x400d8000 0x4000>;
};
clks: ccm@400fc000 {
clks: clock-controller@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <95>, <96>;
clocks = <&osc>;
clock-names = "osc";
#clock-cells = <1>;
assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
<&clks IMXRT1050_CLK_PLL1_BYPASS>,
<&clks IMXRT1050_CLK_PLL2_BYPASS>,
<&clks IMXRT1050_CLK_PLL3_BYPASS>,
<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
<&clks IMXRT1050_CLK_PLL1_ARM>,
<&clks IMXRT1050_CLK_PLL2_SYS>,
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
<&clks IMXRT1050_CLK_PLL2_SYS>;
};
usdhc1: usdhc@402c0000 {
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_USDHC1>;
clock-names = "per";
edma1: dma-controller@400e8000 {
#dma-cells = <2>;
compatible = "fsl,imx7ulp-edma";
reg = <0x400e8000 0x4000>,
<0x400ec000 0x4000>;
dma-channels = <32>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
clock-names = "dma", "dmamux0";
clocks = <&clks IMXRT1050_CLK_DMA>,
<&clks IMXRT1050_CLK_DMA_MUX>;
};
usdhc1: mmc@402c0000 {
compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
reg = <0x402c0000 0x4000>;
interrupts = <110>;
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
<&clks IMXRT1050_CLK_OSC>,
<&clks IMXRT1050_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,wp-controller;
no-1-8-v;
max-frequency = <4000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
gpio1: gpio@401b8000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <80>, <81>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -96,10 +110,9 @@
};
gpio2: gpio@401bc000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <82>, <83>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -107,10 +120,9 @@
};
gpio3: gpio@401c0000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <84>, <85>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -118,10 +130,9 @@
};
gpio4: gpio@401c4000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <86>, <87>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -129,60 +140,21 @@
};
gpio5: gpio@400c0000 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <88>, <89>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
lcdif: lcdif@402b8000 {
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
<&clks IMXRT1050_CLK_LCDIF_APB>;
clock-names = "pix", "axi";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
gpt1: gpt1@401ec000 {
compatible = "fsl,imxrt-gpt";
gpt: timer@401ec000 {
compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100>;
clocks = <&osc>;
status = "disabled";
};
usbphy1: usbphy@400d9000 {
compatible = "fsl,imxrt-usbphy";
reg = <0x400d9000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
usbmisc: usbmisc@402e0800 {
#index-cells = <1>;
compatible = "fsl,imxrt-usbmisc";
reg = <0x402e0800 0x200>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
};
usbotg1: usb@402e0000 {
compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
reg = <0x402e0000 0x200>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
clocks = <&osc3M>;
clock-names = "per";
};
};
};

2
arch/arm/dts/vf610-pinfunc.h
View File

@ -802,7 +802,6 @@
#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0
#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0
#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0
@ -853,4 +852,5 @@
#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0
#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0
#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0
#endif

6
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -44,10 +44,14 @@
#define I2C3_BASE_ADDR 0x30A40000
#define I2C4_BASE_ADDR 0x30A50000
#define UART4_BASE_ADDR 0x30A60000
#ifdef CONFIG_IMX8MP
#define I2C5_BASE_ADDR 0x30AD0000
#define I2C6_BASE_ADDR 0x30AE0000
#endif
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
#define QSPI0_AMBA_BASE 0x08000000
#ifdef CONFIG_IMX8MM
#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP)
#define USDHC3_BASE_ADDR 0x30B60000
#endif
#define UART_BASE_ADDR(n) ( \

6
arch/arm/mach-imx/i2c-mxv7.c
View File

@ -70,6 +70,12 @@ static void * const i2c_bases[] = {
#ifdef I2C4_BASE_ADDR
(void *)I2C4_BASE_ADDR,
#endif
#ifdef I2C5_BASE_ADDR
(void *)I2C5_BASE_ADDR,
#endif
#ifdef I2C6_BASE_ADDR
(void *)I2C6_BASE_ADDR,
#endif
};
/* i2c_index can be from 0 - 3 */

8
arch/arm/mach-imx/imx8/Kconfig
View File

@ -46,28 +46,33 @@ choice
config TARGET_APALIS_IMX8
bool "Support Apalis iMX8 module"
select BINMAN
select BOARD_LATE_INIT
select IMX8QM
config TARGET_COLIBRI_IMX8X
bool "Support Colibri iMX8X module"
select BINMAN
select BOARD_LATE_INIT
select IMX8QXP
config TARGET_DENEB
bool "Support i.MX8QXP Capricorn Deneb board"
select BINMAN
select BOARD_LATE_INIT
select FACTORYSET
select IMX8QXP
config TARGET_GIEDI
bool "Support i.MX8QXP Capricorn Giedi board"
select BINMAN
select BOARD_LATE_INIT
select FACTORYSET
select IMX8QXP
config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BINMAN
select BOARD_LATE_INIT
select IMX8QM
select FSL_CAAM
@ -76,18 +81,21 @@ config TARGET_IMX8QM_MEK
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
select BINMAN
select BOARD_LATE_INIT
select SUPPORT_SPL
select IMX8QM
config TARGET_IMX8QM_ROM7720_A1
bool "Support i.MX8QM ROM-7720-A1"
select BINMAN
select BOARD_LATE_INIT
select SUPPORT_SPL
select IMX8QM
config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BINMAN
select BOARD_LATE_INIT
select IMX8QXP
select FSL_CAAM

9
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -4,6 +4,7 @@ config IMX8M
bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
select ARMV8_CRYPTO
config IMX8MQ
bool
@ -284,6 +285,13 @@ config TARGET_IMX8MP_RSB3720A1_6G
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_MSC_SM2S_IMX8MP
bool "MSC SMARC2 i.MX8MPLUS"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_LIBREM5
bool "Purism Librem5 Phone"
select BINMAN
@ -311,6 +319,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
source "board/msc/sm2s_imx8mp/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/purism/librem5/Kconfig"

12
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -36,11 +36,17 @@ void enable_ocotp_clk(unsigned char enable)
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
/* 0 - 3 is valid i2c num */
if (i2c_num > 3)
u8 i2c_ccgr[6] = {
CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
#if (IS_ENABLED(CONFIG_IMX8MP))
CCGR_I2C5_8MP, CCGR_I2C6_8MP
#endif
};
if (i2c_num > ARRAY_SIZE(i2c_ccgr))
return -EINVAL;
clock_enable(CCGR_I2C1 + i2c_num, !!enable);
clock_enable(i2c_ccgr[i2c_num], !!enable);
return 0;
}

9
arch/arm/mach-imx/mx7/psci-mx7.c
View File

@ -643,8 +643,10 @@ __secure void psci_system_suspend(u32 __always_unused function_id,
/* disable GIC distributor */
writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET);
for (i = 0; i < 4; i++)
for (i = 0; i < 4; i++) {
gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
}
/*
* enable the RBC bypass counter here
@ -668,7 +670,7 @@ __secure void psci_system_suspend(u32 __always_unused function_id,
writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
/*
* now delay for a short while (3usec)
* now delay for a short while (~3usec)
* ARM is at 1GHz at this point
* so a short loop should be enough.
* this delay is required to ensure that
@ -677,7 +679,8 @@ __secure void psci_system_suspend(u32 __always_unused function_id,
* or in case an interrupt arrives just
* as ARM is about to assert DSM_request.
*/
imx_udelay(3);
for (i = 0; i < 2000; i++)
asm volatile("");
/* save resume entry and sp in CPU0 GPR registers */
asm volatile("mov %0, sp" : "=r" (val));

4
board/advantech/imx8qm_rom7720_a1/imximage.cfg
View File

@ -4,8 +4,8 @@
*/
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
BOOT_FROM sd
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */

7
board/beacon/imx8mm/spl.c
View File

@ -34,6 +34,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC2;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
default:
return BOOT_DEVICE_NONE;
}
@ -44,11 +46,6 @@ static void spl_dram_init(void)
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
debug("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{

35
board/beacon/imx8mn/spl.c
View File

@ -74,6 +74,38 @@ static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
static int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@4b", &dev);
if (ret == -ENODEV) {
puts("No pmic\n");
return 0;
}
if (ret != 0)
return ret;
/* decrease RESET key long push time from the default 10s to 10ms */
pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
/* unlock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
/* increase VDD_SOC to typical value 0.85v before first DRAM access */
pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
/* lock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
return 0;
}
int board_early_init_f(void)
{
/* Claiming pwm pins prevents LCD flicker during startup*/
@ -107,6 +139,9 @@ void board_init_f(ulong dummy)
enable_tzc380();
/* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */
power_init_board();
/* DDR initialization */
spl_dram_init();

4
board/congatec/cgtqmx8/imximage.cfg
View File

@ -4,8 +4,8 @@
*/
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
BOOT_FROM sd
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */

2
board/freescale/imx8qm_mek/README
View File

@ -40,7 +40,7 @@ And copy the following firmwares to U-Boot folder:
Build U-Boot
============
$ make imx8qm_mek_defconfig
$ make flash.bin
$ make
Flash the binary into the SD card
=================================

3
board/freescale/imx8qxp_mek/imximage.cfg
View File

@ -7,8 +7,7 @@
*/
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
BOOT_FROM sd
/* SoC type IMX8QX */
SOC_TYPE IMX8QX
/* Append seco container image */

16
board/gateworks/venice/venice.c
View File

@ -179,22 +179,6 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
/* set board model dt prop */
fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
/* update temp thresholds */
off = fdt_path_offset(fdt, "/thermal-zones/cpu-thermal/trips");
if (off >= 0) {
int minc, maxc, prop;
get_cpu_temp_grade(&minc, &maxc);
fdt_for_each_subnode(prop, fdt, off) {
const char *type = fdt_getprop(fdt, prop, "type", NULL);
if (type && (!strcmp("critical", type)))
fdt_setprop_u32(fdt, prop, "temperature", maxc * 1000);
else if (type && (!strcmp("passive", type)))
fdt_setprop_u32(fdt, prop, "temperature", (maxc - 10) * 1000);
}
}
if (!strncmp(base_model, "GW73", 4)) {
pcbrev = get_pcb_rev(base_model);

34
board/gateworks/venice/venice.env Normal file
View File

@ -0,0 +1,34 @@
kernel_addr_r=0x48200000
fdt_addr_r=0x50200000
scriptaddr=0x50280000
ramdisk_addr_r=0x50300000
kernel_comp_addr_r=0x40200000
script=boot.scr
bootm_size=0x10000000
dev=2
preboot=gsc wd-disable
console=ttymxc1,115200
update_firmware=tftpboot $loadaddr $image &&
setexpr blkcnt $filesize + 0x1ff &&
setexpr blkcnt $blkcnt / 0x200 &&
mmc dev $dev &&
mmc write $loadaddr $splblk $blkcnt
loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1;
then echo loaded $fdt_file1;
elif $fsload $fdt_addr_r $dir/$fdt_file2;
then echo loaded $fdt_file2;
elif $fsload $fdt_addr_r $dir/$fdt_file3;
then echo loaded $fdt_file3;
elif $fsload $fdt_addr_r $dir/$fdt_file4;
then echo loaded $fdt_file4;
elif $fsload $fdt_addr_r $dir/$fdt_file5;
then echo loaded $fdt_file5;
fi
boot_net=setenv fsload tftpboot;
run loadfdt && tftpboot $kernel_addr_r $dir/Image &&
booti $kernel_addr_r - $fdt_addr_r
update_rootfs=tftpboot $loadaddr $image &&
gzwrite mmc $dev $loadaddr $filesize 100000 1000000
update_all=tftpboot $loadaddr $image &&
gzwrite mmc $dev $loadaddr $filesize
erase_env=mmc dev $dev; mmc erase 0x7f08 0x40

15
board/msc/sm2s_imx8mp/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_MSC_SM2S_IMX8MP
config SYS_BOARD
default "sm2s_imx8mp"
config SYS_VENDOR
default "msc"
config SYS_CONFIG_NAME
default "msc_sm2s_imx8mp"
config IMX_CONFIG
default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg"
endif

11
board/msc/sm2s_imx8mp/Makefile Normal file
View File

@ -0,0 +1,11 @@
#
# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
#
# SPDX-License-Identifier: GPL-2.0
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o lpddr4_timing.o
else
obj-y += sm2s_imx8mp.o
endif

8
board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg Normal file
View File

@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
ROM_VERSION v2
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x920000

1842
board/msc/sm2s_imx8mp/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
board/msc/sm2s_imx8mp/sm2s_imx8mp.c Normal file
View File

@ -0,0 +1,60 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on vendor support provided by AVNET Embedded
*
* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
* Copyright 2021 General Electric Company
* Copyright 2021 Collabora Ltd.
*/
#include <common.h>
#include <errno.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_init(void)
{
setup_fec();
setup_eqos();
return 0;
}

273
board/msc/sm2s_imx8mp/spl.c Normal file
View File

@ -0,0 +1,273 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on vendor support provided by AVNET Embedded
*
* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
* Copyright 2021 General Electric Company
* Copyright 2021 Collabora Ltd.
*/
#include <common.h>
#include <cpu_func.h>
#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <i2c.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <mmc.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/rn5t567_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
* set by ROM for ND VDD_SOC
*/
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
puts("Normal Boot\n");
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \
| PAD_CTL_PE | PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \
| PAD_CTL_DSE4)
static const iomux_v3_cfg_t usdhc2_pads[] = {
MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19)
static const iomux_v3_cfg_t usdhc3_pads[] = {
MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC2_BASE_ADDR, 0, 4 },
{ USDHC3_BASE_ADDR, 0, 8 },
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 (sd) USDHC2
* mmc1 (emmc) USDHC3
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_RESET_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_RESET_GPIO, 1);
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
gpio_direction_input(USDHC2_CD_GPIO);
break;
case 1:
init_clk_usdhc(2);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
ARRAY_SIZE(usdhc3_pads));
break;
default:
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = 1;
break;
}
return ret;
}
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
static const iomux_v3_cfg_t ser0_pads[] = {
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
return 0;
}
static const iomux_v3_cfg_t reset_out_pad[] = {
MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19)
};
#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27)
static void pulse_reset_out(void)
{
imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad));
gpio_request(RESET_OUT_GPIO, "reset_out_gpio");
gpio_direction_output(RESET_OUT_GPIO, 0);
udelay(10);
gpio_direction_output(RESET_OUT_GPIO, 1);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_dev_pads = {
.scl = {
.i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC,
.gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC,
.gp = IMX_GPIO_NR(3, 19),
},
.sda = {
.i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC,
.gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC,
.gp = IMX_GPIO_NR(3, 20),
},
};
int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev);
if (ret) {
printf("Error: Failed to get PMIC\n");
return ret;
}
/* set VCC_DRAM (buck2) to 1.1V */
pmic_reg_write(dev, RN5T567_DC2DAC, 0x28);
/* set VCC_ARM (buck2) to 0.95V */
pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C);
return 0;
}
int board_fit_config_name_match(const char *name)
{
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
init_uart_clk(1);
board_early_init_f();
pulse_reset_out();
timer_init();
ret = spl_early_init();
if (ret) {
printf("Error: failed to initialize SPL!\n");
hang();
}
preloader_console_init();
enable_tzc380();
power_init_board();
spl_dram_init();
}

2
board/siemens/capricorn/imximage.cfg
View File

@ -8,7 +8,7 @@
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
BOOT_FROM sd
/* SoC type IMX8QX */
SOC_TYPE IMX8QX
/* Append seco container image */

3
board/solidrun/mx6cuboxi/mx6cuboxi.c
View File

@ -844,6 +844,9 @@ void board_init_f(ulong dummy)
/* setup GP timer */
timer_init();
/* Enable device tree and early DM support*/
spl_early_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();

1
configs/apalis-imx8_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y

4
configs/cgtqmx8_defconfig
View File

@ -20,8 +20,10 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
# CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y

1
configs/colibri-imx8x_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set

2
configs/deneb_defconfig
View File

@ -26,6 +26,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3

1
configs/dh_imx6_defconfig
View File

@ -67,6 +67,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_VERSION_VARIABLE=y
CONFIG_ARP_TIMEOUT=200
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y

2
configs/giedi_defconfig
View File

@ -26,6 +26,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3

24
configs/imx8mm_beacon_defconfig
View File

@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x7E1000
@ -30,7 +30,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x920000
CONFIG_SYS_SPL_MALLOC=y
@ -41,6 +40,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@ -58,6 +60,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -74,7 +77,8 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
@ -89,12 +93,9 @@ CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@ -108,20 +109,20 @@ CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_SPL_PHY=y
CONFIG_SPL_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_SPL_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
@ -134,12 +135,13 @@ CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y

1
configs/imx8mm_venice_defconfig
View File

@ -62,6 +62,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y

8
configs/imx8mn_beacon_2g_defconfig
View File

@ -16,10 +16,9 @@ CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
@ -36,12 +35,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x95e000
CONFIG_SPL_BSS_START_ADDR=0x950000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x980000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
@ -122,6 +121,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y

8
configs/imx8mn_beacon_defconfig
View File

@ -15,10 +15,9 @@ CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
@ -35,12 +34,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x95e000
CONFIG_SPL_BSS_START_ADDR=0x950000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x980000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
@ -126,6 +125,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y

1
configs/imx8mn_venice_defconfig
View File

@ -65,6 +65,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y

1
configs/imx8mp_venice_defconfig
View File

@ -64,6 +64,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y

2
configs/imx8qm_mek_defconfig
View File

@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3

3
configs/imx8qm_rom7720_a1_4G_defconfig
View File

@ -20,8 +20,9 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"

2
configs/imx8qxp_mek_defconfig
View File

@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3

106
configs/msc_sm2s_imx8mp_defconfig Normal file
View File

@ -0,0 +1,106 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_MSC_SM2S_IMX8MP=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb"
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x0098FC00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x960000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_SYS_BOOTM_LEN=0x2000000
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_TI=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RN5T567=y
CONFIG_SPL_PMIC_RN5T567=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y

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