From a887f2ac3e6c2479476ff0ef82c1d2e23178b6f9 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 22 Sep 2022 11:18:46 +0200 Subject: [PATCH 01/43] configs: imx8m: Enable CONFIG_ARMV8_CRYPTO support This enables armv8 crypto extension usage for SHA1/SHA256. Which speed up sha1/sha256 operations, about 10x faster with a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms). Signed-off-by: Loic Poulain Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8cd7c7a8dd..fbe676d7be 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -4,6 +4,7 @@ config IMX8M bool select HAS_CAAM select ROM_UNIFIED_SECTIONS + select ARMV8_CRYPTO config IMX8MQ bool From 975f4117d5592312acd14d715fd7498361a77b57 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 26 Sep 2022 10:31:08 +0200 Subject: [PATCH 02/43] ARM: mx7: psci: fix suspend/resume e10133 workaround The e10133 workaround was broken in two places: - The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0. While the old register values were saved, the actual masking was missing. - imx_udelay() expects the system counter to run at its base frequency, but the system counter is switched to a lower frequency earlier in psci_system_suspend(), leading to a much longer delay than intended. Replace the call with an equivalent loop (linux-imx 5.15 does the same) This fixes the SoC hanging forever when there was already a wakeup IRQ pending while suspending. Fixes: 57b620255e ("imx: mx7: add system suspend/resume support") Signed-off-by: Matthias Schiffer --- arch/arm/mach-imx/mx7/psci-mx7.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index f32945ea37..699a2569cb 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -643,8 +643,10 @@ __secure void psci_system_suspend(u32 __always_unused function_id, /* disable GIC distributor */ writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET); - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i++) { gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); + } /* * enable the RBC bypass counter here @@ -668,7 +670,7 @@ __secure void psci_system_suspend(u32 __always_unused function_id, writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); /* - * now delay for a short while (3usec) + * now delay for a short while (~3usec) * ARM is at 1GHz at this point * so a short loop should be enough. * this delay is required to ensure that @@ -677,7 +679,8 @@ __secure void psci_system_suspend(u32 __always_unused function_id, * or in case an interrupt arrives just * as ARM is about to assert DSM_request. */ - imx_udelay(3); + for (i = 0; i < 2000; i++) + asm volatile(""); /* save resume entry and sp in CPU0 GPR registers */ asm volatile("mov %0, sp" : "=r" (val)); From 4dbe07f275b8d6449d1b61f181f442b5a9ade35f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 08:43:42 -0500 Subject: [PATCH 03/43] regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled If the bd718x7 is required, but PMIC_CHILDREN is disabled, this driver throws a compile error. Fix this by putting the function to bind children into an if-statement checking for PMIC_CHILDREN. Allowing PMIC_CHILDREN to be disabled in SPL saves some space and still permits some read/write functions to access the PMIC in early startup. Signed-off-by: Adam Ford Reviewed-by: Simon Glass Reviewed-by: Fabio Estevam --- drivers/power/pmic/bd71837.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index cb9238972f..fdbbd6f559 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -63,10 +63,11 @@ static int bd71837_bind(struct udevice *dev) debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); - children = pmic_bind_children(dev, regulators_node, pmic_children_info); - if (!children) - debug("%s: %s - no child found\n", __func__, dev->name); - + if (CONFIG_IS_ENABLED(PMIC_CHILDREN)) { + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + } /* Always return success for this device */ return 0; } From a5685ea4882f68ac5b34d5e8613e357962f55e9d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 08:43:44 -0500 Subject: [PATCH 04/43] imx: imx8mn-beacon: Fix out of spec voltage The DDR is configured for LPDDR4 running at 1.6GHz which requires the voltage on the PMIC to rise a bit before initializing LPDDR4 or it will be running out of spec. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- board/beacon/imx8mn/spl.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index 029f71bc99..9acd916180 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -74,6 +74,38 @@ static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), }; +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@4b", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + + if (ret != 0) + return ret; + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + + /* lock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + + return 0; +} + int board_early_init_f(void) { /* Claiming pwm pins prevents LCD flicker during startup*/ @@ -107,6 +139,9 @@ void board_init_f(ulong dummy) enable_tzc380(); + /* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */ + power_init_board(); + /* DDR initialization */ spl_dram_init(); From b6c8a280905562c3833bb3da994691de60e5fd8d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 09:28:22 -0500 Subject: [PATCH 05/43] imx: imx8mm_beacon: Eliminate a few extras to free up SPL space There are a few functions which are not essential for use in SPL, but they take up enough space to make other preferred features not fit. Remove the extras. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- board/beacon/imx8mm/spl.c | 5 ----- configs/imx8mm_beacon_defconfig | 8 +------- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index a93cc93878..b0e9d918da 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -44,11 +44,6 @@ static void spl_dram_init(void) ddr_init(&dram_timing); } -void spl_board_init(void) -{ - debug("Normal Boot\n"); -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index b66f8bfea0..5bbaa293ac 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -29,7 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x920000 CONFIG_SYS_SPL_MALLOC=y @@ -88,12 +87,9 @@ CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y -CONFIG_SPL_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_SPL_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y @@ -113,14 +109,12 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y -CONFIG_SPL_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y From 3a7943a90c1508a0719f3038b6f5f0662ab9167d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 09:28:23 -0500 Subject: [PATCH 06/43] imx: imx8mm-beacon: Enable USB booting via SDP In order to boot over USB, the device tree needs to enable a few extra nodes in SPL. Since the USB driver has the ability to detect host/device, the dr_mode can be removed from the device tree since it needs to act as a device when booting and OTG is the default mode. Add USB boot support to spl_board_boot_device and enable the corresponding config options. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 18 +++++++++++++++++- board/beacon/imx8mm/spl.c | 2 ++ configs/imx8mm_beacon_defconfig | 9 ++++++++- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index c94b4ffa4c..00ac413f36 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -13,6 +13,10 @@ }; }; +&aips4 { + u-boot,dm-spl; +}; + ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; @@ -77,12 +81,24 @@ u-boot,dm-spl; }; +®_usbotg1 { + +}; + &uart2 { u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + &usbotg1 { - dr_mode="host"; + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; }; &usdhc2 { diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index b0e9d918da..a5f337aa17 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -34,6 +34,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 5bbaa293ac..cfb0eea99e 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -39,6 +39,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -56,6 +59,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -103,6 +107,8 @@ CONFIG_PHY_ATHEROS=y CONFIG_PHY_GIGE=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -127,12 +133,13 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y From 78f34793ed7ebbe48290aed6dd73bc6092cbc84a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 09:28:24 -0500 Subject: [PATCH 07/43] imx: imx8mm-beacon: Move Environment to eMMC partition 2 The downstream U-Boot distributed by Beacon stores the environment in the eMMC and the end of partition 2. This allow the environment to stay on the SOM regardless of the boot source. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- configs/imx8mm_beacon_defconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index cfb0eea99e..737f578d3a 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" CONFIG_SPL_TEXT_BASE=0x7E1000 @@ -76,7 +76,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" From 03a7a8297026048e4b78a04af809e42467e839a3 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 25 Oct 2022 10:54:58 +0100 Subject: [PATCH 08/43] imx8m: USDHC3 base address definition for i.MX8MP The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 29d5baaab8..c46d4f7e00 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -47,7 +47,7 @@ #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 #define QSPI0_AMBA_BASE 0x08000000 -#ifdef CONFIG_IMX8MM +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP) #define USDHC3_BASE_ADDR 0x30B60000 #endif #define UART_BASE_ADDR(n) ( \ From c92c3a4453b86d977b529b9c48db94a2a1b0b8d0 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 25 Oct 2022 10:54:59 +0100 Subject: [PATCH 09/43] ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 4 ++++ arch/arm/mach-imx/i2c-mxv7.c | 6 ++++++ arch/arm/mach-imx/imx8m/clock_imx8mm.c | 12 +++++++++--- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index c46d4f7e00..6595d97f0a 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -44,6 +44,10 @@ #define I2C3_BASE_ADDR 0x30A40000 #define I2C4_BASE_ADDR 0x30A50000 #define UART4_BASE_ADDR 0x30A60000 +#ifdef CONFIG_IMX8MP +#define I2C5_BASE_ADDR 0x30AD0000 +#define I2C6_BASE_ADDR 0x30AE0000 +#endif #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 #define QSPI0_AMBA_BASE 0x08000000 diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index 85d648b56e..a5866cf9f7 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -70,6 +70,12 @@ static void * const i2c_bases[] = { #ifdef I2C4_BASE_ADDR (void *)I2C4_BASE_ADDR, #endif +#ifdef I2C5_BASE_ADDR + (void *)I2C5_BASE_ADDR, +#endif +#ifdef I2C6_BASE_ADDR + (void *)I2C6_BASE_ADDR, +#endif }; /* i2c_index can be from 0 - 3 */ diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 4db55f8608..64ad57e9b3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -36,11 +36,17 @@ void enable_ocotp_clk(unsigned char enable) int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { - /* 0 - 3 is valid i2c num */ - if (i2c_num > 3) + u8 i2c_ccgr[6] = { + CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4, +#if (IS_ENABLED(CONFIG_IMX8MP)) + CCGR_I2C5_8MP, CCGR_I2C6_8MP +#endif + }; + + if (i2c_num > ARRAY_SIZE(i2c_ccgr)) return -EINVAL; - clock_enable(CCGR_I2C1 + i2c_num, !!enable); + clock_enable(i2c_ccgr[i2c_num], !!enable); return 0; } From da470ddbb3b83ae4f8ce0de5ed33eb69f426c69a Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 25 Oct 2022 10:55:00 +0100 Subject: [PATCH 10/43] drivers: power: pmic: Add support for rn5t568 PMIC Add support for the rn5t568 PMIC to the rn5t567 driver. Signed-off-by: Martyn Welch Reviewed-by: Jaehoon Chung --- drivers/power/pmic/rn5t567.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c index d9a8298ebb..9d103dd840 100644 --- a/drivers/power/pmic/rn5t567.c +++ b/drivers/power/pmic/rn5t567.c @@ -53,6 +53,7 @@ static struct dm_pmic_ops rn5t567_ops = { static const struct udevice_id rn5t567_ids[] = { { .compatible = "ricoh,rn5t567" }, + { .compatible = "ricoh,rn5t568" }, { } }; From e0554577598adf3b559d0a8b705e4078ef9fba17 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 25 Oct 2022 10:55:01 +0100 Subject: [PATCH 11/43] drivers: power: pmic: Enable use of rn5t567 PMIC in SPL The support added later in this series tweaks the PMIC voltages in the SPL. Enable support for the rn5t567 in SPL builds to allow this to be done cleanly. Signed-off-by: Martyn Welch Reviewed-by: Simon Glass Reviewed-by: Jaehoon Chung --- drivers/power/pmic/Kconfig | 8 ++++++++ drivers/power/pmic/Makefile | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 0478f2aa1d..628d3a94bc 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -300,6 +300,14 @@ config PMIC_RN5T567 regulators Real-Time Clock and 4 GPIOs. This driver provides register access only. +config SPL_PMIC_RN5T567 + bool "Enable driver for Ricoh RN5T567 PMIC in SPL" + depends on SPL_DM_PMIC + ---help--- + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. + config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" ---help--- diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e1d3545490..58c6507c58 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o -obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o +obj-$(CONFIG_$(SPL_)PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o From c8f3402ad294b0dd9484e22d338040aa89bae2cf Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 25 Oct 2022 10:55:02 +0100 Subject: [PATCH 12/43] arm: imx8mp: Initial MSC SM2S iMX8MP support Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch Signed-off-by: Fabio Estevam --- MAINTAINERS | 9 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi | 65 + arch/arm/dts/imx8mp-msc-sm2s.dts | 820 ++++++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/msc/sm2s_imx8mp/Kconfig | 15 + board/msc/sm2s_imx8mp/Makefile | 11 + board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg | 8 + board/msc/sm2s_imx8mp/lpddr4_timing.c | 1842 +++++++++++++++++ board/msc/sm2s_imx8mp/sm2s_imx8mp.c | 60 + board/msc/sm2s_imx8mp/spl.c | 273 +++ configs/msc_sm2s_imx8mp_defconfig | 105 + include/configs/msc_sm2s_imx8mp.h | 64 + 13 files changed, 3281 insertions(+) create mode 100644 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-msc-sm2s.dts create mode 100644 board/msc/sm2s_imx8mp/Kconfig create mode 100644 board/msc/sm2s_imx8mp/Makefile create mode 100644 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg create mode 100644 board/msc/sm2s_imx8mp/lpddr4_timing.c create mode 100644 board/msc/sm2s_imx8mp/sm2s_imx8mp.c create mode 100644 board/msc/sm2s_imx8mp/spl.c create mode 100644 configs/msc_sm2s_imx8mp_defconfig create mode 100644 include/configs/msc_sm2s_imx8mp.h diff --git a/MAINTAINERS b/MAINTAINERS index 8d3d528650..a377afbb50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -413,6 +413,15 @@ F: drivers/timer/atmel_tcb_timer.c F: include/dt-bindings/mfd/atmel-flexcom.h F: drivers/timer/mchp-pit64b-timer.c +ARM MSC SM2S IMX8MP SOM +M: Martyn Welch +M: Ian Ray +S: Maintained +F: arch/arm/dts/imx8mp-msc-sm2s* +F: board/msc/sm2s_imx8mp/ +F: configs/msc_sm2s_imx8mp_defconfig +F: include/configs/msc_sm2s_imx8mp.h + ARM NEXELL S5P4418 M: Stefan Bosch S: Maintained diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b52077cddc..e89598af30 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -979,6 +979,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk2.dtb \ imx8mp-evk.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ + imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ imx8mp-venice-gw74xx.dtb \ diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi new file mode 100644 index 0000000000..cf591adf5a --- /dev/null +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + model = "MSC SM2S-IMX8MPLUS"; + compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp"; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c4 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&i2c6 { + u-boot,dm-spl; +}; + +&pinctrl_i2c6 { + u-boot,dm-spl; +}; + +&pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts b/arch/arm/dts/imx8mp-msc-sm2s.dts new file mode 100644 index 0000000000..5dbec71747 --- /dev/null +++ b/arch/arm/dts/imx8mp-msc-sm2s.dts @@ -0,0 +1,820 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Avnet Embedded GmbH + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include + +/ { + aliases { + rtc0 = &sys_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_usb0_host_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_flexcan1_xceiver: regulator-flexcan1 { + compatible = "regulator-fixed"; + regulator-name = "flexcan1-xceiver"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_flexcan2_xceiver: regulator-flexcan2 { + compatible = "regulator-fixed"; + regulator-name = "flexcan2-xceiver"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcd0_backlight: backlight-0 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_backlight>; + pwms = <&pwm1 0 100000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + lcd1_backlight: backlight-1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_backlight>; + pwms = <&pwm2 0 100000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <255>; + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + status = "okay"; + + led-sw { + label = "sw-led"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + extcon_usb0: extcon-usb0 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_extcon>; + id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&A53_0 { + cpu-supply = <&vcc_arm>; +}; + +&A53_1 { + cpu-supply = <&vcc_arm>; +}; + +&A53_2 { + cpu-supply = <&vcc_arm>; +}; + +&A53_3 { + cpu-supply = <&vcc_arm>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + id_eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + clock-frequency = <400000>; + status = "disabled"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + clock-frequency = <400000>; + status = "okay"; + + tca6424: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tca6424>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#", + "gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int", + "PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#", + "wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#", + "gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#", + "CHARGER_PRSNT#"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + dsi_lvds_bridge: bridge@2d { + compatible = "ti,sn65dsi83"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bridge>; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + pmic: pmic@30 { + compatible = "ricoh,rn5t567"; + reg = <0x30>; + interrupt-parent = <&tca6424>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + regulators { + DCDC1 { + regulator-name = "VCC_SOC"; + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + }; + + DCDC2 { + regulator-name = "VCC_DRAM"; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vcc_arm: DCDC3 { + regulator-name = "VCC_ARM"; + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + }; + + DCDC4 { + regulator-name = "VCC_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDO1 { + regulator-name = "VCC_LDO1_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO2 { + regulator-name = "VCC_LDO2_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDO3 { + regulator-name = "VCC_ETH_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO4 { + regulator-name = "VCC_DDR4_2V5"; + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + LDO5 { + regulator-name = "VCC_LDO5_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDORTC1 { + regulator-name = "VCC_SNVS_1V8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + LDORTC2 { + regulator-name = "VCC_SNVS_3V3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + sys_rtc: rtc@32 { + compatible = "ricoh,r2221tl"; + reg = <0x32>; + interrupt-parent = <&tca6424>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; + + tmp_sensor: temperature-sensor@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan1_xceiver>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_flexcan2_xceiver>; + status = "disabled"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + qspi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb0_host_vbus>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb1_host_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + extcon = <&extcon_usb0>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = + , + , + , + , + ; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = + , + , + , + , + ; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = + , + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = + , + ; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = + , + ; + }; + + pinctrl_lcd0_backlight: lcd0-backlightgrp { + fsl,pins = + ; + }; + + pinctrl_lcd1_backlight: lcd1-backlightgrp { + fsl,pins = + ; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = + ; + }; + + pinctrl_lvds_bridge: lvds-bridgegrp { + fsl,pins = + ; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = + ; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = + ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = + ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = + ; + }; + + pinctrl_tca6424: tca6424grp { + fsl,pins = + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = + , + ; + }; + + pinctrl_usb0_extcon: usb0-extcongrp { + fsl,pins = + ; + }; + + pinctrl_usb0_vbus: usb0-vbusgrp { + fsl,pins = + ; + }; + + pinctrl_usb1_vbus: usb1-vbusgrp { + fsl,pins = + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp { + fsl,pins = + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + ; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index fbe676d7be..a0715e8091 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -285,6 +285,13 @@ config TARGET_IMX8MP_RSB3720A1_6G select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_MSC_SM2S_IMX8MP + bool "MSC SMARC2 i.MX8MPLUS" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_LIBREM5 bool "Purism Librem5 Phone" select BINMAN @@ -312,6 +319,7 @@ source "board/google/imx8mq_phanbell/Kconfig" source "board/kontron/pitx_imx8m/Kconfig" source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" +source "board/msc/sm2s_imx8mp/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/purism/librem5/Kconfig" diff --git a/board/msc/sm2s_imx8mp/Kconfig b/board/msc/sm2s_imx8mp/Kconfig new file mode 100644 index 0000000000..f71a5b2bcd --- /dev/null +++ b/board/msc/sm2s_imx8mp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MSC_SM2S_IMX8MP + +config SYS_BOARD + default "sm2s_imx8mp" + +config SYS_VENDOR + default "msc" + +config SYS_CONFIG_NAME + default "msc_sm2s_imx8mp" + +config IMX_CONFIG + default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg" + +endif diff --git a/board/msc/sm2s_imx8mp/Makefile b/board/msc/sm2s_imx8mp/Makefile new file mode 100644 index 0000000000..7908a0ceb0 --- /dev/null +++ b/board/msc/sm2s_imx8mp/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH +# +# SPDX-License-Identifier: GPL-2.0 +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o lpddr4_timing.o +else +obj-y += sm2s_imx8mp.o +endif diff --git a/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..8aadedb102 --- /dev/null +++ b/board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/msc/sm2s_imx8mp/lpddr4_timing.c b/board/msc/sm2s_imx8mp/lpddr4_timing.c new file mode 100644 index 0000000000..e0d659af91 --- /dev/null +++ b/board/msc/sm2s_imx8mp/lpddr4_timing.c @@ -0,0 +1,1842 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c new file mode 100644 index 0000000000..3913c4f242 --- /dev/null +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} + +int board_init(void) +{ + setup_fec(); + + setup_eqos(); + + return 0; +} diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c new file mode 100644 index 0000000000..d20c9c52c9 --- /dev/null +++ b/board/msc/sm2s_imx8mp/spl.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \ + | PAD_CTL_PE | PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \ + | PAD_CTL_DSE4) + +static const iomux_v3_cfg_t usdhc2_pads[] = { + MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19) + +static const iomux_v3_cfg_t usdhc3_pads[] = { + MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR, 0, 4 }, + { USDHC3_BASE_ADDR, 0, 8 }, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (sd) USDHC2 + * mmc1 (emmc) USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_RESET_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_RESET_GPIO, 1); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static const iomux_v3_cfg_t wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +static const iomux_v3_cfg_t ser0_pads[] = { + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads)); + + return 0; +} + +static const iomux_v3_cfg_t reset_out_pad[] = { + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19) +}; + +#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27) + +static void pulse_reset_out(void) +{ + imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad)); + + gpio_request(RESET_OUT_GPIO, "reset_out_gpio"); + gpio_direction_output(RESET_OUT_GPIO, 0); + udelay(10); + gpio_direction_output(RESET_OUT_GPIO, 1); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_dev_pads = { + .scl = { + .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC, + .gp = IMX_GPIO_NR(3, 19), + }, + .sda = { + .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC, + .gp = IMX_GPIO_NR(3, 20), + }, +}; + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev); + if (ret) { + printf("Error: Failed to get PMIC\n"); + return ret; + } + + /* set VCC_DRAM (buck2) to 1.1V */ + pmic_reg_write(dev, RN5T567_DC2DAC, 0x28); + + /* set VCC_ARM (buck2) to 0.95V */ + pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + board_early_init_f(); + + pulse_reset_out(); + + timer_init(); + + ret = spl_early_init(); + if (ret) { + printf("Error: failed to initialize SPL!\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + spl_dram_init(); +} diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig new file mode 100644 index 0000000000..6691eb312f --- /dev/null +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_MSC_SM2S_IMX8MP=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x0098FC00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x960000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RN5T567=y +CONFIG_SPL_PMIC_RN5T567=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h new file mode 100644 index 0000000000..59ab7329fa --- /dev/null +++ b/include/configs/msc_sm2s_imx8mp.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#ifndef __MSC_SM2S_IMX8MP_H +#define __MSC_SM2S_IMX8MP_H + +#include +#include +#include + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CONFIG_FEC_MXC_PHYADDR 1 +#define PHY_ANEG_TIMEOUT 20000 +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define PHYS_SDRAM_2 0xc0000000 +#define PHYS_SDRAM_2_SIZE 0x0 + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#endif From b177a2626e3c6b744ef70e7150633af067edba80 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Nov 2022 23:44:01 +0100 Subject: [PATCH 13/43] ARM: imx: Add version variable to DHSOM Enable insertion of version variable into U-Boot environment on DHSOM, to make it possible to check U-Boot version e.g. in U-Boot scripts. Signed-off-by: Marek Vasut --- configs/dh_imx6_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 007438ba83..3763532eef 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -66,6 +66,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" +CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y From cf8ffbe36fe9de6b23bb19b84498e483e43153fe Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 3 Nov 2022 18:03:38 +0200 Subject: [PATCH 14/43] mx6cuboxi: migrate to DM_SERIAL Add the needed DT overrides to enable UART in SPL. Cc: Fabio Estevam Signed-off-by: Baruch Siach Tested-by: Tom Rini Reviewed-by: Fabio Estevam --- ...mx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 16 ++++++++++++++++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 3 +++ configs/mx6cuboxi_defconfig | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index 400b885e43..e1cb9b3e89 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -15,6 +15,22 @@ }; }; +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_microsom_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + &gpio2 { u-boot,dm-pre-reloc; }; diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index debf4f6a3b..8e80ca6e17 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -844,6 +844,9 @@ void board_init_f(ulong dummy) /* setup GP timer */ timer_init(); + /* Enable device tree and early DM support*/ + spl_early_init(); + /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 46061f5972..45bc0a622f 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -47,7 +47,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15" CONFIG_MULTI_DTB_FIT=y -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -69,6 +68,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y From 630abef2f1feff4b51170696deca3fde72c03b78 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:43:06 -0700 Subject: [PATCH 15/43] board: gateworks: venice: remove redundance adjustment of thermal trip points commit 0543a1ed2787 ("imx8m: fixup thermal trips") moved updating the thermal trip points to all IMX8M so we can remove it from our board specific dt config. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index d94f6b8a57..c4d86c26a9 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -179,22 +179,6 @@ int ft_board_setup(void *fdt, struct bd_info *bd) /* set board model dt prop */ fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); - /* update temp thresholds */ - off = fdt_path_offset(fdt, "/thermal-zones/cpu-thermal/trips"); - if (off >= 0) { - int minc, maxc, prop; - - get_cpu_temp_grade(&minc, &maxc); - fdt_for_each_subnode(prop, fdt, off) { - const char *type = fdt_getprop(fdt, prop, "type", NULL); - - if (type && (!strcmp("critical", type))) - fdt_setprop_u32(fdt, prop, "temperature", maxc * 1000); - else if (type && (!strcmp("passive", type))) - fdt_setprop_u32(fdt, prop, "temperature", (maxc - 10) * 1000); - } - } - if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); From 9414097ab77f6d7b711fcc42fe0c48c67f259a29 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:45:20 -0700 Subject: [PATCH 16/43] configs: imx8mn_venice: fix include header protection Fix typo in the include header protection. Signed-off-by: Tim Harvey --- include/configs/imx8mn_venice.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index c43c4da6fb..5fbfdf4602 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -3,8 +3,8 @@ * Copyright 2022 Gateworks Corporation */ -#ifndef __IMX8MM_VENICE_H -#define __IMX8MM_VENICE_H +#ifndef __IMX8MN_VENICE_H +#define __IMX8MN_VENICE_H #include #include From 37fa34f727cc2816893382409d5b339cf01c0ff3 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:46:17 -0700 Subject: [PATCH 17/43] configs: imx8mn_venice.h: remove unused ifdef remove unused ifdef left behind after commit ca3369df71d8 ("configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE") Signed-off-by: Tim Harvey --- include/configs/imx8mm_venice.h | 2 -- include/configs/imx8mn_venice.h | 4 ---- include/configs/imx8mp_venice.h | 4 ---- 3 files changed, 10 deletions(-) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1301560450..44c6bc331d 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -16,8 +16,6 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ - #endif #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 5fbfdf4602..6694820e76 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -13,10 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* For RAW image gives a error info not panic */ -#endif - #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdt_addr_r=0x50200000\0" \ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 455f5a89dc..71962c54bc 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -13,10 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* For RAW image gives a error info not panic */ -#endif - #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdt_addr_r=0x50200000\0" \ From e9e03e7984ae68be9970153948e5987cb8fa394c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:50:23 -0700 Subject: [PATCH 18/43] configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR The IMX8M based Venice boards all have device-tree fec nodes that use proper dt with a phy-handle pointing to a phy with reg assigned to the proper phy address. There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when a proper dt is used - remove it. This was previously done in commit 400eebf10d9b ("configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR") but got clobbered by commit 6889412ad5e7 ("Convert CONFIG_SYS_BARGSIZE to Kconfig") Signed-off-by: Tim Harvey --- include/configs/imx8mm_venice.h | 4 ---- include/configs/imx8mn_venice.h | 4 ---- 2 files changed, 8 deletions(-) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 44c6bc331d..6ecc3477f1 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -82,8 +82,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -/* FEC */ -#define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC - #endif diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 6694820e76..4266eb0760 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -76,8 +76,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -/* FEC */ -#define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC - #endif From 765f6f1895608031d1ef6c017dff3b2f24192827 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:51:45 -0700 Subject: [PATCH 19/43] imx: imx8m{m,n,p}_venice: migrate to CONFIG_EXTRA_ENV_TEXT Move the majority of the environment from the board headers to a separate text file. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.env | 34 ++++++++++++++++++++++ include/configs/imx8mm_venice.h | 47 ++----------------------------- include/configs/imx8mn_venice.h | 47 ++----------------------------- include/configs/imx8mp_venice.h | 47 ++----------------------------- 4 files changed, 40 insertions(+), 135 deletions(-) create mode 100644 board/gateworks/venice/venice.env diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env new file mode 100644 index 0000000000..f81804ca12 --- /dev/null +++ b/board/gateworks/venice/venice.env @@ -0,0 +1,34 @@ +kernel_addr_r=0x48200000 +fdt_addr_r=0x50200000 +scriptaddr=0x50280000 +ramdisk_addr_r=0x50300000 +kernel_comp_addr_r=0x40200000 +script=boot.scr +bootm_size=0x10000000 +dev=2 +preboot=gsc wd-disable +console=ttymxc1,115200 +update_firmware=tftpboot $loadaddr $image && + setexpr blkcnt $filesize + 0x1ff && + setexpr blkcnt $blkcnt / 0x200 && + mmc dev $dev && + mmc write $loadaddr $splblk $blkcnt +loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1; + then echo loaded $fdt_file1; + elif $fsload $fdt_addr_r $dir/$fdt_file2; + then echo loaded $fdt_file2; + elif $fsload $fdt_addr_r $dir/$fdt_file3; + then echo loaded $fdt_file3; + elif $fsload $fdt_addr_r $dir/$fdt_file4; + then echo loaded $fdt_file4; + elif $fsload $fdt_addr_r $dir/$fdt_file5; + then echo loaded $fdt_file5; + fi +boot_net=setenv fsload tftpboot; + run loadfdt && tftpboot $kernel_addr_r $dir/Image && + booti $kernel_addr_r - $fdt_addr_r +update_rootfs=tftpboot $loadaddr $image && + gzwrite mmc $dev $loadaddr $filesize 100000 1000000 +update_all=tftpboot $loadaddr $image && + gzwrite mmc $dev $loadaddr $filesize +erase_env=mmc dev $dev; mmc erase 0x7f08 0x40 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 6ecc3477f1..f754126854 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -18,13 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "fdt_addr_r=0x50200000\0" \ - "scriptaddr=0x50280000\0" \ - "ramdisk_addr_r=0x50300000\0" \ - "kernel_comp_addr_r=0x40200000\0" - /* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -33,45 +26,9 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include - -/* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "script=boot.scr\0" \ - "bootm_size=0x10000000\0" \ - "dev=2\0" \ - "preboot=gsc wd-disable\0" \ - "console=ttymxc1,115200\0" \ - "update_firmware=" \ - "tftpboot $loadaddr $image && " \ - "setexpr blkcnt $filesize + 0x1ff && " \ - "setexpr blkcnt $blkcnt / 0x200 && " \ - "mmc dev $dev && " \ - "mmc write $loadaddr 0x42 $blkcnt\0" \ - "loadfdt=" \ - "if $fsload $fdt_addr_r $dir/$fdt_file1; " \ - "then echo loaded $fdt_file1; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \ - "then echo loaded $fdt_file2; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \ - "then echo loaded $fdt_file3; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \ - "then echo loaded $fdt_file4; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \ - "then echo loaded $fdt_file5; " \ - "fi\0" \ - "boot_net=" \ - "setenv fsload tftpboot; " \ - "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \ - "booti $kernel_addr_r - $fdt_addr_r\0" \ - "update_rootfs=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ - "update_all=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize\0" \ - "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" + "splblk=0x42\0" \ + BOOTENV #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 4266eb0760..022db009e8 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -13,13 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "fdt_addr_r=0x50200000\0" \ - "scriptaddr=0x50280000\0" \ - "ramdisk_addr_r=0x50300000\0" \ - "kernel_comp_addr_r=0x40200000\0" - /* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -27,45 +20,9 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include - -/* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "script=boot.scr\0" \ - "bootm_size=0x10000000\0" \ - "dev=2\0" \ - "preboot=gsc wd-disable\0" \ - "console=ttymxc1,115200\0" \ - "update_firmware=" \ - "tftpboot $loadaddr $image && " \ - "setexpr blkcnt $filesize + 0x1ff && " \ - "setexpr blkcnt $blkcnt / 0x200 && " \ - "mmc dev $dev && " \ - "mmc write $loadaddr 0x40 $blkcnt\0" \ - "loadfdt=" \ - "if $fsload $fdt_addr_r $dir/$fdt_file1; " \ - "then echo loaded $fdt_file1; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \ - "then echo loaded $fdt_file2; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \ - "then echo loaded $fdt_file3; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \ - "then echo loaded $fdt_file4; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \ - "then echo loaded $fdt_file5; " \ - "fi\0" \ - "boot_net=" \ - "setenv fsload tftpboot; " \ - "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \ - "booti $kernel_addr_r - $fdt_addr_r\0" \ - "update_rootfs=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ - "update_all=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize\0" \ - "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" + "splblk=0x40\0" \ + BOOTENV #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 71962c54bc..6b87f0dbc4 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -13,13 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "fdt_addr_r=0x50200000\0" \ - "scriptaddr=0x50280000\0" \ - "ramdisk_addr_r=0x50300000\0" \ - "kernel_comp_addr_r=0x40200000\0" - /* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -27,45 +20,9 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include - -/* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "script=boot.scr\0" \ - "bootm_size=0x10000000\0" \ - "dev=2\0" \ - "preboot=gsc wd-disable\0" \ - "console=ttymxc1,115200\0" \ - "update_firmware=" \ - "tftpboot $loadaddr $image && " \ - "setexpr blkcnt $filesize + 0x1ff && " \ - "setexpr blkcnt $blkcnt / 0x200 && " \ - "mmc dev $dev && " \ - "mmc write $loadaddr 0x40 $blkcnt\0" \ - "loadfdt=" \ - "if $fsload $fdt_addr_r $dir/$fdt_file1; " \ - "then echo loaded $fdt_file1; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \ - "then echo loaded $fdt_file2; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \ - "then echo loaded $fdt_file3; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \ - "then echo loaded $fdt_file4; " \ - "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \ - "then echo loaded $fdt_file5; " \ - "fi\0" \ - "boot_net=" \ - "setenv fsload tftpboot; " \ - "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \ - "booti $kernel_addr_r - $fdt_addr_r\0" \ - "update_rootfs=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \ - "update_all=" \ - "tftpboot $loadaddr $image && " \ - "gzwrite mmc $dev $loadaddr $filesize\0" \ - "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0" + "splblk=0x40\0" \ + BOOTENV #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M From 4a71b9c286c3e1c2a6e57984409cb50db4f25934 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 4 Nov 2022 08:52:19 -0700 Subject: [PATCH 20/43] configs: imx8m{m,n,p}_venice: disable autoload disable network autoload Signed-off-by: Tim Harvey --- configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 5652e1bb66..06775b39db 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -61,6 +61,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index e7b2b5ce9f..6c31a333f2 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -64,6 +64,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 5c0ea11efc..5a4abbd0d8 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -63,6 +63,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y From 05e22e28046b15c30c240c6528154dad26419145 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:34 +0100 Subject: [PATCH 21/43] vf610: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/vf610-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index 740276431a..b7b7322a2d 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -802,7 +802,6 @@ #define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 - #define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 #define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 #define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 @@ -853,4 +852,5 @@ #define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 #define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 #define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 + #endif From 59a4e7fd88fb22bfb125e10fe2e40ec8ffcb5117 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:35 +0100 Subject: [PATCH 22/43] imxrt1020: migrate to build system included -u-boot.dtsi Migrate to using automatic build system included -u-boot.dtsi device tree include files. Signed-off-by: Marcel Ziswiler Reviewed-by: Giulio Benetti Tested-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ++++--- arch/arm/dts/imxrt1020-evk.dts | 1 - 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi index 9e1b074d2e..7cab486f5f 100644 --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -67,9 +67,6 @@ imxrt1020-evk { u-boot,dm-spl; - pinctrl_lpuart1: lpuart1grp { - u-boot,dm-spl; - }; pinctrl_semc: semcgrp { u-boot,dm-spl; @@ -81,6 +78,10 @@ }; }; +&pinctrl_lpuart1 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts index 22ae5ed735..d4d1de4ea8 100644 --- a/arch/arm/dts/imxrt1020-evk.dts +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "imxrt1020.dtsi" -#include "imxrt1020-evk-u-boot.dtsi" #include "imxrt1020-pinfunc.h" / { From 62f96866d34cdf5abc41827158a1acbb5cc6ba6b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:36 +0100 Subject: [PATCH 23/43] imxrt1050: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Note: Nowadays, the intent is for them regular device trees to just be synchronised from them Linux kernel device trees and any and all U-Boot specific changes need to go into the -u-boot.dtsi device tree include files which BTW get included automatically by the U-Boot build system. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 280 ++++++++++++++++++-- arch/arm/dts/imxrt1050-evk.dts | 257 +++--------------- arch/arm/dts/imxrt1050-pinfunc.h | 2 +- arch/arm/dts/imxrt1050.dtsi | 164 +++++------- include/dt-bindings/clock/imxrt1050-clock.h | 9 +- 5 files changed, 367 insertions(+), 345 deletions(-) diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index 617cece448..e217dfd9eb 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -4,9 +4,18 @@ * Author(s): Giulio Benetti */ +#include +#include "imxrt1050-pinfunc.h" + / { + aliases { + display0 = &lcdif; + usbphy0 = &usbphy1; + }; + chosen { u-boot,dm-spl; + tick-timer = &gpt; }; clocks { @@ -15,6 +24,92 @@ soc { u-boot,dm-spl; + + usbphy1: usbphy@400d9000 { + compatible = "fsl,imxrt-usbphy"; + reg = <0x400d9000 0x1000>; + interrupts = ; + }; + + usbmisc: usbmisc@402e0800 { + #index-cells = <1>; + compatible = "fsl,imxrt-usbmisc"; + reg = <0x402e0800 0x200>; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + }; + + usbotg1: usb@402e0000 { + compatible = "fsl,imxrt-usb", "fsl,imx27-usb"; + reg = <0x402e0000 0x200>; + interrupts = ; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + lcdif: lcdif@402b8000 { + compatible = "fsl,imxrt-lcdif"; + reg = <0x402b8000 0x4000>; + interrupts = ; + clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, + <&clks IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; + assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; + status = "disabled"; + }; + + semc: semc@402f0000 { + compatible = "fsl,imxrt-semc"; + reg = <0x402f0000 0x4000>; + clocks = <&clks IMXRT1050_CLK_SEMC>; + pinctrl-0 = <&pinctrl_semc>; + pinctrl-names = "default"; + status = "okay"; + }; + }; +}; + +&semc { + u-boot,dm-spl; + /* + * Memory configuration from sdram datasheet IS42S16160J-6BLI + */ + fsl,sdram-mux = /bits/ 8 ; + fsl,sdram-control = /bits/ 8 ; + fsl,sdram-timing = /bits/ 8 <0x2 + 0x2 + 0x9 + 0x1 + 0x5 + 0x6 + + 0x20 + 0x09 + 0x01 + 0x00 + + 0x04 + 0x0A + 0x21 + 0x50>; + + bank1: bank@0 { + fsl,base-address = <0x80000000>; + fsl,memory-size = ; + u-boot,dm-spl; }; }; @@ -31,60 +126,205 @@ }; &gpio1 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; u-boot,dm-spl; }; &gpio2 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; u-boot,dm-spl; }; &gpio3 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; u-boot,dm-spl; }; &gpio4 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; u-boot,dm-spl; }; &gpio5 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; u-boot,dm-spl; }; -&gpt1 { +&gpt { + clocks = <&osc>; + compatible = "fsl,imxrt-gpt"; + status = "okay"; u-boot,dm-spl; }; &lpuart1 { /* console */ + compatible = "fsl,imxrt-lpuart"; + clock-names = "per"; u-boot,dm-spl; }; -&semc { - u-boot,dm-spl; - - bank1: bank@0 { - u-boot,dm-spl; - }; -}; - &iomuxc { u-boot,dm-spl; + compatible = "fsl,imxrt-iomuxc"; + pinctrl-0 = <&pinctrl_lpuart1>; - imxrt1050-evk { + pinctrl_semc: semcgrp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 + 0xf1 /* SEMC_D0 */ + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 + 0xf1 /* SEMC_D1 */ + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 + 0xf1 /* SEMC_D2 */ + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 + 0xf1 /* SEMC_D3 */ + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 + 0xf1 /* SEMC_D4 */ + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 + 0xf1 /* SEMC_D5 */ + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 + 0xf1 /* SEMC_D6 */ + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 + 0xf1 /* SEMC_D7 */ + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 + 0xf1 /* SEMC_DM0 */ + MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 + 0xf1 /* SEMC_A0 */ + MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 + 0xf1 /* SEMC_A1 */ + MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 + 0xf1 /* SEMC_A2 */ + MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 + 0xf1 /* SEMC_A3 */ + MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 + 0xf1 /* SEMC_A4 */ + MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 + 0xf1 /* SEMC_A5 */ + MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 + 0xf1 /* SEMC_A6 */ + MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 + 0xf1 /* SEMC_A7 */ + MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 + 0xf1 /* SEMC_A8 */ + MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 + 0xf1 /* SEMC_A9 */ + MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 + 0xf1 /* SEMC_A11 */ + MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 + 0xf1 /* SEMC_A12 */ + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 + 0xf1 /* SEMC_BA0 */ + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 + 0xf1 /* SEMC_BA1 */ + MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 + 0xf1 /* SEMC_A10 */ + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS + 0xf1 /* SEMC_CAS */ + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS + 0xf1 /* SEMC_RAS */ + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK + 0xf1 /* SEMC_CLK */ + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE + 0xf1 /* SEMC_CKE */ + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE + 0xf1 /* SEMC_WE */ + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 + 0xf1 /* SEMC_CS0 */ + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 + 0xf1 /* SEMC_D8 */ + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 + 0xf1 /* SEMC_D9 */ + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 + 0xf1 /* SEMC_D10 */ + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 + 0xf1 /* SEMC_D11 */ + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 + 0xf1 /* SEMC_D12 */ + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 + 0xf1 /* SEMC_D13 */ + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 + 0xf1 /* SEMC_D14 */ + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 + 0xf1 /* SEMC_D15 */ + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 + 0xf1 /* SEMC_DM1 */ + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS + (IMX_PAD_SION | 0xf1) /* SEMC_DQS */ + >; u-boot,dm-spl; - pinctrl_lpuart1: lpuart1grp { - u-boot,dm-spl; - }; + }; - pinctrl_semc: semcgrp { - u-boot,dm-spl; - }; + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069 + MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069 + >; + }; - pinctrl_usdhc0: usdhc0grp { - u-boot,dm-spl; + pinctrl_lpuart1: lpuart1grp { + u-boot,dm-spl; + }; + + pinctrl_usdhc0: usdhc0grp { + u-boot,dm-spl; + }; + }; + +&usdhc1 { + compatible = "fsl,imxrt-usdhc"; + u-boot,dm-spl; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <16>; + + display-timings { + timing0: timing0 { + clock-frequency = <9300000>; + hactive = <480>; + vactive = <272>; + hback-porch = <4>; + hfront-porch = <8>; + vback-porch = <4>; + vfront-porch = <8>; + hsync-len = <41>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; }; }; }; -&usdhc1 { - u-boot,dm-spl; +&usbotg1 { + dr_mode = "host"; + status = "okay"; }; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index fb2da3adfc..6a9c10decf 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 * Author(s): Giulio Benetti @@ -6,7 +6,6 @@ /dts-v1/; #include "imxrt1050.dtsi" -#include "imxrt1050-evk-u-boot.dtsi" #include "imxrt1050-pinfunc.h" / { @@ -14,210 +13,52 @@ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - tick-timer = &gpt1; + stdout-path = &lpuart1; }; - memory { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x2000000>; }; }; -&lpuart1 { /* console */ +&lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart1>; status = "okay"; }; -&semc { - /* - * Memory configuration from sdram datasheet IS42S16160J-6BLI - */ - fsl,sdram-mux = /bits/ 8 ; - fsl,sdram-control = /bits/ 8 ; - fsl,sdram-timing = /bits/ 8 <0x2 - 0x2 - 0x9 - 0x1 - 0x5 - 0x6 - - 0x20 - 0x09 - 0x01 - 0x00 - - 0x04 - 0x0A - 0x21 - 0x50>; - - bank1: bank@0 { - fsl,base-address = <0x80000000>; - fsl,memory-size = ; - }; -}; - &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - - imxrt1050-evk { - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD - 0xf1 - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD - 0xf1 - >; - }; - - pinctrl_semc: semcgrp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 - 0xf1 /* SEMC_D0 */ - MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 - 0xf1 /* SEMC_D1 */ - MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 - 0xf1 /* SEMC_D2 */ - MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 - 0xf1 /* SEMC_D3 */ - MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 - 0xf1 /* SEMC_D4 */ - MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 - 0xf1 /* SEMC_D5 */ - MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 - 0xf1 /* SEMC_D6 */ - MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 - 0xf1 /* SEMC_D7 */ - MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 - 0xf1 /* SEMC_DM0 */ - MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 - 0xf1 /* SEMC_A0 */ - MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 - 0xf1 /* SEMC_A1 */ - MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 - 0xf1 /* SEMC_A2 */ - MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 - 0xf1 /* SEMC_A3 */ - MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 - 0xf1 /* SEMC_A4 */ - MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 - 0xf1 /* SEMC_A5 */ - MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 - 0xf1 /* SEMC_A6 */ - MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 - 0xf1 /* SEMC_A7 */ - MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 - 0xf1 /* SEMC_A8 */ - MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 - 0xf1 /* SEMC_A9 */ - MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 - 0xf1 /* SEMC_A11 */ - MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 - 0xf1 /* SEMC_A12 */ - MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 - 0xf1 /* SEMC_BA0 */ - MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 - 0xf1 /* SEMC_BA1 */ - MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 - 0xf1 /* SEMC_A10 */ - MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS - 0xf1 /* SEMC_CAS */ - MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS - 0xf1 /* SEMC_RAS */ - MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK - 0xf1 /* SEMC_CLK */ - MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE - 0xf1 /* SEMC_CKE */ - MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE - 0xf1 /* SEMC_WE */ - MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 - 0xf1 /* SEMC_CS0 */ - MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 - 0xf1 /* SEMC_D8 */ - MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 - 0xf1 /* SEMC_D9 */ - MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 - 0xf1 /* SEMC_D10 */ - MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 - 0xf1 /* SEMC_D11 */ - MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 - 0xf1 /* SEMC_D12 */ - MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 - 0xf1 /* SEMC_D13 */ - MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 - 0xf1 /* SEMC_D14 */ - MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 - 0xf1 /* SEMC_D15 */ - MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 - 0xf1 /* SEMC_DM1 */ - MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS - (IMX_PAD_SION | 0xf1) /* SEMC_DQS */ - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B - 0x1B000 - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT - 0xB069 - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD - 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK - 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 - 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 - 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 - 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 - 0x17061 - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1 - MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069 - MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069 - >; - }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; }; -}; -&gpt1 { - status = "okay"; + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; }; &usdhc1 { @@ -226,42 +67,6 @@ pinctrl-1 = <&pinctrl_usdhc0>; pinctrl-2 = <&pinctrl_usdhc0>; pinctrl-3 = <&pinctrl_usdhc0>; - status = "okay"; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - timing0: timing0 { - clock-frequency = <9300000>; - hactive = <480>; - vactive = <272>; - hback-porch = <4>; - hfront-porch = <8>; - vback-porch = <4>; - vfront-porch = <8>; - hsync-len = <41>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <0>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&usbotg1 { - dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h index a29031ab3d..22c14a3262 100644 --- a/arch/arm/dts/imxrt1050-pinfunc.h +++ b/arch/arm/dts/imxrt1050-pinfunc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2019 * Author(s): Giulio Benetti diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 09f4712af6..03e6a858a7 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 * Author(s): Giulio Benetti @@ -8,53 +8,37 @@ #include #include #include -#include / { #address-cells = <1>; #size-cells = <1>; - aliases { - display0 = &lcdif; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - mmc0 = &usdhc1; - serial0 = &lpuart1; - usbphy0 = &usbphy1; - }; - clocks { osc: osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; }; soc { - semc: semc@402f0000 { - compatible = "fsl,imxrt-semc"; - reg = <0x402f0000 0x4000>; - clocks = <&clks IMXRT1050_CLK_SEMC>; - pinctrl-0 = <&pinctrl_semc>; - pinctrl-names = "default"; - status = "okay"; - }; - lpuart1: serial@40184000 { - compatible = "fsl,imxrt-lpuart"; + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x40184000 0x4000>; - interrupts = ; + interrupts = <20>; clocks = <&clks IMXRT1050_CLK_LPUART1>; - clock-names = "per"; + clock-names = "ipg"; status = "disabled"; }; - iomuxc: iomuxc@401f8000 { - compatible = "fsl,imxrt-iomuxc"; + iomuxc: pinctrl@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; reg = <0x401f8000 0x4000>; fsl,mux_mask = <0x7>; }; @@ -64,31 +48,61 @@ reg = <0x400d8000 0x4000>; }; - clks: ccm@400fc000 { + clks: clock-controller@400fc000 { compatible = "fsl,imxrt1050-ccm"; reg = <0x400fc000 0x4000>; - interrupts = , - ; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; }; - usdhc1: usdhc@402c0000 { - compatible = "fsl,imxrt-usdhc"; - reg = <0x402c0000 0x10000>; - interrupts = ; - clocks = <&clks IMXRT1050_CLK_USDHC1>; - clock-names = "per"; + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; gpio1: gpio@401b8000 { - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; - interrupts = , - ; + interrupts = <80>, <81>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -96,10 +110,9 @@ }; gpio2: gpio@401bc000 { - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; - interrupts = , - ; + interrupts = <82>, <83>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -107,10 +120,9 @@ }; gpio3: gpio@401c0000 { - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; - interrupts = , - ; + interrupts = <84>, <85>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -118,10 +130,9 @@ }; gpio4: gpio@401c4000 { - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x401c4000 0x4000>; - interrupts = , - ; + interrupts = <86>, <87>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -129,60 +140,21 @@ }; gpio5: gpio@400c0000 { - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; reg = <0x400c0000 0x4000>; - interrupts = , - ; + interrupts = <88>, <89>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - lcdif: lcdif@402b8000 { - compatible = "fsl,imxrt-lcdif"; - reg = <0x402b8000 0x4000>; - interrupts = ; - clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, - <&clks IMXRT1050_CLK_LCDIF_APB>; - clock-names = "pix", "axi"; - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; - status = "disabled"; - }; - - gpt1: gpt1@401ec000 { - compatible = "fsl,imxrt-gpt"; + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; reg = <0x401ec000 0x4000>; interrupts = <100>; - clocks = <&osc>; - status = "disabled"; - }; - - usbphy1: usbphy@400d9000 { - compatible = "fsl,imxrt-usbphy"; - reg = <0x400d9000 0x1000>; - interrupts = ; - }; - - usbmisc: usbmisc@402e0800 { - #index-cells = <1>; - compatible = "fsl,imxrt-usbmisc"; - reg = <0x402e0800 0x200>; - clocks = <&clks IMXRT1050_CLK_USBOH3>; - }; - - usbotg1: usb@402e0000 { - compatible = "fsl,imxrt-usb", "fsl,imx27-usb"; - reg = <0x402e0000 0x200>; - interrupts = ; - clocks = <&clks IMXRT1050_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; + clocks = <&osc3M>; + clock-names = "per"; }; }; }; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h index f74dbbcf93..93bef0832d 100644 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright(C) 2019 * Author(s): Giulio Benetti @@ -62,6 +62,11 @@ #define IMXRT1050_CLK_PLL7_USB_HOST 53 #define IMXRT1050_CLK_LCDIF_PIX 54 #define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_END 56 +#define IMXRT1050_CLK_IPG_PDOF 56 +#define IMXRT1050_CLK_PER_CLK_SEL 57 +#define IMXRT1050_CLK_PER_PDOF 58 +#define IMXRT1050_CLK_DMA 59 +#define IMXRT1050_CLK_DMA_MUX 60 +#define IMXRT1050_CLK_END 61 #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ From ed7bda57104e236ab7edc5f0c3955955b3882387 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:37 +0100 Subject: [PATCH 24/43] imx8ulp: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +- arch/arm/dts/imx8ulp-evk.dts | 242 +++---- arch/arm/dts/imx8ulp-pinfunc.h | 4 +- arch/arm/dts/imx8ulp.dtsi | 594 +++++------------- include/dt-bindings/clock/imx8ulp-clock.h | 53 +- include/dt-bindings/power/imx8ulp-power.h | 26 + include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 7 files changed, 370 insertions(+), 623 deletions(-) create mode 100644 include/dt-bindings/power/imx8ulp-power.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 7c1dab2acf..ad264f271e 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -3,7 +3,16 @@ * Copyright 2021 NXP */ -&{/soc@0} { +/ { + mu@27020000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0 0x27020000 0 0x10000>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&soc { u-boot,dm-spl; }; @@ -23,10 +32,6 @@ u-boot,dm-spl; }; -&s400_mu { - u-boot,dm-spl; -}; - &lpuart5 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts index da09ff48ff..f1c6d933a1 100644 --- a/arch/arm/dts/imx8ulp-evk.dts +++ b/arch/arm/dts/imx8ulp-evk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2021 NXP */ @@ -8,17 +8,31 @@ #include "imx8ulp.dtsi" / { - model = "FSL i.MX8ULP EVK"; + model = "NXP i.MX8ULP EVK"; compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; chosen { stdout-path = &lpuart5; - bootargs = "console=ttyLP1,115200 earlycon"; }; - usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + clock_ext_rmii: clock-ext-rmii { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "ext_rmii_clk"; + #clock-cells = <0>; + }; + + clock_ext_ts: clock-ext-ts { + compatible = "fixed-clock"; + /* External ts clock is 50MHZ from PHY on EVK board. */ + clock-frequency = <50000000>; + clock-output-names = "ext_ts_clk"; + #clock-cells = <0>; }; }; @@ -30,24 +44,67 @@ status = "okay"; }; +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet>; + pinctrl-1 = <&pinctrl_enet>; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&pcc4 IMX8ULP_CLK_ENET>, + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, + <&clock_ext_rmii>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clock_ext_ts>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; + }; +}; + &iomuxc1 { - pinctrl_lpuart5: lpuart5grp { + pinctrl_enet: enetgrp { fsl,pins = < - MX8ULP_PAD_PTF14__LPUART5_TX 0x03 - MX8ULP_PAD_PTF15__LPUART5_RX 0x03 + MX8ULP_PAD_PTE15__ENET0_MDC 0x43 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 + MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >; }; - pinctrl_lpi2c7: lpi2c7grp { + pinctrl_lpuart5: lpuart5grp { fsl,pins = < - MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27 - MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27 + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < - MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43 MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 MX8ULP_PAD_PTD10__SDHC0_D0 0x43 @@ -61,163 +118,4 @@ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 >; }; - - pinctrl_usdhc2_pte: usdhc2ptegrp { - fsl,pins = < - MX8ULP_PAD_PTE1__SDHC2_D0 0x43 - MX8ULP_PAD_PTE0__SDHC2_D1 0x43 - MX8ULP_PAD_PTE5__SDHC2_D2 0x43 - MX8ULP_PAD_PTE4__SDHC2_D3 0x43 - MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042 - MX8ULP_PAD_PTE3__SDHC2_CMD 0x43 - MX8ULP_PAD_PTE7__PTE7 0x10003 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 - MX8ULP_PAD_PTE15__ENET0_MDC 0x43 - MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 - MX8ULP_PAD_PTE17__ENET0_RXER 0x43 - MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 - MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 - MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 - MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 - MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 - MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043 - MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043 - >; - }; - - pinctrl_usbotg0_id: otg0idgrp { - fsl,pins = < - MX8ULP_PAD_PTF2__USB0_ID 0x10003 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - MX8ULP_PAD_PTD23__USB1_ID 0x10003 - >; - }; -}; - -&usdhc0 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc0>; - pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2_pte>; - pinctrl-1 = <&pinctrl_usdhc2_pte>; - pinctrl-2 = <&pinctrl_usdhc2_pte>; - pinctrl-3 = <&pinctrl_usdhc2_pte>; - mmc-pwrseq = <&usdhc2_pwrseq>; - max-frequency = <100000000>; - bus-width = <4>; - keep-power-in-suspend; - non-removable; - wakeup-source; - status = "okay"; - - wifi_wake_host { - compatible = "nxp,wifi-wake-host"; - interrupt-parent = <&gpioe>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&lpi2c7 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c7>; - status = "okay"; - - pcal6408: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&flexspi0 { - status = "okay"; - - flash0: atxp032@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <66000000>; - }; -}; - -&flexspi2 { - status = "okay"; - - flash1: mt35xu512aba@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-nor,ddr-quad-read-dummy = <8>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-handle = <ðphy>; - status = "okay"; - - phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <1>; - }; - }; -}; - -&usbotg0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg0_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy0 { - fsl,tx-d-cal = <88>; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <88>; }; diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h index c21c3b644e..b204ac79b4 100644 --- a/arch/arm/dts/imx8ulp-pinfunc.h +++ b/arch/arm/dts/imx8ulp-pinfunc.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */ #ifndef __DTS_IMX8ULP_PINFUNC_H diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi index d3b16bd2fe..06ce5f19aa 100644 --- a/arch/arm/dts/imx8ulp.dtsi +++ b/arch/arm/dts/imx8ulp.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2021 NXP */ @@ -6,6 +6,8 @@ #include #include #include +#include + #include "imx8ulp-pinfunc.h" / { @@ -14,49 +16,29 @@ #size-cells = <2>; aliases { + ethernet0 = &fec; gpio0 = &gpiod; gpio1 = &gpioe; gpio2 = &gpiof; - serial0 = &lpuart5; mmc0 = &usdhc0; mmc1 = &usdhc1; mmc2 = &usdhc2; - spi0 = &flexspi0; - spi2 = &flexspi2; - ethernet0 = &fec; - i2c7 = &lpi2c7; - usbphy0 = &usbphy0; - usb0 = &usbotg0; - usbphy1 = &usbphy1; - usb1 = &usbotg1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; }; - cpus: cpus { + cpus { #address-cells = <2>; #size-cells = <0>; - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - }; - - /* We have 1 clusters with 4 Cortex-A35 cores */ A35_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; }; A35_1: cpu@1 { @@ -65,7 +47,6 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; }; A35_L2: l2-cache0 { @@ -73,37 +54,6 @@ }; }; - a35_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <800000>; - clock-latency-ns = <150000>; - }; - - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-microvolt = <900000>; - clock-latency-ns = <150000>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - s400_mu: mu@27020000 { - u-boot,dm-spl; - compatible = "fsl,imx8ulp-mu"; - reg = <0 0x27020000 0 0x10000>; - status = "okay"; - }; - gic: interrupt-controller@2d400000 { compatible = "arm,gic-v3"; reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ @@ -113,6 +63,14 @@ interrupts = ; }; + pmu { + compatible = "arm,cortex-a35-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-affinity = <&A35_0>, <&A35_1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -154,7 +112,7 @@ #clock-cells = <0>; }; - sram@0x2201f000 { + sram@2201f000 { compatible = "mmio-sram"; reg = <0x0 0x2201f000 0x0 0x1000>; @@ -162,10 +120,9 @@ #size-cells = <1>; ranges = <0 0x0 0x2201f000 0x1000>; - /* TODO: split or unify */ - scmi_pd: scmi_pd@0 { + scmi_buf: scmi-sram-section@0 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; + reg = <0x0 0x400>; }; }; @@ -175,41 +132,31 @@ arm,smc-id = <0xc20000fe>; #address-cells = <1>; #size-cells = <0>; - shmem = <&scmi_pd>; + shmem = <&scmi_buf>; scmi_devpd: protocol@11 { reg = <0x11>; #power-domain-cells = <1>; }; - scmi_perf: protocol@13 { - reg = <0x13>; + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; }; }; }; - soc@0 { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>; + ranges = <0x0 0x0 0x0 0x40000000>; - per_bridge0: bus@28000000 { - compatible = "simple-bus"; - reg = <0x28000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flexspi0: flexspi@28039000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8ulp-fspi"; - reg = <0x28039000 0x10000>, - <0x04000000 0x7ffffff>; - reg-names = "fspi_base", "fspi_mmap"; - status = "disabled"; - }; + s4muap: mailbox@27020000 { + compatible = "fsl,imx8ulp-mu-s4"; + reg = <0x27020000 0x10000>; + interrupts = ; + #mbox-cells = <2>; }; per_bridge3: bus@29000000 { @@ -219,110 +166,21 @@ #size-cells = <1>; ranges; - edma1: dma-controller@29010000 { - compatible = "fsl,imx8ulp-edma"; - reg = <0x29010000 0x10000>, - <0x29020000 0x10000>, <0x29030000 0x10000>, - <0x29040000 0x10000>, <0x29050000 0x10000>, - <0x29060000 0x10000>, <0x29070000 0x10000>, - <0x29080000 0x10000>, <0x29090000 0x10000>, - <0x290a0000 0x10000>, <0x290b0000 0x10000>, - <0x290c0000 0x10000>, <0x290d0000 0x10000>, - <0x290e0000 0x10000>, <0x290f0000 0x10000>, - <0x29100000 0x10000>, <0x29110000 0x10000>, - <0x29120000 0x10000>, <0x29130000 0x10000>, - <0x29140000 0x10000>, <0x29150000 0x10000>, - <0x29160000 0x10000>, <0x29170000 0x10000>, - <0x29180000 0x10000>, <0x29190000 0x10000>, - <0x291a0000 0x10000>, <0x291b0000 0x10000>, - <0x291c0000 0x10000>, <0x291d0000 0x10000>, - <0x291e0000 0x10000>, <0x291f0000 0x10000>, - <0x29200000 0x10000>, <0x29210000 0x10000>; - #dma-cells = <3>; - dma-channels = <32>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", - "edma1-chan2-tx", "edma1-chan3-tx", - "edma1-chan4-tx", "edma1-chan5-tx", - "edma1-chan6-tx", "edma1-chan7-tx", - "edma1-chan8-tx", "edma1-chan9-tx", - "edma1-chan10-tx", "edma1-chan11-tx", - "edma1-chan12-tx", "edma1-chan13-tx", - "edma1-chan14-tx", "edma1-chan15-tx", - "edma1-chan16-tx", "edma1-chan17-tx", - "edma1-chan18-tx", "edma1-chan19-tx", - "edma1-chan20-tx", "edma1-chan21-tx", - "edma1-chan22-tx", "edma1-chan23-tx", - "edma1-chan24-tx", "edma1-chan25-tx", - "edma1-chan26-tx", "edma1-chan27-tx", - "edma1-chan28-tx", "edma1-chan29-tx", - "edma1-chan30-tx", "edma1-chan31-tx"; - clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, - <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, - <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, - <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, - <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, - <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, - <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, - <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, - <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, - <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, - <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, - <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, - <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, - <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, - <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, - <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, - <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; - clock-names = "edma-mp-clk", - "edma1-chan0-clk", "edma1-chan1-clk", - "edma1-chan2-clk", "edma1-chan3-clk", - "edma1-chan4-clk", "edma1-chan5-clk", - "edma1-chan6-clk", "edma1-chan7-clk", - "edma1-chan8-clk", "edma1-chan9-clk", - "edma1-chan10-clk", "edma1-chan11-clk", - "edma1-chan12-clk", "edma1-chan13-clk", - "edma1-chan14-clk", "edma1-chan15-clk", - "edma1-chan16-clk", "edma1-chan17-clk", - "edma1-chan18-clk", "edma1-chan19-clk", - "edma1-chan20-clk", "edma1-chan21-clk", - "edma1-chan22-clk", "edma1-chan23-clk", - "edma1-chan24-clk", "edma1-chan25-clk", - "edma1-chan26-clk", "edma1-chan27-clk", - "edma1-chan28-clk", "edma1-chan29-clk", - "edma1-chan30-clk", "edma1-chan31-clk"; - status = "okay"; + mu: mailbox@29220000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0x29220000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu3: mailbox@29230000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0x29230000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; + #mbox-cells = <2>; + status = "disabled"; }; wdog3: watchdog@292a0000 { @@ -331,15 +189,13 @@ interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; - assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; timeout-sec = <40>; }; cgc1: clock-controller@292c0000 { compatible = "fsl,imx8ulp-cgc1"; reg = <0x292c0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; - clock-names = "rosc", "sosc", "frosc", "lposc"; #clock-cells = <1>; }; @@ -347,6 +203,7 @@ compatible = "fsl,imx8ulp-pcc3"; reg = <0x292d0000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; }; tpm5: tpm@29340000 { @@ -356,6 +213,33 @@ clocks = <&pcc3 IMX8ULP_CLK_TPM5>, <&pcc3 IMX8ULP_CLK_TPM5>; clock-names = "ipg", "per"; + status = "disabled"; + }; + + lpi2c4: i2c@29370000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29370000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, + <&pcc3 IMX8ULP_CLK_LPI2C4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: i2c@29380000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29380000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, + <&pcc3 IMX8ULP_CLK_LPI2C5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; }; lpuart4: serial@29390000 { @@ -370,10 +254,41 @@ lpuart5: serial@293a0000 { compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x293a0000 0x1000>; + interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; status = "disabled"; }; + + lpspi4: spi@293b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293b0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, + <&pcc3 IMX8ULP_CLK_LPSPI4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi5: spi@293c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293c0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, + <&pcc3 IMX8ULP_CLK_LPSPI5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; }; per_bridge4: bus@29800000 { @@ -387,77 +302,84 @@ compatible = "fsl,imx8ulp-pcc4"; reg = <0x29800000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; }; - lpi2c6: lpi2c6@29840000 { + lpi2c6: i2c@29840000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29840000 0x10000>; interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, <&pcc4 IMX8ULP_CLK_LPI2C6>; clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; status = "disabled"; }; - lpi2c7: lpi2c7@29850000 { + lpi2c7: i2c@29850000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29850000 0x10000>; interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, <&pcc4 IMX8ULP_CLK_LPI2C7>; clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; status = "disabled"; }; - flexspi2: flexspi@29810000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8ulp-fspi"; - reg = <0x29810000 0x10000>, - <0x60000000 0xfffffff>; - reg-names = "fspi_base", "fspi_mmap"; + lpuart6: serial@29860000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29860000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + clock-names = "ipg"; status = "disabled"; }; - flexspi2_nand: flexspi2_nand@29810000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8-fspi-nand"; - reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; - reg-names = "FlexSPI", "FlexSPI-memory"; + lpuart7: serial@29870000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29870000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + clock-names = "ipg"; status = "disabled"; }; iomuxc1: pinctrl@298c0000 { compatible = "fsl,imx8ulp-iomuxc1"; reg = <0x298c0000 0x10000>; - fsl,mux_mask = <0xf00>; }; usdhc0: mmc@298d0000 { - compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; reg = <0x298d0000 0x10000>; interrupts = ; - clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, - <&cgc1 IMX8ULP_CLK_DUMMY>, + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; usdhc1: mmc@298e0000 { - compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; reg = <0x298e0000 0x10000>; interrupts = ; - clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, - <&cgc1 IMX8ULP_CLK_DUMMY>, + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -470,117 +392,50 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>; - assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; - assigned-clock-rates = <396000000>, <396000000>; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; - usbotg0: usb@29900000 { - compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", - "fsl,imx27-usb"; - reg = <0x29900000 0x200>; - interrupts = ; - clocks = <&pcc4 IMX8ULP_CLK_USB0>; - fsl,usbphy = <&usbphy0>; - fsl,usbmisc = <&usbmisc0 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc0: usbmisc@29900200 { - #index-cells = <1>; - compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x29900200 0x200>; - }; - - usbphy0: usbphy@29910000 { - compatible = "fsl,imx8ulp-usbphy", - "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; - reg = <0x29910000 0x1000>; - interrupts = ; - clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; - }; - - usbotg1: usb@29920000 { - compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", - "fsl,imx27-usb"; - reg = <0x29920000 0x200>; - interrupts = ; - clocks = <&pcc4 IMX8ULP_CLK_USB1>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc1: usbmisc@29920200 { - #index-cells = <1>; - compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x29920200 0x200>; - }; - - usbphy1: usbphy@29930000 { - compatible = "fsl,imx8ulp-usbphy", - "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; - reg = <0x29930000 0x1000>; - interrupts = ; - clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; - }; - fec: ethernet@29950000 { - compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x29950000 0x10000>; interrupts = ; - clocks = <&pcc4 IMX8ULP_CLK_ENET>, - <&pcc4 IMX8ULP_CLK_ENET>, - <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>, - <&pcc4 IMX8ULP_CLK_ENET>, - <&pcc4 IMX8ULP_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; + interrupt-names = "int0"; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; status = "disabled"; }; - }; - gpioe: gpio@2d000000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2d000080 0x1000 0x2d000040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, - <&pcc4 IMX8ULP_CLK_PCTLE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 32 24>; + gpioe: gpio@2d000080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; }; - gpiof: gpio@2d010000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2d010080 0x1000 0x2d010040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, - <&pcc4 IMX8ULP_CLK_PCTLF>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 64 24>; + gpiof: gpio@2d010080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; }; per_bridge5: bus@2d800000 { @@ -590,117 +445,9 @@ #size-cells = <1>; ranges; - edma2: dma-controller@2d800000 { - compatible = "fsl,imx8ulp-edma"; - reg = <0x2d800000 0x10000>, - <0x2d810000 0x10000>, <0x2d820000 0x10000>, - <0x2d830000 0x10000>, <0x2d840000 0x10000>, - <0x2d850000 0x10000>, <0x2d860000 0x10000>, - <0x2d870000 0x10000>, <0x2d880000 0x10000>, - <0x2d890000 0x10000>, <0x2d8a0000 0x10000>, - <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>, - <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>, - <0x2d8f0000 0x10000>, <0x2d900000 0x10000>, - <0x2d910000 0x10000>, <0x2d920000 0x10000>, - <0x2d930000 0x10000>, <0x2d940000 0x10000>, - <0x2d950000 0x10000>, <0x2d960000 0x10000>, - <0x2d970000 0x10000>, <0x2d980000 0x10000>, - <0x2d990000 0x10000>, <0x2d9a0000 0x10000>, - <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>, - <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>, - <0x2d9f0000 0x10000>, <0x2da00000 0x10000>; - #dma-cells = <3>; - dma-channels = <32>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", - "edma2-chan2-tx", "edma2-chan3-tx", - "edma2-chan4-tx", "edma2-chan5-tx", - "edma2-chan6-tx", "edma2-chan7-tx", - "edma2-chan8-tx", "edma2-chan9-tx", - "edma2-chan10-tx", "edma2-chan11-tx", - "edma2-chan12-tx", "edma2-chan13-tx", - "edma2-chan14-tx", "edma2-chan15-tx", - "edma2-chan16-tx", "edma2-chan17-tx", - "edma2-chan18-tx", "edma2-chan19-tx", - "edma2-chan20-tx", "edma2-chan21-tx", - "edma2-chan22-tx", "edma2-chan23-tx", - "edma2-chan24-tx", "edma2-chan25-tx", - "edma2-chan26-tx", "edma2-chan27-tx", - "edma2-chan28-tx", "edma2-chan29-tx", - "edma2-chan30-tx", "edma2-chan31-tx"; - clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, - <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, - <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, - <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, - <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, - <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, - <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, - <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, - <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, - <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, - <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, - <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, - <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, - <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, - <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, - <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, - <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; - clock-names = "edma-mp-clk", - "edma2-chan0-clk", "edma2-chan1-clk", - "edma2-chan2-clk", "edma2-chan3-clk", - "edma2-chan4-clk", "edma2-chan5-clk", - "edma2-chan6-clk", "edma2-chan7-clk", - "edma2-chan8-clk", "edma2-chan9-clk", - "edma2-chan10-clk", "edma2-chan11-clk", - "edma2-chan12-clk", "edma2-chan13-clk", - "edma2-chan14-clk", "edma2-chan15-clk", - "edma2-chan16-clk", "edma2-chan17-clk", - "edma2-chan18-clk", "edma2-chan19-clk", - "edma2-chan20-clk", "edma2-chan21-clk", - "edma2-chan22-clk", "edma2-chan23-clk", - "edma2-chan24-clk", "edma2-chan25-clk", - "edma2-chan26-clk", "edma2-chan27-clk", - "edma2-chan28-clk", "edma2-chan29-clk", - "edma2-chan30-clk", "edma2-chan31-clk"; - status = "okay"; - }; - cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; - clocks = <&sosc>, <&frosc>; - clock-names = "sosc", "frosc"; #clock-cells = <1>; }; @@ -708,12 +455,13 @@ compatible = "fsl,imx8ulp-pcc5"; reg = <0x2da70000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; }; }; - gpiod: gpio@2e200000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2e200080 0x1000 0x2e200040 0x40>; + gpiod: gpio@2e200080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = ; diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h index 49166a1830..953ecfe8eb 100644 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -1,16 +1,14 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define __DT_BINDINGS_CLOCK_IMX8ULP_H #define IMX8ULP_CLK_DUMMY 0 -#define IMX8ULP_CLK_ROSC 1 -#define IMX8ULP_CLK_FROSC 2 -#define IMX8ULP_CLK_LPOSC 3 -#define IMX8ULP_CLK_SOSC 4 + +/* CGC1 */ #define IMX8ULP_CLK_SPLL2 5 #define IMX8ULP_CLK_SPLL3 6 #define IMX8ULP_CLK_A35_SEL 7 @@ -57,14 +55,15 @@ #define IMX8ULP_CLK_FROSC_DIV1_GATE 48 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49 #define IMX8ULP_CLK_FROSC_DIV3_GATE 50 -#define IMX8ULP_CLK_ENETSTAMP_SEL 51 -#define IMX8ULP_CLK_SAI4_SEL 52 -#define IMX8ULP_CLK_SAI5_SEL 53 -#define IMX8ULP_CLK_AUD_CLK1 54 -#define IMX8ULP_CLK_ARM 55 +#define IMX8ULP_CLK_SAI4_SEL 51 +#define IMX8ULP_CLK_SAI5_SEL 52 +#define IMX8ULP_CLK_AUD_CLK1 53 +#define IMX8ULP_CLK_ARM 54 +#define IMX8ULP_CLK_ENET_TS_SEL 55 #define IMX8ULP_CLK_CGC1_END 56 +/* CGC2 */ #define IMX8ULP_CLK_PLL4_PRE_SEL 0 #define IMX8ULP_CLK_PLL4 1 #define IMX8ULP_CLK_PLL4_VCODIV 2 @@ -110,8 +109,12 @@ #define IMX8ULP_CLK_SAI6_SEL 42 #define IMX8ULP_CLK_SAI7_SEL 43 #define IMX8ULP_CLK_SPDIF_SEL 44 +#define IMX8ULP_CLK_HIFI_SEL 45 +#define IMX8ULP_CLK_HIFI_DIVCORE 46 +#define IMX8ULP_CLK_HIFI_DIVPLAT 47 +#define IMX8ULP_CLK_DSI_PHY_REF 48 -#define IMX8ULP_CLK_CGC2_END 45 +#define IMX8ULP_CLK_CGC2_END 49 /* PCC3 */ #define IMX8ULP_CLK_WDOG3 0 @@ -160,9 +163,12 @@ #define IMX8ULP_CLK_DMA1_CH29 43 #define IMX8ULP_CLK_DMA1_CH30 44 #define IMX8ULP_CLK_DMA1_CH31 45 +#define IMX8ULP_CLK_MU3_A 46 +#define IMX8ULP_CLK_MU0_B 47 -#define IMX8ULP_CLK_PCC3_END 46 +#define IMX8ULP_CLK_PCC3_END 48 +/* PCC4 */ #define IMX8ULP_CLK_FLEXSPI2 0 #define IMX8ULP_CLK_TPM6 1 #define IMX8ULP_CLK_TPM7 2 @@ -189,24 +195,25 @@ #define IMX8ULP_CLK_PCC4_END 23 +/* PCC5 */ #define IMX8ULP_CLK_TPM8 0 #define IMX8ULP_CLK_SAI6 1 #define IMX8ULP_CLK_SAI7 2 #define IMX8ULP_CLK_SPDIF 3 -#define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_ISI 4 +#define IMX8ULP_CLK_CSI_REGS 5 #define IMX8ULP_CLK_PCTLD 6 -#define IMX8ULP_CLK_CSI 7 -#define IMX8ULP_CLK_DSI 8 +#define IMX8ULP_CLK_CSI 7 +#define IMX8ULP_CLK_DSI 8 #define IMX8ULP_CLK_WDOG5 9 #define IMX8ULP_CLK_EPDC 10 -#define IMX8ULP_CLK_PXP 11 +#define IMX8ULP_CLK_PXP 11 #define IMX8ULP_CLK_SFA2 12 #define IMX8ULP_CLK_GPU2D 13 #define IMX8ULP_CLK_GPU3D 14 #define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 -#define IMX8ULP_CLK_CSI_CLK_ESC 17 +#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_ESC 17 #define IMX8ULP_CLK_RGPIOD 18 #define IMX8ULP_CLK_DMA2_MP 19 #define IMX8ULP_CLK_DMA2_CH0 20 @@ -241,7 +248,11 @@ #define IMX8ULP_CLK_DMA2_CH29 49 #define IMX8ULP_CLK_DMA2_CH30 50 #define IMX8ULP_CLK_DMA2_CH31 51 +#define IMX8ULP_CLK_MU2_B 52 +#define IMX8ULP_CLK_MU3_B 53 +#define IMX8ULP_CLK_AVD_SIM 54 +#define IMX8ULP_CLK_DSI_TX_ESC 55 -#define IMX8ULP_CLK_PCC5_END 52 +#define IMX8ULP_CLK_PCC5_END 56 #endif diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h new file mode 100644 index 0000000000..a556b2e96d --- /dev/null +++ b/include/dt-bindings/power/imx8ulp-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ +#define __DT_BINDINGS_IMX8ULP_POWER_H__ + +#define IMX8ULP_PD_DMA1 0 +#define IMX8ULP_PD_FLEXSPI2 1 +#define IMX8ULP_PD_USB0 2 +#define IMX8ULP_PD_USDHC0 3 +#define IMX8ULP_PD_USDHC1 4 +#define IMX8ULP_PD_USDHC2_USB1 5 +#define IMX8ULP_PD_DCNANO 6 +#define IMX8ULP_PD_EPDC 7 +#define IMX8ULP_PD_DMA2 8 +#define IMX8ULP_PD_GPU2D 9 +#define IMX8ULP_PD_GPU3D 10 +#define IMX8ULP_PD_HIFI4 11 +#define IMX8ULP_PD_ISI 12 +#define IMX8ULP_PD_MIPI_CSI 13 +#define IMX8ULP_PD_MIPI_DSI 14 +#define IMX8ULP_PD_PXP 15 + +#endif diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h new file mode 100644 index 0000000000..e99a4735c3 --- /dev/null +++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2021 NXP + */ + +#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H +#define DT_BINDING_PCC_RESET_IMX8ULP_H + +/* PCC3 */ +#define PCC3_WDOG3_SWRST 0 +#define PCC3_WDOG4_SWRST 1 +#define PCC3_LPIT1_SWRST 2 +#define PCC3_TPM4_SWRST 3 +#define PCC3_TPM5_SWRST 4 +#define PCC3_FLEXIO1_SWRST 5 +#define PCC3_I3C2_SWRST 6 +#define PCC3_LPI2C4_SWRST 7 +#define PCC3_LPI2C5_SWRST 8 +#define PCC3_LPUART4_SWRST 9 +#define PCC3_LPUART5_SWRST 10 +#define PCC3_LPSPI4_SWRST 11 +#define PCC3_LPSPI5_SWRST 12 + +/* PCC4 */ +#define PCC4_FLEXSPI2_SWRST 0 +#define PCC4_TPM6_SWRST 1 +#define PCC4_TPM7_SWRST 2 +#define PCC4_LPI2C6_SWRST 3 +#define PCC4_LPI2C7_SWRST 4 +#define PCC4_LPUART6_SWRST 5 +#define PCC4_LPUART7_SWRST 6 +#define PCC4_SAI4_SWRST 7 +#define PCC4_SAI5_SWRST 8 +#define PCC4_USDHC0_SWRST 9 +#define PCC4_USDHC1_SWRST 10 +#define PCC4_USDHC2_SWRST 11 +#define PCC4_USB0_SWRST 12 +#define PCC4_USB0_PHY_SWRST 13 +#define PCC4_USB1_SWRST 14 +#define PCC4_USB1_PHY_SWRST 15 +#define PCC4_ENET_SWRST 16 + +/* PCC5 */ +#define PCC5_TPM8_SWRST 0 +#define PCC5_SAI6_SWRST 1 +#define PCC5_SAI7_SWRST 2 +#define PCC5_SPDIF_SWRST 3 +#define PCC5_ISI_SWRST 4 +#define PCC5_CSI_REGS_SWRST 5 +#define PCC5_CSI_SWRST 6 +#define PCC5_DSI_SWRST 7 +#define PCC5_WDOG5_SWRST 8 +#define PCC5_EPDC_SWRST 9 +#define PCC5_PXP_SWRST 10 +#define PCC5_GPU2D_SWRST 11 +#define PCC5_GPU3D_SWRST 12 +#define PCC5_DC_NANO_SWRST 13 + +#endif /*DT_BINDING_RESET_IMX8ULP_H */ From cb9b70fd2feaa415280445e049c037a7b9092b56 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:38 +0100 Subject: [PATCH 25/43] imx8mq: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx8mq-evk.dts | 43 +++++++ arch/arm/dts/imx8mq-librem5-r3.dtsi | 45 +++++++ arch/arm/dts/imx8mq-librem5-r4.dts | 20 +-- arch/arm/dts/imx8mq-librem5.dtsi | 153 +++++++++++++++++++++-- arch/arm/dts/imx8mq-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq.dtsi | 19 +-- include/dt-bindings/reset/imx8mq-reset.h | 61 ++++----- 7 files changed, 281 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/imx8mq-librem5-r3.dtsi diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 99fed35168..82387b9cb8 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -71,12 +71,36 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -386,6 +410,16 @@ status = "okay"; }; +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -548,6 +582,15 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 diff --git a/arch/arm/dts/imx8mq-librem5-r3.dtsi b/arch/arm/dts/imx8mq-librem5-r3.dtsi new file mode 100644 index 0000000000..e4f8b47cce --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5-r3.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2021 Purism SPC + +/dts-v1/; + +/* + * This file describes hardware that is shared among r3 ("Dogwood") and + * later revisions of the Librem 5 so it has to be included in dts there. + */ + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&camera_front { + pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_r3_camera_pwr: r3camerapwrgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 + >; + }; +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts b/arch/arm/dts/imx8mq-librem5-r4.dts index cbfb49aa25..1056b7981b 100644 --- a/arch/arm/dts/imx8mq-librem5-r4.dts +++ b/arch/arm/dts/imx8mq-librem5-r4.dts @@ -1,35 +1,27 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC +// Copyright (C) 2021 Purism SPC /dts-v1/; -#include "imx8mq-librem5.dtsi" +#include "imx8mq-librem5-r3.dtsi" / { model = "Purism Librem 5r4"; compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - &bat { maxim,rsns-microohm = <1667>; }; -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &led_backlight { led-max-microamp = <25000>; }; +&lcd_panel { + compatible = "ys,ys57pss36bh5gq"; +}; + &proximity { proximity-near-level = <10>; }; diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi index 60d47c7149..ae08556b2e 100644 --- a/arch/arm/dts/imx8mq-librem5.dtsi +++ b/arch/arm/dts/imx8mq-librem5.dtsi @@ -7,6 +7,7 @@ #include "dt-bindings/input/input.h" #include +#include #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -14,6 +15,7 @@ / { model = "Purism Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; + chassis-type = "handset"; backlight_dsi: backlight-dsi { compatible = "led-backlight"; @@ -36,18 +38,45 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_keys>; - vol-down { + key-vol-down { label = "VOL_DOWN"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; }; - vol-up { + key-vol-up { label = "VOL_UP"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + max-brightness = <248>; + pwms = <&pwm2 0 50000 0>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + max-brightness = <248>; + pwms = <&pwm4 0 50000 0>; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + max-brightness = <248>; + pwms = <&pwm3 0 50000 0>; }; }; @@ -62,6 +91,40 @@ enable-active-high; }; + /* + * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC + * since we can't have it twice in the 2 different regulator nodes. + */ + reg_csi_1v8: regulator-csi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* controlled by the CAMERA_POWER_KEY HKS */ + reg_vcam_1v2: regulator-vcam-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_vdd_1v8>; + enable-active-high; + }; + + reg_vcam_2v8: regulator-vcam-2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_gnss: regulator-gnss { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -237,8 +300,13 @@ cpu-supply = <&buck2_reg>; }; +&csi1 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay"; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; @@ -283,15 +351,10 @@ }; partition@30000 { - label = "protected1"; - reg = <0x30000 0x10000>; + label = "firmware"; + reg = <0x30000 0x1d0000>; read-only; }; - - partition@40000 { - label = "rw"; - reg = <0x40000 0x1C0000>; - }; }; }; @@ -329,12 +392,24 @@ >; }; + pinctrl_camera_pwr: camerapwrgrp { + fsl,pins = < + /* CAMERA_PWR_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + /* CSI1_NRST */ + MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - /* CHG_STATUS_B */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 >; }; @@ -698,6 +773,10 @@ interrupt-names = "irq"; connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -725,7 +804,7 @@ compatible = "rohm,bd71837"; reg = <0x4b>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; + pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; @@ -958,6 +1037,31 @@ >; }; + camera_front: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-rates = <25000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + vdda-supply = <®_vcam_2v8>; + vddd-supply = <®_vcam_1v2>; + vddio-supply = <®_csi_1v8>; + rotation = <90>; + orientation = <0>; + + port { + camera1_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <80000000 200000000 300000000>; + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + backlight@36 { compatible = "ti,lm36922"; reg = <0x36>; @@ -996,6 +1100,12 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <®_csi_1v8>; + }; + bat: fuel-gauge@36 { compatible = "maxim,max17055"; reg = <0x36>; @@ -1003,6 +1113,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gauge>; + power-supplies = <&bq25895>; maxim,over-heat-temp = <700>; maxim,over-volt = <4500>; maxim,rsns-microohm = <5000>; @@ -1019,7 +1130,7 @@ ti,precharge-current = <130000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <500000>; /* uA */ + ti,boost-max-current = <1500000>; /* uA */ ti,use-vinmin-threshold = <1>; /* enable VINDPM */ ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; @@ -1031,6 +1142,21 @@ status = "okay"; }; +&mipi_csi1 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi1_sensor_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; @@ -1174,6 +1300,7 @@ #size-cells = <0>; dr_mode = "otg"; snps,dis_u3_susphy_quirk; + usb-role-switch; status = "okay"; port@0 { diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index c69c6cc58b..8d385e8da4 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -10,23 +10,23 @@ }; -&{/soc@0} { +&soc { u-boot,dm-spl; }; -&{/soc@0/bus@30000000} { +&aips1 { u-boot,dm-spl; }; -&{/soc@0/bus@30400000} { +&aips2 { u-boot,dm-spl; }; -&{/soc@0/bus@30800000} { +&aips3 { u-boot,dm-spl; }; -&{/soc@0/bus@32c00000} { +&aips4 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index 49eadb081b..19eaa52356 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -94,7 +94,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -320,7 +320,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -329,7 +329,7 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; - bus@30000000 { /* AIPS1 */ + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; #address-cells = <1>; @@ -507,7 +507,7 @@ <0x00030005 0x00000053>, <0x00030006 0x0000005f>, <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <1>; }; wdog1: watchdog@30280000 { @@ -534,7 +534,7 @@ status = "disabled"; }; - sdma2: sdma@302c0000 { + sdma2: dma-controller@302c0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = ; @@ -784,7 +784,7 @@ }; }; - bus@30400000 { /* AIPS2 */ + aips2: bus@30400000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30400000 0x400000>; #address-cells = <1>; @@ -844,7 +844,7 @@ }; }; - bus@30800000 { /* AIPS3 */ + aips3: bus@30800000 { /* AIPS3 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30800000 0x400000>; #address-cells = <1>; @@ -1018,6 +1018,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = ; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -1301,7 +1302,7 @@ status = "disabled"; }; - sdma1: sdma@30bd0000 { + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; @@ -1369,7 +1370,7 @@ }; }; - bus@32c00000 { /* AIPS4 */ + aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; #address-cells = <1>; diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 9a301082d3..705870693e 100755 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -28,37 +28,40 @@ #define IMX8MQ_RESET_A53_L2RESET 17 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 #define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ #define IMX8MQ_RESET_DISP_RESET 31 #define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_SW_M4C_RST 50 +#define IMX8MQ_RESET_SW_M4P_RST 51 +#define IMX8MQ_RESET_M4_ENABLE 52 -#define IMX8MQ_RESET_NUM 50 +#define IMX8MQ_RESET_NUM 53 #endif From 0b42fdca2d86939a51ff9eecedb930e42031c1e1 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:39 +0100 Subject: [PATCH 26/43] imx8mp: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler Tested-By: Tim Harvey #imx8m{m,n,p}-venice-* --- arch/arm/dts/imx8mp-dhcom-pdk2.dts | 29 +- arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +- arch/arm/dts/imx8mp-evk.dts | 179 +++++++---- arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts | 2 +- arch/arm/dts/imx8mp-icore-mx8mp.dtsi | 2 +- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 +-- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- arch/arm/dts/imx8mp-venice-gw74xx.dts | 290 +++++++++++++----- arch/arm/dts/imx8mp-verdin.dtsi | 32 +- arch/arm/dts/imx8mp.dtsi | 147 ++++++++- include/dt-bindings/clock/imx8mp-clock.h | 13 +- include/dt-bindings/interconnect/fsl,imx8mp.h | 59 ++++ include/dt-bindings/power/imx8mp-power.h | 21 +- include/dt-bindings/reset/imx8mp-reset.h | 50 +++ 14 files changed, 686 insertions(+), 208 deletions(-) create mode 100644 include/dt-bindings/interconnect/fsl,imx8mp.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts index c9a481ac9a..382fbedaf6 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts @@ -17,14 +17,13 @@ / { model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", - "fsl,imx8mp"; + "fsl,imx8mp"; chosen { stdout-path = &uart1; }; gpio-keys { - #size-cells = <0>; compatible = "gpio-keys"; button-0 { @@ -67,7 +66,7 @@ led { compatible = "gpio-leds"; - led-5 { + led-0 { color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -76,7 +75,7 @@ pinctrl-names = "default"; }; - led-6 { + led-1 { color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -85,7 +84,7 @@ pinctrl-names = "default"; }; - led-7 { + led-2 { color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -94,7 +93,7 @@ pinctrl-names = "default"; }; - led-8 { + led-3 { color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -123,10 +122,11 @@ mdio { ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy1>; pinctrl-names = "default"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + max-speed = <100>; reg = <7>; reset-assert-us = <1000>; reset-deassert-us = <1000>; @@ -143,7 +143,6 @@ txd2-skew-ps = <0>; txd3-skew-ps = <0>; txen-skew-ps = <0>; - max-speed = <100>; }; }; }; @@ -155,3 +154,15 @@ &usb3_1 { fsl,over-current-active-low; }; + +&iomuxc { + /* + * GPIO_A,B,C,D are connected to buttons. + * GPIO_E,F,H,I are connected to LEDs. + * GPIO_M is connected to CLKOUT2. + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_g &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index 197840d1a6..0f13ee3627 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021-2022 Marek Vasut */ @@ -224,10 +224,6 @@ }; &i2c3 { - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; @@ -393,10 +389,6 @@ }; &i2c4 { - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; @@ -407,10 +399,6 @@ }; &i2c5 { /* HDMI EDID bus */ - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c5>; @@ -802,8 +790,8 @@ pinctrl_i2c5: dhcom-i2c5-grp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 >; }; @@ -830,7 +818,7 @@ pinctrl_rtc: dhcom-rtc-grp { fsl,pins = < /* RTC_#INT Interrupt */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6 + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 >; }; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index 4c3ac4214a..9f1469db55 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8mp.dtsi" / { @@ -33,6 +34,12 @@ <0x1 0x00000000 0 0xc0000000>; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; regulator-name = "can1-stby"; @@ -55,6 +62,17 @@ enable-active-high; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -67,18 +85,20 @@ }; }; -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; +&A53_0 { + cpu-supply = <®_arm>; }; -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; }; &eqos { @@ -197,6 +217,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -221,7 +255,7 @@ regulator-ramp-delay = <3125>; }; - BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; @@ -334,6 +368,28 @@ */ }; +&pcie_phy { + fsl,refclk-pad-mode = ; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -395,41 +451,41 @@ &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 >; }; @@ -461,28 +517,41 @@ pinctrl_gpio_led: gpioledgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; pinctrl_i2c5: i2c5grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 >; }; @@ -500,20 +569,20 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 >; }; pinctrl_usb1_vbus: usb1grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 >; }; @@ -525,7 +594,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -537,7 +606,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -549,7 +618,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts index dd703b6a5e..a02b31c42d 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi index 5116079cce..a6319824ea 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 984a6b9ded..6aa720bafe 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -116,48 +116,48 @@ &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 >; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 >; }; @@ -175,7 +175,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -187,7 +187,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -199,7 +199,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index b5d640df7e..f9883aa133 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -10,7 +10,7 @@ }; }; -&{/soc@0} { +&soc { u-boot,dm-pre-reloc; u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts index 101d311476..06b4c93c58 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx8mp.dtsi" @@ -100,6 +101,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -123,8 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_can>; regulator-name = "can2_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -135,13 +141,29 @@ compatible = "regulator-fixed"; regulator-name = "wl"; gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; + startup-delay-us = <70000>; enable-active-high; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; }; +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -200,8 +222,8 @@ &gpio2 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "pcie3_wdis#", "", + "", "", "pcie2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -362,7 +384,7 @@ regulator-ramp-delay = <3125>; }; - BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; @@ -484,35 +506,40 @@ lan1: port@0 { reg = <0>; label = "lan1"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan2: port@1 { reg = <1>; label = "lan2"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan3: port@2 { reg = <2>; label = "lan3"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan4: port@3 { reg = <3>; label = "lan4"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan5: port@4 { reg = <4>; label = "lan5"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; - port@6 { - reg = <6>; + port@5 { + reg = <5>; label = "cpu"; ethernet = <&fec>; phy-mode = "rgmii-id"; @@ -542,6 +569,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + /* GPS / off-board header */ &uart1 { pinctrl-names = "default"; @@ -556,6 +605,21 @@ status = "okay"; }; +/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; + cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -563,22 +627,37 @@ }; /* USB1 - Type C front panel */ -&usb3_phy0 { +&usb3_0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - status = "okay"; -}; - -&usb3_0 { fsl,over-current-active-low; status = "okay"; }; -&usb_dwc3_0 { - dr_mode = "host"; +&usb3_phy0 { status = "okay"; }; +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + /* USB2 - USB3.0 Hub */ &usb3_phy1 { vbus-supply = <®_usb2_vbus>; @@ -596,6 +675,25 @@ status = "okay"; }; +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi_en>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@0 { + compatible = "cypress,cyw4373-fmac"; + reg = <0>; + }; +}; + /* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; @@ -622,15 +720,14 @@ pinctrl_hog: hoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ @@ -639,47 +736,47 @@ pinctrl_accel: accelgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 >; }; pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 >; }; @@ -692,61 +789,67 @@ pinctrl_gsc: gscgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 >; }; pinctrl_ksz: kszgrp { fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ - MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ >; }; pinctrl_gpio_leds: ledgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 - MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 >; }; pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 >; }; pinctrl_pps: ppsgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 >; }; @@ -758,22 +861,22 @@ pinctrl_reg_usb2: regusb2grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 >; }; pinctrl_reg_wifi: regwifigrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 >; }; pinctrl_sai2: sai2grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC - MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 - MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK - MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 >; }; @@ -811,7 +914,7 @@ pinctrl_uart3_gpio: uart3gpiogrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119 + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 >; }; @@ -825,7 +928,12 @@ pinctrl_usb1: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usbcon1: usb1congrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; @@ -840,6 +948,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi index 68100a1726..7b712d1888 100644 --- a/arch/arm/dts/imx8mp-verdin.dtsi +++ b/arch/arm/dts/imx8mp-verdin.dtsi @@ -49,7 +49,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + button-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; @@ -146,6 +146,30 @@ }; }; +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi1 { #address-cells = <1>; @@ -445,7 +469,7 @@ regulator-ramp-delay = <3125>; }; - BUCK2 { + reg_vdd_arm: BUCK2 { nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; regulator-always-on; @@ -619,7 +643,7 @@ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; reg = <0x4a>; /* Verdin GPIO_2 (SODIMM 208) */ - reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "disabled"; }; }; @@ -696,7 +720,7 @@ pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; reg = <0x4a>; /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index d9542dfff8..bb916a0948 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -5,8 +5,10 @@ #include #include +#include #include #include +#include #include #include @@ -195,7 +197,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -293,7 +295,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -469,6 +471,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mp-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { @@ -595,7 +602,34 @@ pgc_ispdwp: power-domain@18 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; + }; + + pgc_vpumix: power-domain@19 { + #power-domain-cells = <0>; + reg = ; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + pgc_vpu_g1: power-domain@20 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + pgc_vpu_g2: power-domain@21 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + pgc_vpu_vc8000e: power-domain@22 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; }; }; @@ -791,6 +825,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = ; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -903,7 +938,7 @@ <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -917,7 +952,7 @@ <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -931,7 +966,7 @@ <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1018,6 +1053,26 @@ }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MP_CLK_NOC>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200M { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-1000M { + opp-hz = /bits/ 64 <1000000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; @@ -1043,6 +1098,18 @@ "lcdif1", "isi", "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2"; + interconnects = + <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; + interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", + "isi1", "isi2", "isp0", "isp1", + "dwe"; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, @@ -1063,6 +1130,17 @@ #power-domain-cells = <1>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x32f00000 0x10000>; + resets = <&src IMX8MP_RESET_PCIEPHY>, + <&src IMX8MP_RESET_PCIEPHY_PERST>; + reset-names = "pciephy", "perst"; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; @@ -1074,10 +1152,46 @@ <&pgc_hsiomix>, <&pgc_pcie_phy>; power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; + interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; + interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; }; }; + pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie"; + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + linux,pci-domain = <0>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1109,6 +1223,23 @@ power-domains = <&pgc_gpu2d>; }; + vpumix_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; + power-domain-names = "bus", "g1", "g2", "vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, + <&clk IMX8MP_CLK_VPU_G2_ROOT>, + <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + clock-names = "g1", "g2", "vc8000e"; + interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; + interconnect-names = "g1", "g2", "vc8000e"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -1168,7 +1299,7 @@ interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u2-freeclk-exists-quirk; + snps,gfladj-refclk-lpm-sel-quirk; }; }; @@ -1210,7 +1341,7 @@ interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u2-freeclk-exists-quirk; + snps,gfladj-refclk-lpm-sel-quirk; }; }; diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fbb6e..9d5cc2ddde 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -117,7 +117,6 @@ #define IMX8MP_CLK_AUDIO_AHB 108 #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 #define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 #define IMX8MP_CLK_DRAM_ALT 112 #define IMX8MP_CLK_DRAM_APB 113 #define IMX8MP_CLK_VPU_G1 114 @@ -125,7 +124,6 @@ #define IMX8MP_CLK_CAN1 116 #define IMX8MP_CLK_CAN2 117 #define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_PHY 119 #define IMX8MP_CLK_PCIE_AUX 120 #define IMX8MP_CLK_I2C5 121 #define IMX8MP_CLK_I2C6 122 @@ -182,8 +180,6 @@ #define IMX8MP_CLK_MEDIA_CAM2_PIX 173 #define IMX8MP_CLK_MEDIA_LDB 174 #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_PCIE2_CTRL 176 -#define IMX8MP_CLK_PCIE2_PHY 177 #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 #define IMX8MP_CLK_ECSPI3 179 #define IMX8MP_CLK_PDM 180 @@ -321,8 +317,15 @@ #define IMX8MP_CLK_AUDIO_AXI 310 #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 +#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 +#define IMX8MP_CLK_CLKOUT1_SEL 314 +#define IMX8MP_CLK_CLKOUT1_DIV 315 +#define IMX8MP_CLK_CLKOUT1 316 +#define IMX8MP_CLK_CLKOUT2_SEL 317 +#define IMX8MP_CLK_CLKOUT2_DIV 318 +#define IMX8MP_CLK_CLKOUT2 319 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_END 320 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h new file mode 100644 index 0000000000..7357d41752 --- /dev/null +++ b/include/dt-bindings/interconnect/fsl,imx8mp.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright 2022 NXP + * Peng Fan + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H + +#define IMX8MP_ICN_NOC 0 +#define IMX8MP_ICN_MAIN 1 +#define IMX8MP_ICS_DRAM 2 +#define IMX8MP_ICS_OCRAM 3 +#define IMX8MP_ICM_A53 4 +#define IMX8MP_ICM_SUPERMIX 5 +#define IMX8MP_ICM_GIC 6 +#define IMX8MP_ICM_MLMIX 7 + +#define IMX8MP_ICN_AUDIO 8 +#define IMX8MP_ICM_DSP 9 +#define IMX8MP_ICM_SDMA2PER 10 +#define IMX8MP_ICM_SDMA2BURST 11 +#define IMX8MP_ICM_SDMA3PER 12 +#define IMX8MP_ICM_SDMA3BURST 13 +#define IMX8MP_ICM_EDMA 14 + +#define IMX8MP_ICN_GPU 15 +#define IMX8MP_ICM_GPU2D 16 +#define IMX8MP_ICM_GPU3D 17 + +#define IMX8MP_ICN_HDMI 18 +#define IMX8MP_ICM_HRV 19 +#define IMX8MP_ICM_LCDIF_HDMI 20 +#define IMX8MP_ICM_HDCP 21 + +#define IMX8MP_ICN_HSIO 22 +#define IMX8MP_ICM_NOC_PCIE 23 +#define IMX8MP_ICM_USB1 24 +#define IMX8MP_ICM_USB2 25 +#define IMX8MP_ICM_PCIE 26 + +#define IMX8MP_ICN_MEDIA 27 +#define IMX8MP_ICM_LCDIF_RD 28 +#define IMX8MP_ICM_LCDIF_WR 29 +#define IMX8MP_ICM_ISI0 30 +#define IMX8MP_ICM_ISI1 31 +#define IMX8MP_ICM_ISI2 32 +#define IMX8MP_ICM_ISP0 33 +#define IMX8MP_ICM_ISP1 34 +#define IMX8MP_ICM_DWE 35 + +#define IMX8MP_ICN_VIDEO 36 +#define IMX8MP_ICM_VPU_G1 37 +#define IMX8MP_ICM_VPU_G2 38 +#define IMX8MP_ICM_VPU_H1 39 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index 3f72bf7818..2fe3c2abad 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -38,9 +38,22 @@ #define IMX8MP_MEDIABLK_PD_ISI 3 #define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 #define IMX8MP_MEDIABLK_PD_LCDIF_2 5 -#define IMX8MP_MEDIABLK_PD_ISP2 6 -#define IMX8MP_MEDIABLK_PD_ISP1 7 -#define IMX8MP_MEDIABLK_PD_DWE 8 -#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9 +#define IMX8MP_MEDIABLK_PD_ISP 6 +#define IMX8MP_MEDIABLK_PD_DWE 7 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 + +#define IMX8MP_HDMIBLK_PD_IRQSTEER 0 +#define IMX8MP_HDMIBLK_PD_LCDIF 1 +#define IMX8MP_HDMIBLK_PD_PAI 2 +#define IMX8MP_HDMIBLK_PD_PVI 3 +#define IMX8MP_HDMIBLK_PD_TRNG 4 +#define IMX8MP_HDMIBLK_PD_HDMI_TX 5 +#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6 +#define IMX8MP_HDMIBLK_PD_HDCP 7 +#define IMX8MP_HDMIBLK_PD_HRV 8 + +#define IMX8MP_VPUBLK_PD_G1 0 +#define IMX8MP_VPUBLK_PD_G2 1 +#define IMX8MP_VPUBLK_PD_VC8000E 2 #endif diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 0000000000..2e8c9104b6 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 + +#define IMX8MP_RESET_NUM 38 + +#endif From f067b597431ef347813031b21e87a0a45459fec0 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:40 +0100 Subject: [PATCH 27/43] imx8mn: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler Tested-By: Tim Harvey #imx8m{m,n,p}-venice-* --- arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mn-evk.dtsi | 45 ++++++++++++++++++++++- arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +-- arch/arm/dts/imx8mn-venice-gw7902.dts | 9 ++--- arch/arm/dts/imx8mn.dtsi | 14 +++---- include/dt-bindings/interconnect/imx8mn.h | 41 +++++++++++++++++++++ 6 files changed, 101 insertions(+), 18 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mn.h diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi index 02f37dcda7..9e82069c94 100644 --- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi @@ -146,7 +146,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -182,7 +182,7 @@ &usbotg1 { vbus-supply = <®_usb_otg_vbus>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index d1f6cccfa0..261c365400 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -47,6 +47,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -57,6 +62,25 @@ clock-names = "mclk"; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "fsl,imx-audio-wm8524"; model = "wm8524-audio"; @@ -78,7 +102,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -183,6 +207,16 @@ }; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -354,6 +388,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts index f61c48776c..3ed7021a48 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony.dts +++ b/arch/arm/dts/imx8mn-var-som-symphony.dts @@ -26,19 +26,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = ; }; - home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index 367a232675..dd4302ac1d 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -39,13 +39,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -59,14 +59,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; @@ -213,7 +213,6 @@ compatible = "microchip,mcp2515"; reg = <0>; clocks = <&can20m>; - oscillator-frequency = <20000000>; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <10000000>; diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index e41e1d56f9..cb2836bfbd 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -269,7 +269,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -422,7 +422,7 @@ "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; status = "disabled"; }; @@ -672,7 +672,6 @@ <&clk IMX8MN_CLK_GPU_SHADER>, <&clk IMX8MN_CLK_GPU_BUS_ROOT>, <&clk IMX8MN_CLK_GPU_AHB>; - resets = <&src IMX8MQ_RESET_GPU_RESET>; }; pgc_dispmix: power-domain@3 { @@ -857,6 +856,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = ; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -941,7 +941,7 @@ <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -955,7 +955,7 @@ <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -969,7 +969,7 @@ <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 0000000000..307b977100 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ From dbd5ca2e46055f3deedd849516d9a641e94c0600 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Mon, 7 Nov 2022 22:22:41 +0100 Subject: [PATCH 28/43] imx8mm: synchronise device tree with linux Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler Tested-By: Tim Harvey #imx8m{m,n,p}-venice-* --- arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 43 +++++++++++++++++++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 14 +++---- arch/arm/dts/imx8mm-mx8menlo.dts | 14 +++---- arch/arm/dts/imx8mm-u-boot.dtsi | 2 +- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++------ arch/arm/dts/imx8mm-venice-gw7901.dts | 12 ++++-- arch/arm/dts/imx8mm-venice-gw7902.dts | 14 +++---- arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +-- arch/arm/dts/imx8mm-venice-gw7904.dts | 4 ++ arch/arm/dts/imx8mm-verdin.dtsi | 50 +++++++++++++++++------ include/dt-bindings/interconnect/imx8mm.h | 50 +++++++++++++++++++++++ 12 files changed, 179 insertions(+), 58 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mm.h diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index f338a886d8..03266bd90a 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -285,14 +285,14 @@ &usbotg1 { vbus-supply = <®_usbotg1>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; &usbotg2 { pinctrl-names = "default"; disable-over-current; - dr_mode="host"; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index c42b966f7a..7d6317d95b 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -75,6 +75,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -83,6 +88,25 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -346,6 +370,16 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -494,6 +528,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi index b40148d728..def7bb5d37 100644 --- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi +++ b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { @@ -84,42 +84,42 @@ }; reg_buck1: buck1 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck2: buck2 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck3: buck3 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck4: buck4 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck5: buck5 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck6: buck6 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts index 92eaf4ef45..32f6f2f50c 100644 --- a/arch/arm/dts/imx8mm-mx8menlo.dts +++ b/arch/arm/dts/imx8mm-mx8menlo.dts @@ -20,13 +20,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user1 { + led-1 { label = "TestLed601"; gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - user2 { + led-2 { label = "TestLed602"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -152,11 +152,11 @@ * CPLD_reset is RESET_SOFT in schematic */ gpio-line-names = - "CPLD_D[1]", "CPLD_int", "CPLD_reset", "", - "", "CPLD_D[0]", "", "", - "", "", "", "CPLD_D[2]", - "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]", - "CPLD_D[7]", "", "", "", + "CPLD_D[6]", "CPLD_int", "CPLD_reset", "", + "", "CPLD_D[7]", "", "", + "", "", "", "CPLD_D[5]", + "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]", + "CPLD_D[0]", "", "", "", "", "", "", "", "", "", "", "KBD_intK", "", "", "", ""; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index a5e30f7994..60d49bc3d7 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -9,7 +9,7 @@ }; }; -&{/soc@0} { +&soc { u-boot,dm-pre-reloc; u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index 00f86cada3..66a0d103c9 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -16,13 +16,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -36,14 +36,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; @@ -286,8 +286,8 @@ regulator-name = "buck1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; regulator-always-on; }; @@ -297,8 +297,8 @@ regulator-name = "buck2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; @@ -308,8 +308,8 @@ regulator-name = "buck3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-always-on; }; @@ -318,8 +318,8 @@ regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index 24737e8903..d3ee6fc4ba 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -38,13 +38,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -58,14 +58,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; @@ -626,24 +626,28 @@ lan1: port@0 { reg = <0>; label = "lan1"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan2: port@1 { reg = <1>; label = "lan2"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan3: port@2 { reg = <2>; label = "lan3"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan4: port@3 { reg = <3>; label = "lan4"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 8e8d0d34c2..31f4c735fe 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -42,13 +42,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -62,14 +62,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; @@ -222,7 +222,6 @@ compatible = "microchip,mcp2515"; reg = <0>; clocks = <&can20m>; - oscillator-frequency = <20000000>; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <10000000>; @@ -651,7 +650,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; uart-has-rtscts; status = "okay"; }; @@ -742,9 +741,6 @@ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts index 1b69ac0e12..19f6d2943d 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ b/arch/arm/dts/imx8mm-venice-gw7903.dts @@ -33,13 +33,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -53,7 +53,7 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts index 2b68fb3e43..a67771d021 100644 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ b/arch/arm/dts/imx8mm-venice-gw7904.dts @@ -617,6 +617,10 @@ status = "okay"; }; +&pgc_mipi { + status = "disabled"; +}; + /* off-board RS232 */ &uart1 { pinctrl-names = "default"; diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi index eafa88d980..bcab830c6e 100644 --- a/arch/arm/dts/imx8mm-verdin.dtsi +++ b/arch/arm/dts/imx8mm-verdin.dtsi @@ -32,10 +32,10 @@ }; /* Fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { + clk40m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <20000000>; + clock-frequency = <40000000>; }; gpio-keys { @@ -43,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + key-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; @@ -53,6 +53,21 @@ }; }; + hdmi_connector: hdmi-connector { + compatible = "hdmi-connector"; + ddc-i2c-bus = <&i2c2>; + label = "hdmi"; + type = "a"; + status = "disabled"; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + status = "disabled"; + }; + /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -154,6 +169,14 @@ cpu-supply = <®_vdd_arm>; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -194,8 +217,8 @@ can1: can@0 { compatible = "microchip,mcp251xfd"; - clocks = <&clk20m>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk40m>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_int>; reg = <0>; @@ -359,8 +382,8 @@ nxp,dvs-standby-voltage = <850000>; regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <950000>; - regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <805000>; regulator-name = "On-module +VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -368,8 +391,8 @@ reg_vdd_dram: BUCK3 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <950000>; - regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; }; @@ -408,7 +431,7 @@ reg_vdd_snvs: LDO2 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <800000>; regulator-min-microvolt = <800000>; regulator-name = "On-module +V0.8_SNVS (LDO2)"; }; @@ -553,8 +576,8 @@ status = "disabled"; }; - lvds_ti_sn65dsi83: bridge@2c { - compatible = "ti,sn65dsi83"; + lvds_ti_sn65dsi84: bridge@2c { + compatible = "ti,sn65dsi84"; /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; @@ -595,7 +618,7 @@ pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; reg = <0x4a>; /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -737,6 +760,7 @@ }; &usbphynop2 { + power-domains = <&pgc_otg2>; vcc-supply = <®_vdd_3v3>; }; diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 0000000000..8f10bb06cb --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ From 899f291bd16fd710acb2b9b6942da8c538c4f781 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 08:43:41 -0500 Subject: [PATCH 29/43] configs: imx8mn_beacon: Re-align memory to standard imx8mn settings The imx8mn_beacon board does not use the same memory map as the reference design from NXP or other imx8mn boards. As such, memory is more limited in SPL. Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases the amount of available meory for the SPL stack. Doing this allows the board to no longer define CONFIG_MALLOC_F_ADDR. Since SYS_LOAD_ADDR also does not align with other boards, move it too. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- configs/imx8mn_beacon_2g_defconfig | 7 +++---- configs/imx8mn_beacon_defconfig | 7 +++---- include/configs/imx8mn_beacon.h | 8 -------- 3 files changed, 6 insertions(+), 16 deletions(-) diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 3f6a42b5bd..862d9847b6 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -16,10 +16,9 @@ CONFIG_IMX8MN_BEACON_2GB_LPDDR=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_LTO=y @@ -35,12 +34,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_START_ADDR=0x950000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_STACK=0x980000 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 0d8601ad39..c9d0b64617 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -15,10 +15,9 @@ CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_LTO=y @@ -34,12 +33,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_START_ADDR=0x950000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_STACK=0x980000 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 6faecbde77..930b11b75e 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -13,14 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 - -/* For RAW image gives a error info not panic */ - -#endif /* CONFIG_SPL_BUILD */ - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ From f2fe18fa3826e67c66d8a30a056fadc81a9966c9 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 22 Oct 2022 08:43:43 -0500 Subject: [PATCH 30/43] configs: imx8mn_beacon: Enable SPL_DM_PMIC_BD71837 To properly operate the Nano with LPDDR4 at 1.6GHz, the voltage needs to be adjusted before DDR is initialized. Enable the PMIC in SPL to do this. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Reviewed-by: Peng Fan --- configs/imx8mn_beacon_2g_defconfig | 1 + configs/imx8mn_beacon_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 862d9847b6..94a8e85847 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -120,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index c9d0b64617..b2c26637e2 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -124,6 +124,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y From f827f84d3f5607d0b33e927f6127a888e7bd664f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Nov 2022 08:12:54 -0300 Subject: [PATCH 31/43] wandboard: Pass mmc aliases Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi. After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux"), the aliases node is gone as the upstream version does not have it. This causes a regression in which the SD card cannot be found anymore: Since commit the aliases node has been removed U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300) CPU: Freescale i.MX6QP rev1.0 at 792 MHz Reset cause: POR DRAM: 2 GiB Core: 62 devices, 17 uclasses, devicetree: separate PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... MMC: no card present *** Warning - No block device, using default environment Fix it by passing the alias node in the u-boot.dtsi file to restore the original behaviour where the SD card (esdhc3) was mapped to mmc0. Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi | 1 + arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi | 1 + arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi | 9 +++++++++ arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi | 1 + 4 files changed, 12 insertions(+) create mode 100644 arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi diff --git a/arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi b/arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi new file mode 100644 index 0000000000..6785db754b --- /dev/null +++ b/arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi @@ -0,0 +1 @@ +#include "imx6qdl-wandboard-u-boot.dtsi" diff --git a/arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi b/arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi new file mode 100644 index 0000000000..6785db754b --- /dev/null +++ b/arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi @@ -0,0 +1 @@ +#include "imx6qdl-wandboard-u-boot.dtsi" diff --git a/arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi b/arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi new file mode 100644 index 0000000000..46c4b3b31f --- /dev/null +++ b/arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "imx6qdl-u-boot.dtsi" + +/ { + aliases { + mmc0 = &usdhc3; + }; +}; diff --git a/arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi b/arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi new file mode 100644 index 0000000000..6785db754b --- /dev/null +++ b/arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi @@ -0,0 +1 @@ +#include "imx6qdl-wandboard-u-boot.dtsi" From 20cc70a84f5d8bb0795f09daccbf06f6a846d14b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Nov 2022 08:12:55 -0300 Subject: [PATCH 32/43] wandboard: Select DM_SERIAL The conversion to DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam --- configs/wandboard_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 70b4cf9ffa..33d9db56e1 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -72,6 +72,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_USB=y From 55be8433d56172d189306f64fe606f9131183cef Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:37 +0100 Subject: [PATCH 33/43] imx: imx8qm-rom7720: switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute --- arch/arm/dts/imx8qm-rom7720-a1.dts | 1 + arch/arm/dts/imx8qm-u-boot.dtsi | 133 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + .../advantech/imx8qm_rom7720_a1/imximage.cfg | 4 +- configs/imx8qm_rom7720_a1_4G_defconfig | 3 +- doc/board/advantech/imx8qm-rom7720-a1.rst | 3 +- 6 files changed, 140 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index d1f2fff869..332d441c6d 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -10,6 +10,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Advantech iMX8QM Qseven series"; diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi new file mode 100644 index 0000000000..f3fc90c9bb --- /dev/null +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + fit,external-offset = ; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x00910000>; + load = <0x00091000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; + + scfw { + arch = "arm64"; + compression = "none"; + description = "System Controler Firmware"; + type = "firmware"; + + scfw_blob { + filename = "mx8qm-val-scfw-tcm.bin"; + type = "blob-ext"; + }; + }; + + seco { + arch = "arm64"; + compression = "none"; + description = "Seco Firmware"; + type = "firmware"; + + seco_blob { + filename = "mx8qm-ahab-container.img"; + type = "blob-ext"; + }; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + binman_configuration: @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; + loadables = "atf"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + filename = "spl.bin"; + offset = <0x0>; + type = "blob-ext"; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 2ba7454457..a7e3af57dc 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -82,6 +82,7 @@ config TARGET_CONGA_QMX8 config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/advantech/imx8qm_rom7720_a1/imximage.cfg b/board/advantech/imx8qm_rom7720_a1/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/advantech/imx8qm_rom7720_a1/imximage.cfg +++ b/board/advantech/imx8qm_rom7720_a1/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index c3c93bfdf8..7819bef863 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -20,8 +20,9 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst index bd4be1dbeb..953cf01fde 100644 --- a/doc/board/advantech/imx8qm-rom7720-a1.rst +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make imx8qm_rom7720_a1_4G_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- From 5a878c9472ef37cda7028a0c21ff7c2364aaff96 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:38 +0100 Subject: [PATCH 34/43] imx: imx8qm: cgtqmx8: switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute Reviewed-by: Fabio Estevam Reviewed-by: Simon Glass Reviewed-by: Peng Fan --- arch/arm/dts/imx8qm-cgtqmx8.dts | 1 + arch/arm/mach-imx/imx8/Kconfig | 1 + board/congatec/cgtqmx8/imximage.cfg | 4 ++-- configs/cgtqmx8_defconfig | 4 +++- doc/board/congatec/cgtqmx8.rst | 3 +-- 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts index 555c357f6f..919d00644f 100644 --- a/arch/arm/dts/imx8qm-cgtqmx8.dts +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -12,6 +12,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Congatec QMX8 Qseven series"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index a7e3af57dc..d423cf8563 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -76,6 +76,7 @@ config TARGET_IMX8QM_MEK config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/congatec/cgtqmx8/imximage.cfg +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index ba2b09fb44..94a31d1677 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -20,8 +20,10 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set +# CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index bccdef2f16..16711a844d 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make cgtqmx8_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- From 61c57b614e5d70698906d9048e2aa195156ffe68 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:39 +0100 Subject: [PATCH 35/43] imx: imx8qxp: imx8qxp_mek switch to binman Switch to use binman pack images Signed-off-by: Oliver Graute Reviewed-by: Peng Fan --- arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 2 + arch/arm/dts/imx8qxp-u-boot.dtsi | 133 +++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + board/freescale/imx8qxp_mek/imximage.cfg | 3 +- configs/imx8qxp_mek_defconfig | 2 + doc/board/nxp/imx8qxp_mek.rst | 2 +- 6 files changed, 140 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx8qxp-u-boot.dtsi diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index ae037c7550..17f44e1ce7 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2018, 2021 NXP */ +#include "imx8qxp-u-boot.dtsi" + &{/imx8qx-pm} { u-boot,dm-spl; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi new file mode 100644 index 0000000000..01183f8ade --- /dev/null +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, 2021 NXP + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { +#ifdef CONFIG_SPL + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; +#endif + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + fit,external-offset = ; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x00910000>; + load = <0x00091000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; + + scfw { + arch = "arm64"; + compression = "none"; + description = "System Controler Firmware"; + type = "firmware"; + + scfw_blob { + filename = "mx8qx-mek-scfw-tcm.bin"; + type = "blob-ext"; + }; + }; + + seco { + arch = "arm64"; + compression = "none"; + description = "Seco Firmware"; + type = "firmware"; + + seco_blob { + filename = "mx8qxc0-ahab-container.img"; + type = "blob-ext"; + }; + }; + + fdt { + type = "flat_dt"; + compression = "none"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + fdt = "fdt"; + firmware = "uboot"; + loadables = "atf"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + filename = "spl.bin"; + offset = <0x0>; + type = "blob-ext"; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index d423cf8563..23a7fcf361 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -90,6 +90,7 @@ config TARGET_IMX8QM_ROM7720_A1 config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" + select BINMAN select BOARD_LATE_INIT select IMX8QXP select FSL_CAAM diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg index 89a4736ab7..88d6955a9e 100644 --- a/board/freescale/imx8qxp_mek/imximage.cfg +++ b/board/freescale/imx8qxp_mek/imximage.cfg @@ -7,8 +7,7 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd /* SoC type IMX8QX */ SOC_TYPE IMX8QX /* Append seco container image */ diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 3865eb393f..a00951a3b0 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 diff --git a/doc/board/nxp/imx8qxp_mek.rst b/doc/board/nxp/imx8qxp_mek.rst index 215627cfa6..708db1952e 100644 --- a/doc/board/nxp/imx8qxp_mek.rst +++ b/doc/board/nxp/imx8qxp_mek.rst @@ -50,7 +50,7 @@ Build U-Boot .. code-block:: bash $ make imx8qxp_mek_defconfig - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- From 4aa738823c5e1683bfb2113e53247f28fc437c24 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:40 +0100 Subject: [PATCH 36/43] imx: imx8qm: imx8qm_mek switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute --- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + board/freescale/imx8qm_mek/README | 2 +- configs/imx8qm_mek_defconfig | 2 ++ 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index a95209e141..eefdccf992 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2018, 2021 NXP */ +#include "imx8qm-u-boot.dtsi" + &{/imx8qm-pm} { u-boot,dm-spl; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 23a7fcf361..4ccbabf506 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -68,6 +68,7 @@ config TARGET_GIEDI config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" + select BINMAN select BOARD_LATE_INIT select IMX8QM select FSL_CAAM diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index 570ed7e210..b1a4c6cc82 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -40,7 +40,7 @@ And copy the following firmwares to U-Boot folder: Build U-Boot ============ $ make imx8qm_mek_defconfig -$ make flash.bin +$ make Flash the binary into the SD card ================================= diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index da27383e68..4fc828681b 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 From dcbc4ae9d6699a1bc8c6b0509b0b22ec2d1a9429 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:41 +0100 Subject: [PATCH 37/43] imx: imx8qxp: giedi switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute --- arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + board/siemens/capricorn/imximage.cfg | 2 +- configs/giedi_defconfig | 2 ++ 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi index 1cf58fc3f9..f3e6421b2b 100644 --- a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2019 Siemens AG */ +#include "imx8qxp-u-boot.dtsi" + &{/imx8qx-pm} { u-boot,dm-spl; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4ccbabf506..63d99ea23e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -62,6 +62,7 @@ config TARGET_DENEB config TARGET_GIEDI bool "Support i.MX8QXP Capricorn Giedi board" + select BINMAN select BOARD_LATE_INIT select FACTORYSET select IMX8QXP diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index fa871bac21..4350e2967c 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -8,7 +8,7 @@ /* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd /* SoC type IMX8QX */ SOC_TYPE IMX8QX /* Append seco container image */ diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index e20830df4a..6d00a61d3d 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -26,6 +26,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 From bc1d145eafc1cc078abb3f86a37cfdc52abe891f Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:42 +0100 Subject: [PATCH 38/43] imx: imx8qxp: deneb switch to binman Signed-off-by: Oliver Graute Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8/Kconfig | 1 + configs/deneb_defconfig | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 63d99ea23e..018b87b85b 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -56,6 +56,7 @@ config TARGET_COLIBRI_IMX8X config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" + select BINMAN select BOARD_LATE_INIT select FACTORYSET select IMX8QXP diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index cb4dd33202..a5836f4c86 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -26,6 +26,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 From bdadc140a127b14a666d2007eddc3f65c8de7d5a Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:43 +0100 Subject: [PATCH 39/43] imx: imx8x: colibri: switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute --- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + configs/colibri-imx8x_defconfig | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index 322429a98a..91e2944781 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2019 Toradex AG */ +#include "imx8qxp-u-boot.dtsi" + &{/imx8qx-pm} { u-boot,dm-pre-proper; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 018b87b85b..37d12d1895 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -51,6 +51,7 @@ config TARGET_APALIS_IMX8 config TARGET_COLIBRI_IMX8X bool "Support Colibri iMX8X module" + select BINMAN select BOARD_LATE_INIT select IMX8QXP diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index fb9171a703..6896236045 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -17,6 +17,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set From b8072ae848b73e89a73ba5b535324e4dc2793f37 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 4 Nov 2022 16:03:44 +0100 Subject: [PATCH 40/43] imx: imx8: apalis: switch to binman Switch to use binman to pack images Signed-off-by: Oliver Graute --- arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 2 ++ arch/arm/dts/imx8qm-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + configs/apalis-imx8_defconfig | 1 + 4 files changed, 6 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 956d724979..8fd0e33d2b 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2019 Toradex AG */ +#include "imx8qm-u-boot.dtsi" + &mu { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index f3fc90c9bb..3507489a81 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -10,6 +10,7 @@ }; &binman { +#ifdef CONFIG_SPL u-boot-spl-ddr { align = <4>; align-size = <4>; @@ -33,6 +34,7 @@ }; }; }; +#endif itb { filename = "u-boot.itb"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 37d12d1895..91bd888308 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -46,6 +46,7 @@ choice config TARGET_APALIS_IMX8 bool "Support Apalis iMX8 module" + select BINMAN select BOARD_LATE_INIT select IMX8QM diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 6226d50c8a..d0e24785ae 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -17,6 +17,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_LOG=y From cca660c2bd0a7e04df9f7c6db95cd5e08408fa8c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 9 Nov 2022 16:50:49 +0100 Subject: [PATCH 41/43] Convert mx8 u-boot.dtsi to CONFIG_TEXT_BASE Signed-off-by: Stefano Babic Signed-off-by: Fabio Estevam --- arch/arm/dts/imx8qm-u-boot.dtsi | 2 +- arch/arm/dts/imx8qxp-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index 3507489a81..442e64badc 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -50,7 +50,7 @@ arch = "arm64"; compression = "none"; description = "U-Boot (64-bit)"; - load = ; + load = ; type = "standalone"; uboot-blob { diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 01183f8ade..e8df5bb8bf 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -50,7 +50,7 @@ arch = "arm64"; compression = "none"; description = "U-Boot (64-bit)"; - load = ; + load = ; type = "standalone"; uboot-blob { From c9713c1551277654626a6cc4b41a391c3741f63f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 11 Nov 2022 15:46:42 -0300 Subject: [PATCH 42/43] imx8-u-boot: Fix SPL guard option We should guard the SPL nodes against CONFIG_SPL_BUILD to fix the following build error when the blobs are absent: binman: Fail open first container file mx8qm-ahab-container.img Signed-off-by: Fabio Estevam --- arch/arm/dts/imx8qm-u-boot.dtsi | 2 +- arch/arm/dts/imx8qxp-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index 442e64badc..a3e0af4810 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL +#ifdef CONFIG_SPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index e8df5bb8bf..7622c40906 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL +#ifdef CONFIG_SPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; From fc1c1760de38823edbdc2cdd9606dff938a07f6e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Nov 2022 08:39:33 -0300 Subject: [PATCH 43/43] Revert "serial: mxc: have putc use the TXFIFO" This reverts commit c7878a0483c59c48a730123bc0f4659fd40921bf. Since commit c7878a0483c5 ("serial: mxc: have putc use the TXFIFO"), serial console corruption can be seen when priting inside board_init(). Revert it to avoid the regression. Reported-by: Tim Harvey Signed-off-by: Fabio Estevam Acked-by: Tim Harvey --- drivers/serial/serial_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 4cf79c1ca2..82c0d84628 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, const char ch) struct mxc_serial_plat *plat = dev_get_plat(dev); struct mxc_uart *const uart = plat->reg; - if (readl(&uart->ts) & UTS_TXFULL) + if (!(readl(&uart->ts) & UTS_TXEMPTY)) return -EAGAIN; writel(ch, &uart->txd);