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armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC

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1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Calvin Johnson 2018-03-08 15:30:33 +05:30 committed by Joe Hershberger
parent c44f8125bc
commit c4dc68b02f
3 changed files with 36 additions and 0 deletions
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23
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -612,6 +612,29 @@ int setup_chip_volt(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 ecccr2;
out_be32(&scfg->pfeasbcr,
in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
out_be32(&scfg->pfebsbcr,
in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
/* CCI-400 QoS settings for PFE */
out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
| SCFG_WR_QOS1_PFE2_QOS));
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS));
ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC);
}
#endif
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +

10
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -205,6 +205,8 @@ struct sys_info {
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0
#define DCFG_DCSR_ECCCR2 0x524
#define DISABLE_PFE_ECC BIT(13)
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@ -410,6 +412,14 @@ struct ccsr_gur {
#define SCFG_PFEASBCR_ARSNP BIT(27)
#define SCFG_PFEASBCR_AWSNP BIT(26)
/* WR_QoS1 PFE bit definitions */
#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24)
#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20)
/* RD_QoS1 PFE bit definitions */
#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24)
#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20)
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u8 res_000[0x100-0x000];

3
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
/* Setup core vdd in unit mV */
int board_setup_core_volt(u32 vdd);
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void);
#endif
#endif
void cpu_name(char *name);