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Merge branch 'master' of git://git.denx.de/u-boot-spi

Browse Source 
- Drop zipitz2 board (Tom)
- Add DEPRECATED option (Tom)
- Mark legacy or non-dm drivers as DEPRECATED (Jagan)
This commit is contained in:
Tom Rini 2019-06-17 11:32:22 -04:00
commit c3f43185ee
31 changed files with 46 additions and 550 deletions
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7
Kconfig
View File

@ -20,6 +20,13 @@ config BROKEN
This option cannot be enabled. It is used as dependency
for broken and incomplete features.
config DEPRECATED
bool
help
This option cannot be enabled. It it used as a dependency for
code that relies on deprecated features that will be removed and
the conversion deadline has passed.
config LOCALVERSION
string "Local version - append to U-Boot release"
help

19
Makefile
View File

@ -928,6 +928,14 @@ cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
all: $(ALL-y)
ifeq ($(CONFIG_DEPRECATED),y)
$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
ifeq ($(CONFIG_SPI),y)
ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
$(warning "The relevant config item with associated code will remove in v2019.07 release.")
endif
endif
endif
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@ -1004,17 +1012,6 @@ ifeq ($(CONFIG_OF_EMBED),y)
@echo >&2 "See doc/README.fdt-control for more info."
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_SPI),y)
ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board does not use CONFIG_DM_SPI. Please update"
@echo >&2 "the board before v2019.04 for no dm conversion"
@echo >&2 "and v2019.07 for partially dm converted drivers."
@echo >&2 "Failure to update can lead to driver/board removal"
@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
@echo >&2 "===================================================="
endif
endif
ifeq ($(CONFIG_SPI_FLASH),y)
ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
@echo >&2 "===================== WARNING ======================"

2
arch/Kconfig
View File

@ -101,6 +101,7 @@ config SANDBOX
imply CMD_IOTRACE
imply CMD_LZMADEC
imply CMD_SATA
imply CMD_SF
imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
@ -147,6 +148,7 @@ config X86
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH

5
arch/arm/Kconfig
View File

@ -1410,10 +1410,6 @@ config TARGET_H2200
bool "Support h2200"
select CPU_PXA
config TARGET_ZIPITZ2
bool "Support zipitz2"
select CPU_PXA
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@ -1727,7 +1723,6 @@ source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"

4
board/renesas/sh7752evb/sh7752evb.c
View File

@ -174,6 +174,7 @@ int board_mmc_init(bd_t *bis)
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
struct spi_flash *spi;
int ret;
@ -190,6 +191,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size)
return 1;
}
spi_flash_free(spi);
#endif
return 0;
}
@ -239,6 +241,7 @@ int board_late_init(void)
return 0;
}
#ifdef CONFIG_DEPRECATED
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, ret;
@ -302,3 +305,4 @@ U_BOOT_CMD(
"write MAC address for GETHERC",
"[GETHERC ch0] [GETHERC ch1]\n"
);
#endif

4
board/renesas/sh7753evb/sh7753evb.c
View File

@ -190,6 +190,7 @@ int board_mmc_init(bd_t *bis)
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
struct spi_flash *spi;
int ret;
@ -206,6 +207,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size)
return 1;
}
spi_flash_free(spi);
#endif
return 0;
}
@ -255,6 +257,7 @@ int board_late_init(void)
return 0;
}
#ifdef CONFIG_DEPRECATED
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, ret;
@ -318,3 +321,4 @@ U_BOOT_CMD(
"write MAC address for GETHERC",
"[GETHERC ch0] [GETHERC ch1]\n"
);
#endif

9
board/renesas/sh7757lcr/sh7757lcr.c
View File

@ -30,6 +30,7 @@ static void init_gctrl(void)
static int init_pcie_bridge_from_spi(void *buf, size_t size)
{
#ifdef CONFIG_DEPRECATED
struct spi_flash *spi;
int ret;
unsigned long pcie_addr;
@ -54,6 +55,10 @@ static int init_pcie_bridge_from_spi(void *buf, size_t size)
spi_flash_free(spi);
return 0;
#else
printf("No SPI support so no PCIe support\n");
return 1;
#endif
}
static void init_pcie_bridge(void)
@ -231,6 +236,7 @@ int board_mmc_init(bd_t *bis)
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
struct spi_flash *spi;
int ret;
@ -247,6 +253,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size)
return 1;
}
spi_flash_free(spi);
#endif
return 0;
}
@ -352,6 +359,7 @@ U_BOOT_CMD(
"enable SH-G200 bus (disable PCIe-G200)"
);
#ifdef CONFIG_DEPRECATED
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, ret;
@ -418,3 +426,4 @@ U_BOOT_CMD(
"write MAC address for ETHERC/GETHERC",
"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
);
#endif

3
board/work-microwave/work_92105/Makefile
View File

@ -6,5 +6,6 @@
ifdef CONFIG_SPL_BUILD
obj-y += work_92105_spl.o
else
obj-y += work_92105.o work_92105_display.o
obj-y += work_92105.o
obj-$(CONFIG_DEPRECATED) += work_92105_display.o
endif

2
board/work-microwave/work_92105/work_92105.c
View File

@ -52,8 +52,10 @@ int board_early_init_r(void)
gpio_request(GPO_19, "NAND_nWP");
gpio_direction_output(GPO_19, 1);
#ifdef CONFIG_DEPRECATED
/* initialize display */
work_92105_display_init();
#endif
return 0;
}

9
board/zipitz2/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_ZIPITZ2
config SYS_BOARD
default "zipitz2"
config SYS_CONFIG_NAME
default "zipitz2"
endif

6
board/zipitz2/MAINTAINERS
View File

@ -1,6 +0,0 @@
ZIPITZ2 BOARD
M: Vasily Khoruzhick <anarsoul@gmail.com>
S: Maintained
F: board/zipitz2/
F: include/configs/zipitz2.h
F: configs/zipitz2_defconfig

8
board/zipitz2/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2009
# Marek Vasut <marek.vasut@gmail.com>
#
# Heavily based on pxa255_idp platform
obj-y := zipitz2.o

219
board/zipitz2/zipitz2.c
View File

@ -1,219 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2009
* Marek Vasut <marek.vasut@gmail.com>
*
* Heavily based on pxa255_idp platform
*/
#include <common.h>
#include <command.h>
#include <serial.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa.h>
#include <asm/arch/regs-mmc.h>
#include <spi.h>
#include <asm/io.h>
#include <usb.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_SPI
void lcd_start(void);
#else
inline void lcd_start(void) {};
#endif
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
/* arch number of Z2 */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
/* Enable LCD */
lcd_start();
return 0;
}
int dram_init(void)
{
pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_USB
int board_usb_init(int index, enum usb_init_type init)
{
/* enable port 2 */
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
return 0;
}
void usb_board_stop(void)
{
}
#endif
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bis)
{
pxa_mmc_register(0);
return 0;
}
#endif
#ifdef CONFIG_CMD_SPI
struct {
unsigned char reg;
unsigned short data;
unsigned char mdelay;
} lcd_data[] = {
{ 0x07, 0x0000, 0 },
{ 0x13, 0x0000, 10 },
{ 0x11, 0x3004, 0 },
{ 0x14, 0x200F, 0 },
{ 0x10, 0x1a20, 0 },
{ 0x13, 0x0040, 50 },
{ 0x13, 0x0060, 0 },
{ 0x13, 0x0070, 200 },
{ 0x01, 0x0127, 0 },
{ 0x02, 0x0700, 0 },
{ 0x03, 0x1030, 0 },
{ 0x08, 0x0208, 0 },
{ 0x0B, 0x0620, 0 },
{ 0x0C, 0x0110, 0 },
{ 0x30, 0x0120, 0 },
{ 0x31, 0x0127, 0 },
{ 0x32, 0x0000, 0 },
{ 0x33, 0x0503, 0 },
{ 0x34, 0x0727, 0 },
{ 0x35, 0x0124, 0 },
{ 0x36, 0x0706, 0 },
{ 0x37, 0x0701, 0 },
{ 0x38, 0x0F00, 0 },
{ 0x39, 0x0F00, 0 },
{ 0x40, 0x0000, 0 },
{ 0x41, 0x0000, 0 },
{ 0x42, 0x013f, 0 },
{ 0x43, 0x0000, 0 },
{ 0x44, 0x013f, 0 },
{ 0x45, 0x0000, 0 },
{ 0x46, 0xef00, 0 },
{ 0x47, 0x013f, 0 },
{ 0x48, 0x0000, 0 },
{ 0x07, 0x0015, 30 },
{ 0x07, 0x0017, 0 },
{ 0x20, 0x0000, 0 },
{ 0x21, 0x0000, 0 },
{ 0x22, 0x0000, 0 },
};
void zipitz2_spi_sda(int set)
{
/* GPIO 13 */
if (set)
writel((1 << 13), GPSR0);
else
writel((1 << 13), GPCR0);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
writel((1 << 22), GPCR0);
else
writel((1 << 22), GPSR0);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
return !!(readl(GPLR1) & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Always valid */
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
writel((1 << 24), GPCR2);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
writel((1 << 24), GPSR2);
}
void lcd_start(void)
{
int i;
unsigned char reg[3] = { 0x74, 0x00, 0 };
unsigned char data[3] = { 0x76, 0, 0 };
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
/* Enable clock to all PWM */
writel(readl(CKEN) | 0x3, CKEN);
/* Configure PWM2 */
writel(0x4f, PWM_CTRL2);
writel(0x2ff, PWM_PWDUTY2);
writel(792, PWM_PERVAL2);
/* Toggle the reset pin to reset the LCD */
writel((1 << 19), GPSR0);
udelay(100000);
writel((1 << 19), GPCR0);
udelay(20000);
writel((1 << 19), GPSR0);
udelay(20000);
/* Program the LCD init sequence */
for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
reg[0] = 0x74;
reg[1] = 0x0;
reg[2] = lcd_data[i].reg;
spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
data[0] = 0x76;
data[1] = lcd_data[i].data >> 8;
data[2] = lcd_data[i].data & 0xff;
spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
if (lcd_data[i].mdelay)
udelay(lcd_data[i].mdelay * 1000);
}
writel((1 << 11), GPSR0);
}
#endif

3
cmd/Kconfig
View File

@ -1035,11 +1035,13 @@ config CMD_SDRAM
config CMD_SF
bool "sf"
depends on DM_SPI_FLASH || SPI_FLASH
help
SPI Flash support
config CMD_SF_TEST
bool "sf test - Allow testing of SPI flash"
depends on CMD_SF
help
Provides a way to test that SPI flash is working correctly. The
test is destructive, in that an area of SPI flash must be provided
@ -1051,6 +1053,7 @@ config CMD_SF_TEST
config CMD_SPI
bool "sspi - Command to access spi device"
depends on SPI
help
SPI utility command.

9
configs/bg0900_defconfig
View File

@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=2
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -33,13 +30,7 @@ CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_OF_LIBFDT=y

2
configs/devkit3250_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -45,7 +44,6 @@ CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LPC32XX_SSP=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

9
configs/mx28evk_auart_console_defconfig
View File

@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=2
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -44,15 +41,9 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_SST=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

9
configs/mx28evk_defconfig
View File

@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=2
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -44,15 +41,9 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_SST=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

9
configs/mx28evk_nand_defconfig
View File

@ -21,9 +21,6 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=2
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -43,15 +40,9 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_SST=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

10
configs/mx28evk_spi_defconfig
View File

@ -21,9 +21,6 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=2
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -39,19 +36,12 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_SST=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_MXS_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

6
configs/sh7752evb_defconfig
View File

@ -18,7 +18,6 @@ CONFIG_CMD_MD5SUM=y
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
@ -29,14 +28,9 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/sh7753evb_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_CMD_MD5SUM=y
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
@ -28,14 +27,9 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y

5
configs/sh7757lcr_defconfig
View File

@ -20,7 +20,6 @@ CONFIG_CMD_MD5SUM=y
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
@ -31,13 +30,9 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SH_ETHER=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_SH_SPI=y
CONFIG_USE_PRIVATE_LIBGCC=y

2
configs/work_92105_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -41,4 +40,3 @@ CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LPC32XX_SSP=y

34
configs/zipitz2_defconfig
View File

@ -1,34 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=tty0 console=ttyS2,115200 fbcon=rotate:3"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="$ "
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_CONS_INDEX=2
CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set

4
drivers/spi/Kconfig
View File

@ -322,6 +322,7 @@ endif # if DM_SPI
config SOFT_SPI
bool "Soft SPI driver"
depends on DM_SPI || (DEPRECATED && !DM_SPI)
help
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
@ -362,6 +363,7 @@ config DAVINCI_SPI
config SH_SPI
bool "SuperH SPI driver"
depends on DEPRECATED
help
Enable the SuperH SPI controller driver. This driver can be used
on various SuperH SoCs, such as SH7757.
@ -380,6 +382,7 @@ config KIRKWOOD_SPI
config LPC32XX_SSP
bool "LPC32XX SPI Driver"
depends on DEPRECATED
help
Enable support for SPI on LPC32xx
@ -391,6 +394,7 @@ config MXC_SPI
config MXS_SPI
bool "MXS SPI Driver"
depends on DEPRECATED
help
Enable the MXS SPI controller driver. This driver can be used
on the i.MX23 and i.MX28 SoCs.

2
env/Kconfig vendored
View File

@ -287,7 +287,7 @@ config ENV_IS_IN_REMOTE
config ENV_IS_IN_SPI_FLASH
bool "Environment is in SPI flash"
depends on !CHAIN_OF_TRUST
depends on !CHAIN_OF_TRUST && SPI
default y if ARMADA_XP
default y if INTEL_BAYTRAIL
default y if INTEL_BRASWELL

1
include/configs/sh7752evb.h
View File

@ -63,7 +63,6 @@
#define CONFIG_SH_MMCIF_CLK 48000000
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)

1
include/configs/sh7753evb.h
View File

@ -63,7 +63,6 @@
#define CONFIG_SH_MMCIF_CLK 48000000
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)

1
include/configs/sh7757lcr.h
View File

@ -75,7 +75,6 @@
#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)

186
include/configs/zipitz2.h
View File

@ -1,186 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Aeronix Zipit Z2 configuration file
*
* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_PREBOOT
/*
* Environment settings
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
"then " \
"source 0xa0000000; " \
"else " \
"bootm 0x50000; " \
"fi; "
#define CONFIG_TIMESTAMP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/*
* Serial Console Configuration
* STUART - the lower serial port on Colibri board
*/
#define CONFIG_STUART 1
/*
* Bootloader Components Configuration
*/
/*
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
/*
* SPI and LCD
*/
#ifdef CONFIG_CMD_SPI
#define CONFIG_SOFT_SPI
#define CONFIG_LCD_ROTATION
#define CONFIG_PXA_LCD
#define CONFIG_LMS283GF05
#define SPI_DELAY udelay(10)
#define SPI_SDA(val) zipitz2_spi_sda(val)
#define SPI_SCL(val) zipitz2_spi_scl(val)
#define SPI_READ zipitz2_spi_read()
#ifndef __ASSEMBLY__
void zipitz2_spi_sda(int);
void zipitz2_spi_scl(int);
unsigned char zipitz2_spi_read(void);
#endif
#endif
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*
* SRAM Map
*/
#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
/*
* DRAM Map
*/
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
/*
* NOR FLASH
*/
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
/*
* GPIO settings
*/
#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
#define CONFIG_SYS_GPCR0_VAL 0x00000000
#define CONFIG_SYS_GPCR1_VAL 0x00000020
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL 0x06080400
#define CONFIG_SYS_GPSR1_VAL 0x007f0000
#define CONFIG_SYS_GPSR2_VAL 0x032a0000
#define CONFIG_SYS_GPSR3_VAL 0x00000180
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Clock settings
*/
#define CONFIG_SYS_CKEN 0x00511220
#define CONFIG_SYS_CCCR 0x00000190
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
#define CONFIG_SYS_MSC2_VAL 0x0000b884
#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000001
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
#include "pxa-common.h"
#endif /* __CONFIG_H */