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mmc: stm32_sdmmc2: add dual data rate support

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To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Yann Gautier
2022-09-13 13:23:44 +02:00
committed by Jaehoon Chung
parent 12fc8efe5a
commit be1872982e
1 changed files with 4 additions and 1 deletions
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5
drivers/mmc/stm32_sdmmc2.c
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@@ -598,13 +598,16 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev)
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
if (desired && ((sys_clock > desired) ||
if (desired && (sys_clock > desired || mmc->ddr_mode ||
IS_RISING_EDGE(plat->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
if (mmc->ddr_mode)
clk |= SDMMC_CLKCR_DDR;
if (mmc->bus_width == 4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mmc->bus_width == 8)