imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDP
Since the vast majority of i.MX6 boards are migrating to SPL, this patch converts im6q_logic to SPL and enables the SDP for loading SPL and u-boot.img over USB. The Falcon mode only supports NAND flash as of now due to limited space/RAM, but all i.MX6D/Q SOM's from Logic PD have internal NAND from which to boot. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Stefano Babic
@@ -182,3 +182,144 @@ int board_late_init(void)
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6q-ddr.h>
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#include <spl.h>
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#include <linux/libfdt.h>
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0xFFFFF300, &ccm->CCGR4);
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writel(0x0F0000F3, &ccm->CCGR5);
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writel(0x00000FFF, &ccm->CCGR6);
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}
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static int mx6q_dcd_table[] = {
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MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
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MX6_IOM_GRP_DDRPKE, 0x00000000,
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MX6_IOM_DRAM_SDCLK_0, 0x00000030,
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MX6_IOM_DRAM_SDCLK_1, 0x00000030,
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MX6_IOM_DRAM_CAS, 0x00000030,
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MX6_IOM_DRAM_RAS, 0x00000030,
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MX6_IOM_GRP_ADDDS, 0x00000030,
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MX6_IOM_DRAM_RESET, 0x00000030,
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MX6_IOM_DRAM_SDBA2, 0x00000000,
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MX6_IOM_DRAM_SDODT0, 0x00000030,
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MX6_IOM_DRAM_SDODT1, 0x00000030,
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MX6_IOM_GRP_CTLDS, 0x00000030,
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MX6_IOM_DDRMODE_CTL, 0x00020000,
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MX6_IOM_DRAM_SDQS0, 0x00000030,
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MX6_IOM_DRAM_SDQS1, 0x00000030,
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MX6_IOM_DRAM_SDQS2, 0x00000030,
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MX6_IOM_DRAM_SDQS3, 0x00000030,
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MX6_IOM_GRP_DDRMODE, 0x00020000,
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MX6_IOM_GRP_B0DS, 0x00000030,
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MX6_IOM_GRP_B1DS, 0x00000030,
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MX6_IOM_GRP_B2DS, 0x00000030,
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MX6_IOM_GRP_B3DS, 0x00000030,
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MX6_IOM_DRAM_DQM0, 0x00000030,
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MX6_IOM_DRAM_DQM1, 0x00000030,
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MX6_IOM_DRAM_DQM2, 0x00000030,
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MX6_IOM_DRAM_DQM3, 0x00000030,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
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MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
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MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
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MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
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MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
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MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
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MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
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MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
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MX6_MMDC_P0_MPMUR0, 0x00000800,
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MX6_MMDC_P0_MDPDC, 0x00020036,
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MX6_MMDC_P0_MDOTC, 0x09444040,
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MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
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MX6_MMDC_P0_MDCFG1, 0xFF328F64,
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MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
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MX6_MMDC_P0_MDMISC, 0x00011740,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MDRWD, 0x000026D2,
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MX6_MMDC_P0_MDOR, 0x00BE1023,
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MX6_MMDC_P0_MDASP, 0x00000047,
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MX6_MMDC_P0_MDCTL, 0x85190000,
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MX6_MMDC_P0_MDSCR, 0x00888032,
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MX6_MMDC_P0_MDSCR, 0x00008033,
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MX6_MMDC_P0_MDSCR, 0x00008031,
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MX6_MMDC_P0_MDSCR, 0x19408030,
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MX6_MMDC_P0_MDSCR, 0x04008040,
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MX6_MMDC_P0_MDREF, 0x00007800,
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MX6_MMDC_P0_MPODTCTRL, 0x00000007,
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MX6_MMDC_P0_MDPDC, 0x00025576,
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MX6_MMDC_P0_MAPSR, 0x00011006,
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MX6_MMDC_P0_MDSCR, 0x00000000,
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/* enable AXI cache for VDOA/VPU/IPU */
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MX6_IOMUXC_GPR4, 0xF00000CF,
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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MX6_IOMUXC_GPR6, 0x007F007F,
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MX6_IOMUXC_GPR7, 0x007F007F,
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};
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static void ddr_init(int *table, int size)
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{
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int i;
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for (i = 0; i < size / 2 ; i++)
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writel(table[2 * i + 1], table[2 * i]);
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}
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static void spl_dram_init(void)
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{
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if (is_mx6dq())
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ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
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}
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void board_init_f(ulong dummy)
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{
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/* DDR initialization */
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spl_dram_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* iomux and setup of uart and NAND pins */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif
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@@ -1,111 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Logic PD, Inc.
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* Adam Ford <aford173@gmail.com>
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#include <asm/mach-imx/imximage.cfg>
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/* image version */
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IMAGE_VERSION 2
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BOOT_OFFSET FLASH_OFFSET_STANDARD
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch-mx6/mx6-ddr.h"
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#include "asm/arch-mx6/iomux.h"
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#include "asm/arch-mx6/crm_regs.h"
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
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DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
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DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
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DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
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DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0xFFFFF300
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DATA 4, CCM_CCGR5, 0x0F0000F3
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DATA 4, CCM_CCGR6, 0x00000FFF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 MX6_IOMUXC_GPR6 0x007F007F
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DATA 4 MX6_IOMUXC_GPR7 0x007F007F
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