imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDP
Since the vast majority of i.MX6 boards are migrating to SPL, this patch converts im6q_logic to SPL and enables the SDP for loading SPL and u-boot.img over USB. The Falcon mode only supports NAND flash as of now due to limited space/RAM, but all i.MX6D/Q SOM's from Logic PD have internal NAND from which to boot. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Stefano Babic
parent
0481bef035
commit
bbbb50f9fd
@ -205,6 +205,8 @@ config TARGET_MX6CUBOXI
|
||||
|
||||
config TARGET_MX6LOGICPD
|
||||
bool "Logic PD i.MX6 SOM"
|
||||
select MX6Q
|
||||
select SUPPORT_SPL
|
||||
select BOARD_EARLY_INIT_F
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
@ -213,7 +215,6 @@ config TARGET_MX6LOGICPD
|
||||
select DM_I2C
|
||||
select DM_MMC
|
||||
select DM_PMIC
|
||||
select DM_REGULATOR
|
||||
select OF_CONTROL
|
||||
|
||||
config TARGET_MX6MEMCAL
|
||||
|
||||
@ -182,3 +182,144 @@ int board_late_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <asm/arch/mx6q-ddr.h>
|
||||
#include <spl.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0x00C03F3F, &ccm->CCGR0);
|
||||
writel(0x0030FC03, &ccm->CCGR1);
|
||||
writel(0x0FFFC000, &ccm->CCGR2);
|
||||
writel(0x3FF00000, &ccm->CCGR3);
|
||||
writel(0xFFFFF300, &ccm->CCGR4);
|
||||
writel(0x0F0000F3, &ccm->CCGR5);
|
||||
writel(0x00000FFF, &ccm->CCGR6);
|
||||
}
|
||||
|
||||
static int mx6q_dcd_table[] = {
|
||||
MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
|
||||
MX6_IOM_GRP_DDRPKE, 0x00000000,
|
||||
MX6_IOM_DRAM_SDCLK_0, 0x00000030,
|
||||
MX6_IOM_DRAM_SDCLK_1, 0x00000030,
|
||||
MX6_IOM_DRAM_CAS, 0x00000030,
|
||||
MX6_IOM_DRAM_RAS, 0x00000030,
|
||||
MX6_IOM_GRP_ADDDS, 0x00000030,
|
||||
MX6_IOM_DRAM_RESET, 0x00000030,
|
||||
MX6_IOM_DRAM_SDBA2, 0x00000000,
|
||||
MX6_IOM_DRAM_SDODT0, 0x00000030,
|
||||
MX6_IOM_DRAM_SDODT1, 0x00000030,
|
||||
MX6_IOM_GRP_CTLDS, 0x00000030,
|
||||
MX6_IOM_DDRMODE_CTL, 0x00020000,
|
||||
MX6_IOM_DRAM_SDQS0, 0x00000030,
|
||||
MX6_IOM_DRAM_SDQS1, 0x00000030,
|
||||
MX6_IOM_DRAM_SDQS2, 0x00000030,
|
||||
MX6_IOM_DRAM_SDQS3, 0x00000030,
|
||||
MX6_IOM_GRP_DDRMODE, 0x00020000,
|
||||
MX6_IOM_GRP_B0DS, 0x00000030,
|
||||
MX6_IOM_GRP_B1DS, 0x00000030,
|
||||
MX6_IOM_GRP_B2DS, 0x00000030,
|
||||
MX6_IOM_GRP_B3DS, 0x00000030,
|
||||
MX6_IOM_DRAM_DQM0, 0x00000030,
|
||||
MX6_IOM_DRAM_DQM1, 0x00000030,
|
||||
MX6_IOM_DRAM_DQM2, 0x00000030,
|
||||
MX6_IOM_DRAM_DQM3, 0x00000030,
|
||||
MX6_MMDC_P0_MDSCR, 0x00008000,
|
||||
MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
|
||||
MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
|
||||
MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
|
||||
MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
|
||||
MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
|
||||
MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
|
||||
MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
|
||||
MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
|
||||
MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
|
||||
MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
|
||||
MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
|
||||
MX6_MMDC_P0_MPMUR0, 0x00000800,
|
||||
MX6_MMDC_P0_MDPDC, 0x00020036,
|
||||
MX6_MMDC_P0_MDOTC, 0x09444040,
|
||||
MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
|
||||
MX6_MMDC_P0_MDCFG1, 0xFF328F64,
|
||||
MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
|
||||
MX6_MMDC_P0_MDMISC, 0x00011740,
|
||||
MX6_MMDC_P0_MDSCR, 0x00008000,
|
||||
MX6_MMDC_P0_MDRWD, 0x000026D2,
|
||||
MX6_MMDC_P0_MDOR, 0x00BE1023,
|
||||
MX6_MMDC_P0_MDASP, 0x00000047,
|
||||
MX6_MMDC_P0_MDCTL, 0x85190000,
|
||||
MX6_MMDC_P0_MDSCR, 0x00888032,
|
||||
MX6_MMDC_P0_MDSCR, 0x00008033,
|
||||
MX6_MMDC_P0_MDSCR, 0x00008031,
|
||||
MX6_MMDC_P0_MDSCR, 0x19408030,
|
||||
MX6_MMDC_P0_MDSCR, 0x04008040,
|
||||
MX6_MMDC_P0_MDREF, 0x00007800,
|
||||
MX6_MMDC_P0_MPODTCTRL, 0x00000007,
|
||||
MX6_MMDC_P0_MDPDC, 0x00025576,
|
||||
MX6_MMDC_P0_MAPSR, 0x00011006,
|
||||
MX6_MMDC_P0_MDSCR, 0x00000000,
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
|
||||
MX6_IOMUXC_GPR4, 0xF00000CF,
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
MX6_IOMUXC_GPR6, 0x007F007F,
|
||||
MX6_IOMUXC_GPR7, 0x007F007F,
|
||||
};
|
||||
|
||||
static void ddr_init(int *table, int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < size / 2 ; i++)
|
||||
writel(table[2 * i + 1], table[2 * i]);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
if (is_mx6dq())
|
||||
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
gpr_init();
|
||||
|
||||
/* iomux and setup of uart and NAND pins */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,111 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2017 Logic PD, Inc.
|
||||
* Adam Ford <aford173@gmail.com>
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#include <asm/mach-imx/imximage.cfg>
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
BOOT_OFFSET FLASH_OFFSET_STANDARD
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch-mx6/mx6-ddr.h"
|
||||
#include "asm/arch-mx6/iomux.h"
|
||||
#include "asm/arch-mx6/crm_regs.h"
|
||||
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4, CCM_CCGR0, 0x00C03F3F
|
||||
DATA 4, CCM_CCGR1, 0x0030FC03
|
||||
DATA 4, CCM_CCGR2, 0x0FFFC000
|
||||
DATA 4, CCM_CCGR3, 0x3FF00000
|
||||
DATA 4, CCM_CCGR4, 0xFFFFF300
|
||||
DATA 4, CCM_CCGR5, 0x0F0000F3
|
||||
DATA 4, CCM_CCGR6, 0x00000FFF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4 MX6_IOMUXC_GPR6 0x007F007F
|
||||
DATA 4 MX6_IOMUXC_GPR7 0x007F007F
|
||||
@ -1,39 +1,74 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x17800000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_MX6LOGICPD=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_DMA_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SYS_PROMPT="i.MX6 Logic # "
|
||||
CONFIG_CMD_SPL=y
|
||||
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND_TRIMFFS=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_LED is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_PCF8575_GPIO=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_MXS=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DM_PMIC_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
|
||||
@ -11,6 +11,10 @@
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#define CONSOLE_DEV "ttymxc0"
|
||||
|
||||
#ifdef CONFIG_SPL
|
||||
#include "imx6_spl.h"
|
||||
#endif
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
@ -132,7 +136,7 @@
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Environment organization */
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_SIZE (1024 * 1024)
|
||||
#define CONFIG_ENV_OFFSET 0x400000
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
|
||||
@ -143,7 +147,7 @@
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
|
||||
/* MTD device */
|
||||
# define CONFIG_MTD_DEVICE
|
||||
# define CONFIG_MTD_PARTITIONS
|
||||
@ -153,4 +157,22 @@
|
||||
/* EEPROM contains serial no, MAC addr and other Logic PD info */
|
||||
#define CONFIG_I2C_EEPROM
|
||||
|
||||
/* USB Configs */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
|
||||
#endif
|
||||
|
||||
/* Falcon Mode */
|
||||
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
|
||||
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x15000000
|
||||
|
||||
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
|
||||
|
||||
#endif /* __IMX6LOGIC_CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user