mips: octeon: Add misc cvmx-* header files
Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
committed by
Stefan Roese
Stefan Roese
parent
46eb29201c
commit
ba5eb2327b
45
arch/mips/mach-octeon/include/mach/cvmx-agl.h
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45
arch/mips/mach-octeon/include/mach/cvmx-agl.h
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@@ -0,0 +1,45 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Functions for AGL (RGMII) commong initialization, configuration.
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*/
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#ifndef __CVMX_AGL_H__
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#define __CVMX_AGL_H__
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/*
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* @param port to enable
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_agl_enable(int port);
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cvmx_helper_link_info_t cvmx_agl_link_get(int port);
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/*
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* Set MII/RGMII link based on mode.
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*
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* @param port interface port to set the link.
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* @param link_info Link status
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*
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* @return 0 on success and 1 on failure
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*/
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int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info);
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/**
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* Disables the sending of flow control (pause) frames on the specified
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* AGL (RGMII) port(s).
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*
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* @param interface Which interface (0 or 1)
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* @param port_mask Mask (4bits) of which ports on the interface to disable
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* backpressure on.
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* 1 => disable backpressure
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* 0 => enable backpressure
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*
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* @return 0 on success
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* -1 on error
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*/
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int cvmx_agl_set_backpressure_override(u32 interface, uint32_t port_mask);
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#endif /* __CVMX_AGL_H__ */
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128
arch/mips/mach-octeon/include/mach/cvmx-config.h
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128
arch/mips/mach-octeon/include/mach/cvmx-config.h
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@@ -0,0 +1,128 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*/
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#ifndef __CVMX_CONFIG_H__
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#define __CVMX_CONFIG_H__
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/************************* Config Specific Defines ************************/
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#define CVMX_LLM_NUM_PORTS 1
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/**< PKO queues per port for interface 0 (ports 0-15) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
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/**< PKO queues per port for interface 1 (ports 16-31) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
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/**< PKO queues per port for interface 4 (AGL) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4 1
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/**< Limit on the number of PKO ports enabled for interface 0 */
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#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
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/**< Limit on the number of PKO ports enabled for interface 1 */
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#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
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/**< PKO queues per port for PCI (ports 32-35) */
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#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
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/**< PKO queues per port for Loop devices (ports 36-39) */
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#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
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/**< PKO queues per port for SRIO0 devices (ports 40-41) */
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#define CVMX_PKO_QUEUES_PER_PORT_SRIO0 1
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/**< PKO queues per port for SRIO1 devices (ports 42-43) */
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#define CVMX_PKO_QUEUES_PER_PORT_SRIO1 1
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/************************* FPA allocation *********************************/
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/* Pool sizes in bytes, must be multiple of a cache line */
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#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_3_SIZE (2 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_6_SIZE (8 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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/* Pools in use */
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/**< Packet buffers */
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#define CVMX_FPA_PACKET_POOL (0)
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#ifndef CVMX_FPA_PACKET_POOL_SIZE
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#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
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#endif
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/**< Work queue entries */
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#define CVMX_FPA_WQE_POOL (1)
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#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
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/**< PKO queue command buffers */
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#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
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#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
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/**< BCH queue command buffers */
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#define CVMX_FPA_BCH_POOL (6)
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#define CVMX_FPA_BCH_POOL_SIZE CVMX_FPA_POOL6_SIZE
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/************************* FAU allocation ********************************/
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/* The fetch and add registers are allocated here. They are arranged
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* in order of descending size so that all alignment constraints are
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* automatically met.
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* The enums are linked so that the following enum continues allocating
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* where the previous one left off, so the numbering within each
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* enum always starts with zero. The macros take care of the address
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* increment size, so the values entered always increase by 1.
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* FAU registers are accessed with byte addresses.
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*/
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#define CVMX_FAU_REG_64_ADDR(x) (((x) << 3) + CVMX_FAU_REG_64_START)
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typedef enum {
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CVMX_FAU_REG_64_START = 0,
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/**< FAU registers for the position in PKO command buffers */
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CVMX_FAU_REG_OQ_ADDR_INDEX = CVMX_FAU_REG_64_ADDR(0),
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/* Array of 36 */
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CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(36),
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} cvmx_fau_reg_64_t;
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#define CVMX_FAU_REG_32_ADDR(x) (((x) << 2) + CVMX_FAU_REG_32_START)
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typedef enum {
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CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
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CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
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} cvmx_fau_reg_32_t;
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#define CVMX_FAU_REG_16_ADDR(x) (((x) << 1) + CVMX_FAU_REG_16_START)
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typedef enum {
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CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
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CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
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} cvmx_fau_reg_16_t;
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#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
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typedef enum {
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CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
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CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
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} cvmx_fau_reg_8_t;
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/* The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first available
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* FAU address that is not allocated in cvmx-config.h. This is 64 bit aligned.
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*/
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#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
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#define CVMX_FAU_REG_END (2048)
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/********************** scratch memory allocation *************************/
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/* Scratchpad memory allocation. Note that these are byte memory addresses.
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* Some uses of scratchpad (IOBDMA for example) require the use of 8-byte
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* aligned addresses, so proper alignment needs to be taken into account.
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*/
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/**< Pre allocation for PKO queue command buffers */
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#define CVMX_SCR_OQ_BUF_PRE_ALLOC (0)
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/**< Generic scratch iobdma area */
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#define CVMX_SCR_SCRATCH (8)
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/**< First location available after cvmx-config.h allocated region. */
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#define CVMX_SCR_REG_AVAIL_BASE (16)
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#endif /* __CVMX_CONFIG_H__ */
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581
arch/mips/mach-octeon/include/mach/cvmx-fau.h
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581
arch/mips/mach-octeon/include/mach/cvmx-fau.h
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@@ -0,0 +1,581 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Interface to the hardware Fetch and Add Unit.
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*/
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#ifndef __CVMX_FAU_H__
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#define __CVMX_FAU_H__
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extern u8 *cvmx_fau_regs_ptr;
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/**
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* Initializes fau, on devices with FAU hw this is a noop.
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*/
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int cvmx_fau_init(void);
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/**
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* Return the location of emulated FAU register
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*/
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static inline u8 *__cvmx_fau_sw_addr(int reg)
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{
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if (cvmx_unlikely(!cvmx_fau_regs_ptr))
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cvmx_fau_init();
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return (cvmx_fau_regs_ptr + reg);
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}
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/**
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* Perform an atomic 64 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg64_t reg,
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int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add64(reg, value);
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return __atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 32 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg32_t reg,
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int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add32(reg, value);
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reg ^= SWIZZLE_32;
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return __atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 16 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg16_t reg,
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int16_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add16(reg, value);
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reg ^= SWIZZLE_16;
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return __atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 8 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_fetch_and_add8(reg, value);
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reg ^= SWIZZLE_8;
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return __atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST);
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}
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/**
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* Perform an atomic 64 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait64_t
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cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg, int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add64(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait64_t){ 1, 0 };
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}
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/**
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* Perform an atomic 32 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait32_t
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cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg, int32_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add32(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait32_t){ 1, 0 };
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}
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/**
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* Perform an atomic 16 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait16_t
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cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg, int16_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add16(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait16_t){ 1, 0 };
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}
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/**
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* Perform an atomic 8 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait8_t
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cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU))
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return cvmx_hwfau_tagwait_fetch_and_add8(reg, value);
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/* not implemented yet.*/
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return (cvmx_fau_tagwait8_t){ 1, 0 };
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}
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/**
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* Perform an async atomic 64 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, int64_t value)
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{
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if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
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cvmx_hwfau_async_fetch_and_add64(scraddr, reg, value);
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return;
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}
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cvmx_scratch_write64(
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scraddr,
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__atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
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value, __ATOMIC_SEQ_CST));
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}
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/**
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* Perform an async atomic 32 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void
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cvmx_fau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, int32_t value)
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{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_fetch_and_add32(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 16 bit add. The old value is
|
||||
* placed in the scratch memory at byte address scraddr.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 2 for 16 bit access.
|
||||
* @param value Signed value to add.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void
|
||||
cvmx_fau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, int16_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_fetch_and_add16(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 8 bit add. The old value is
|
||||
* placed in the scratch memory at byte address scraddr.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* @param value Signed value to add.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void
|
||||
cvmx_fau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_fetch_and_add8(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 64 bit add after the current tag
|
||||
* switch completes.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
||||
* the value of the register before the update will be
|
||||
* returned
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 8 for 64 bit access.
|
||||
* @param value Signed value to add.
|
||||
* Note: Only the low 22 bits are available.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void cvmx_fau_async_tagwait_fetch_and_add64(u64 scraddr,
|
||||
cvmx_fau_reg64_t reg,
|
||||
int64_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_tagwait_fetch_and_add64(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Broken. Where is the tag wait? */
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 32 bit add after the current tag
|
||||
* switch completes.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
||||
* the value of the register before the update will be
|
||||
* returned
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 4 for 32 bit access.
|
||||
* @param value Signed value to add.
|
||||
* Note: Only the low 22 bits are available.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void cvmx_fau_async_tagwait_fetch_and_add32(u64 scraddr,
|
||||
cvmx_fau_reg32_t reg,
|
||||
int32_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_tagwait_fetch_and_add32(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
/* Broken. Where is the tag wait? */
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 16 bit add after the current tag
|
||||
* switch completes.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
||||
* the value of the register before the update will be
|
||||
* returned
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 2 for 16 bit access.
|
||||
* @param value Signed value to add.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void cvmx_fau_async_tagwait_fetch_and_add16(u64 scraddr,
|
||||
cvmx_fau_reg16_t reg,
|
||||
int16_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_tagwait_fetch_and_add16(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
/* Broken. Where is the tag wait? */
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an async atomic 8 bit add after the current tag
|
||||
* switch completes.
|
||||
*
|
||||
* @param scraddr Scratch memory byte address to put response in.
|
||||
* Must be 8 byte aligned.
|
||||
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
||||
* the value of the register before the update will be
|
||||
* returned
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* @param value Signed value to add.
|
||||
* @return Placed in the scratch pad register
|
||||
*/
|
||||
static inline void cvmx_fau_async_tagwait_fetch_and_add8(u64 scraddr,
|
||||
cvmx_fau_reg8_t reg,
|
||||
int8_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_async_tagwait_fetch_and_add8(scraddr, reg, value);
|
||||
return;
|
||||
}
|
||||
/* Broken. Where is the tag wait? */
|
||||
cvmx_scratch_write64(
|
||||
scraddr,
|
||||
__atomic_fetch_add(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)),
|
||||
value, __ATOMIC_SEQ_CST));
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 64 bit add
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 8 for 64 bit access.
|
||||
* @param value Signed value to add.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_add64(cvmx_fau_reg64_t reg, int64_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_add64(reg, value);
|
||||
return;
|
||||
}
|
||||
/* Ignored fetch values should be optimized away */
|
||||
__atomic_add_fetch(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 32 bit add
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 4 for 32 bit access.
|
||||
* @param value Signed value to add.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_add32(cvmx_fau_reg32_t reg, int32_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_add32(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_32;
|
||||
/* Ignored fetch values should be optimized away */
|
||||
__atomic_add_fetch(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 16 bit add
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 2 for 16 bit access.
|
||||
* @param value Signed value to add.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_add16(cvmx_fau_reg16_t reg, int16_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_add16(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_16;
|
||||
/* Ignored fetch values should be optimized away */
|
||||
__atomic_add_fetch(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 8 bit add
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* @param value Signed value to add.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_add8(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_8;
|
||||
/* Ignored fetch values should be optimized away */
|
||||
__atomic_add_fetch(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 64 bit write
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 8 for 64 bit access.
|
||||
* @param value Signed value to write.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_write64(cvmx_fau_reg64_t reg, int64_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_write64(reg, value);
|
||||
return;
|
||||
}
|
||||
__atomic_store_n(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 32 bit write
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 4 for 32 bit access.
|
||||
* @param value Signed value to write.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_write32(cvmx_fau_reg32_t reg, int32_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_write32(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_32;
|
||||
__atomic_store_n(CASTPTR(int32_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 16 bit write
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* - Step by 2 for 16 bit access.
|
||||
* @param value Signed value to write.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg16_t reg, int16_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_write16(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_16;
|
||||
__atomic_store_n(CASTPTR(int16_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an atomic 8 bit write
|
||||
*
|
||||
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
||||
* @param value Signed value to write.
|
||||
*/
|
||||
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value)
|
||||
{
|
||||
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
|
||||
cvmx_hwfau_atomic_write8(reg, value);
|
||||
return;
|
||||
}
|
||||
reg ^= SWIZZLE_8;
|
||||
__atomic_store_n(CASTPTR(int8_t, __cvmx_fau_sw_addr(reg)), value,
|
||||
__ATOMIC_SEQ_CST);
|
||||
}
|
||||
|
||||
/** Allocates 64bit FAU register.
|
||||
* @param reserve base address to reserve
|
||||
* @return value is the base address of allocated FAU register
|
||||
*/
|
||||
int cvmx_fau64_alloc(int reserve);
|
||||
|
||||
/** Allocates 32bit FAU register.
|
||||
* @param reserve base address to reserve
|
||||
* @return value is the base address of allocated FAU register
|
||||
*/
|
||||
int cvmx_fau32_alloc(int reserve);
|
||||
|
||||
/** Allocates 16bit FAU register.
|
||||
* @param reserve base address to reserve
|
||||
* @return value is the base address of allocated FAU register
|
||||
*/
|
||||
int cvmx_fau16_alloc(int reserve);
|
||||
|
||||
/** Allocates 8bit FAU register.
|
||||
* @param reserve base address to reserve
|
||||
* @return value is the base address of allocated FAU register
|
||||
*/
|
||||
int cvmx_fau8_alloc(int reserve);
|
||||
|
||||
/** Frees the specified FAU register.
|
||||
* @param address base address of register to release.
|
||||
* @return 0 on success; -1 on failure
|
||||
*/
|
||||
int cvmx_fau_free(int address);
|
||||
|
||||
/** Display the fau registers array
|
||||
*/
|
||||
void cvmx_fau_show(void);
|
||||
|
||||
#endif /* __CVMX_FAU_H__ */
|
||||
516
arch/mips/mach-octeon/include/mach/cvmx-mdio.h
Normal file
516
arch/mips/mach-octeon/include/mach/cvmx-mdio.h
Normal file
@@ -0,0 +1,516 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018-2022 Marvell International Ltd.
|
||||
*
|
||||
* Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
|
||||
* clause 22 and clause 45 operations.
|
||||
*/
|
||||
|
||||
#ifndef __CVMX_MIO_H__
|
||||
#define __CVMX_MIO_H__
|
||||
|
||||
/**
|
||||
* PHY register 0 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_CONTROL 0
|
||||
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 reset : 1;
|
||||
u16 loopback : 1;
|
||||
u16 speed_lsb : 1;
|
||||
u16 autoneg_enable : 1;
|
||||
u16 power_down : 1;
|
||||
u16 isolate : 1;
|
||||
u16 restart_autoneg : 1;
|
||||
u16 duplex : 1;
|
||||
u16 collision_test : 1;
|
||||
u16 speed_msb : 1;
|
||||
u16 unidirectional_enable : 1;
|
||||
u16 reserved_0_4 : 5;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_control_t;
|
||||
|
||||
/**
|
||||
* PHY register 1 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_STATUS 1
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 capable_100base_t4 : 1;
|
||||
u16 capable_100base_x_full : 1;
|
||||
u16 capable_100base_x_half : 1;
|
||||
u16 capable_10_full : 1;
|
||||
u16 capable_10_half : 1;
|
||||
u16 capable_100base_t2_full : 1;
|
||||
u16 capable_100base_t2_half : 1;
|
||||
u16 capable_extended_status : 1;
|
||||
u16 capable_unidirectional : 1;
|
||||
u16 capable_mf_preamble_suppression : 1;
|
||||
u16 autoneg_complete : 1;
|
||||
u16 remote_fault : 1;
|
||||
u16 capable_autoneg : 1;
|
||||
u16 link_status : 1;
|
||||
u16 jabber_detect : 1;
|
||||
u16 capable_extended_registers : 1;
|
||||
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_status_t;
|
||||
|
||||
/**
|
||||
* PHY register 2 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_ID1 2
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 oui_bits_3_18;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_id1_t;
|
||||
|
||||
/**
|
||||
* PHY register 3 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_ID2 3
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 oui_bits_19_24 : 6;
|
||||
u16 model : 6;
|
||||
u16 revision : 4;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_id2_t;
|
||||
|
||||
/**
|
||||
* PHY register 4 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 next_page : 1;
|
||||
u16 reserved_14 : 1;
|
||||
u16 remote_fault : 1;
|
||||
u16 reserved_12 : 1;
|
||||
u16 asymmetric_pause : 1;
|
||||
u16 pause : 1;
|
||||
u16 advert_100base_t4 : 1;
|
||||
u16 advert_100base_tx_full : 1;
|
||||
u16 advert_100base_tx_half : 1;
|
||||
u16 advert_10base_tx_full : 1;
|
||||
u16 advert_10base_tx_half : 1;
|
||||
u16 selector : 5;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_autoneg_adver_t;
|
||||
|
||||
/**
|
||||
* PHY register 5 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 next_page : 1;
|
||||
u16 ack : 1;
|
||||
u16 remote_fault : 1;
|
||||
u16 reserved_12 : 1;
|
||||
u16 asymmetric_pause : 1;
|
||||
u16 pause : 1;
|
||||
u16 advert_100base_t4 : 1;
|
||||
u16 advert_100base_tx_full : 1;
|
||||
u16 advert_100base_tx_half : 1;
|
||||
u16 advert_10base_tx_full : 1;
|
||||
u16 advert_10base_tx_half : 1;
|
||||
u16 selector : 5;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_link_partner_ability_t;
|
||||
|
||||
/**
|
||||
* PHY register 6 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 reserved_5_15 : 11;
|
||||
u16 parallel_detection_fault : 1;
|
||||
u16 link_partner_next_page_capable : 1;
|
||||
u16 local_next_page_capable : 1;
|
||||
u16 page_received : 1;
|
||||
u16 link_partner_autoneg_capable : 1;
|
||||
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_autoneg_expansion_t;
|
||||
|
||||
/**
|
||||
* PHY register 9 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 test_mode : 3;
|
||||
u16 manual_master_slave : 1;
|
||||
u16 master : 1;
|
||||
u16 port_type : 1;
|
||||
u16 advert_1000base_t_full : 1;
|
||||
u16 advert_1000base_t_half : 1;
|
||||
u16 reserved_0_7 : 8;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_control_1000_t;
|
||||
|
||||
/**
|
||||
* PHY register 10 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_STATUS_1000 10
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 master_slave_fault : 1;
|
||||
u16 is_master : 1;
|
||||
u16 local_receiver_ok : 1;
|
||||
u16 remote_receiver_ok : 1;
|
||||
u16 remote_capable_1000base_t_full : 1;
|
||||
u16 remote_capable_1000base_t_half : 1;
|
||||
u16 reserved_8_9 : 2;
|
||||
u16 idle_error_count : 8;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_status_1000_t;
|
||||
|
||||
/**
|
||||
* PHY register 15 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 capable_1000base_x_full : 1;
|
||||
u16 capable_1000base_x_half : 1;
|
||||
u16 capable_1000base_t_full : 1;
|
||||
u16 capable_1000base_t_half : 1;
|
||||
u16 reserved_0_11 : 12;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_extended_status_t;
|
||||
|
||||
/**
|
||||
* PHY register 13 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 function : 2;
|
||||
u16 reserved_5_13 : 9;
|
||||
u16 devad : 5;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_mmd_control_t;
|
||||
|
||||
/**
|
||||
* PHY register 14 from the 802.3 spec
|
||||
*/
|
||||
#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
|
||||
typedef union {
|
||||
u16 u16;
|
||||
struct {
|
||||
u16 address_data : 16;
|
||||
} s;
|
||||
} cvmx_mdio_phy_reg_mmd_address_data_t;
|
||||
|
||||
/* Operating request encodings. */
|
||||
#define MDIO_CLAUSE_22_WRITE 0
|
||||
#define MDIO_CLAUSE_22_READ 1
|
||||
|
||||
#define MDIO_CLAUSE_45_ADDRESS 0
|
||||
#define MDIO_CLAUSE_45_WRITE 1
|
||||
#define MDIO_CLAUSE_45_READ_INC 2
|
||||
#define MDIO_CLAUSE_45_READ 3
|
||||
|
||||
/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
|
||||
#define CVMX_MMD_DEVICE_PMA_PMD 1
|
||||
#define CVMX_MMD_DEVICE_WIS 2
|
||||
#define CVMX_MMD_DEVICE_PCS 3
|
||||
#define CVMX_MMD_DEVICE_PHY_XS 4
|
||||
#define CVMX_MMD_DEVICE_DTS_XS 5
|
||||
#define CVMX_MMD_DEVICE_TC 6
|
||||
#define CVMX_MMD_DEVICE_CL22_EXT 29
|
||||
#define CVMX_MMD_DEVICE_VENDOR_1 30
|
||||
#define CVMX_MMD_DEVICE_VENDOR_2 31
|
||||
|
||||
#define CVMX_MDIO_TIMEOUT 100000 /* 100 millisec */
|
||||
|
||||
static inline int cvmx_mdio_bus_id_to_node(int bus_id)
|
||||
{
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN78XX))
|
||||
return (bus_id >> 2) & CVMX_NODE_MASK;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int cvmx_mdio_bus_id_to_bus(int bus_id)
|
||||
{
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN78XX))
|
||||
return bus_id & 3;
|
||||
else
|
||||
return bus_id;
|
||||
}
|
||||
|
||||
/* Helper function to put MDIO interface into clause 45 mode */
|
||||
static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
|
||||
{
|
||||
cvmx_smix_clk_t smi_clk;
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
|
||||
/* Put bus into clause 45 mode */
|
||||
smi_clk.u64 = csr_rd_node(node, CVMX_SMIX_CLK(bus));
|
||||
smi_clk.s.mode = 1;
|
||||
smi_clk.s.preamble = 1;
|
||||
csr_wr_node(node, CVMX_SMIX_CLK(bus), smi_clk.u64);
|
||||
}
|
||||
|
||||
/* Helper function to put MDIO interface into clause 22 mode */
|
||||
static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
|
||||
{
|
||||
cvmx_smix_clk_t smi_clk;
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
|
||||
/* Put bus into clause 22 mode */
|
||||
smi_clk.u64 = csr_rd_node(node, CVMX_SMIX_CLK(bus));
|
||||
smi_clk.s.mode = 0;
|
||||
csr_wr_node(node, CVMX_SMIX_CLK(bus), smi_clk.u64);
|
||||
}
|
||||
|
||||
/**
|
||||
* @INTERNAL
|
||||
* Function to read SMIX_RD_DAT and check for timeouts. This
|
||||
* code sequence is done fairly often, so put in one spot.
|
||||
*
|
||||
* @param bus_id SMI/MDIO bus to read
|
||||
*
|
||||
* @return Value of SMIX_RD_DAT. pending will be set on
|
||||
* a timeout.
|
||||
*/
|
||||
static inline cvmx_smix_rd_dat_t __cvmx_mdio_read_rd_dat(int bus_id)
|
||||
{
|
||||
cvmx_smix_rd_dat_t smi_rd;
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
u64 done;
|
||||
|
||||
done = get_timer(0);
|
||||
|
||||
do {
|
||||
mdelay(1);
|
||||
smi_rd.u64 = csr_rd_node(node, CVMX_SMIX_RD_DAT(bus));
|
||||
if (get_timer(done) > (CVMX_MDIO_TIMEOUT / 1000))
|
||||
break;
|
||||
} while (smi_rd.s.pending);
|
||||
|
||||
return smi_rd;
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an MII read. This function is used to read PHY
|
||||
* registers controlling auto negotiation.
|
||||
*
|
||||
* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
|
||||
* support multiple busses.
|
||||
* @param phy_id The MII phy id
|
||||
* @param location Register location to read
|
||||
*
|
||||
* @return Result from the read or -1 on failure
|
||||
*/
|
||||
static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
|
||||
{
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
cvmx_smix_cmd_t smi_cmd;
|
||||
cvmx_smix_rd_dat_t smi_rd;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
|
||||
__cvmx_mdio_set_clause22_mode(bus_id);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = location;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
|
||||
if (smi_rd.s.val)
|
||||
return smi_rd.s.dat;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an MII write. This function is used to write PHY
|
||||
* registers controlling auto negotiation.
|
||||
*
|
||||
* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
|
||||
* support multiple busses.
|
||||
* @param phy_id The MII phy id
|
||||
* @param location Register location to write
|
||||
* @param val Value to write
|
||||
*
|
||||
* @return -1 on error
|
||||
* 0 on success
|
||||
*/
|
||||
static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
|
||||
{
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
cvmx_smix_cmd_t smi_cmd;
|
||||
cvmx_smix_wr_dat_t smi_wr;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
|
||||
__cvmx_mdio_set_clause22_mode(bus_id);
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = val;
|
||||
csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = location;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
||||
cvmx_smix_wr_dat_t, pending, ==, 0,
|
||||
CVMX_MDIO_TIMEOUT))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY
|
||||
* registers controlling auto negotiation.
|
||||
*
|
||||
* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
|
||||
* support multiple busses.
|
||||
* @param phy_id The MII phy id
|
||||
* @param device MDIO Manageable Device (MMD) id
|
||||
* @param location Register location to read
|
||||
*
|
||||
* @return Result from the read or -1 on failure
|
||||
*/
|
||||
|
||||
static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
|
||||
int location)
|
||||
{
|
||||
cvmx_smix_cmd_t smi_cmd;
|
||||
cvmx_smix_rd_dat_t smi_rd;
|
||||
cvmx_smix_wr_dat_t smi_wr;
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
|
||||
if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
|
||||
return -1;
|
||||
|
||||
__cvmx_mdio_set_clause45_mode(bus_id);
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = location;
|
||||
csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = device;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
||||
cvmx_smix_wr_dat_t, pending, ==, 0,
|
||||
CVMX_MDIO_TIMEOUT)) {
|
||||
debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(address)\n",
|
||||
bus_id, phy_id, device, location);
|
||||
return -1;
|
||||
}
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = device;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
|
||||
if (smi_rd.s.pending) {
|
||||
debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(data)\n",
|
||||
bus_id, phy_id, device, location);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (smi_rd.s.val)
|
||||
return smi_rd.s.dat;
|
||||
|
||||
debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d INVALID READ\n",
|
||||
bus_id, phy_id, device, location);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Perform an IEEE 802.3 clause 45 MII write. This function is used to write PHY
|
||||
* registers controlling auto negotiation.
|
||||
*
|
||||
* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
|
||||
* support multiple busses.
|
||||
* @param phy_id The MII phy id
|
||||
* @param device MDIO Manageable Device (MMD) id
|
||||
* @param location Register location to write
|
||||
* @param val Value to write
|
||||
*
|
||||
* @return -1 on error
|
||||
* 0 on success
|
||||
*/
|
||||
static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
|
||||
int location, int val)
|
||||
{
|
||||
cvmx_smix_cmd_t smi_cmd;
|
||||
cvmx_smix_wr_dat_t smi_wr;
|
||||
int node = cvmx_mdio_bus_id_to_node(bus_id);
|
||||
int bus = cvmx_mdio_bus_id_to_bus(bus_id);
|
||||
|
||||
if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
|
||||
return -1;
|
||||
|
||||
__cvmx_mdio_set_clause45_mode(bus_id);
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = location;
|
||||
csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = device;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
||||
cvmx_smix_wr_dat_t, pending, ==, 0,
|
||||
CVMX_MDIO_TIMEOUT))
|
||||
return -1;
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = val;
|
||||
csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = device;
|
||||
csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
|
||||
|
||||
if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
||||
cvmx_smix_wr_dat_t, pending, ==, 0,
|
||||
CVMX_MDIO_TIMEOUT))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
343
arch/mips/mach-octeon/include/mach/cvmx-pki-cluster.h
Normal file
343
arch/mips/mach-octeon/include/mach/cvmx-pki-cluster.h
Normal file
@@ -0,0 +1,343 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018-2022 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
/* L4_PORT_CHECK_DISABLE_LF tag */
|
||||
/* This file is autogenerated from ipemainc.elf */
|
||||
const int cvmx_pki_cluster_code_length = 997;
|
||||
const u64 cvmx_pki_cluster_code_default[] = {
|
||||
0x000000000a000000ull, 0x0000413a68024070ull, 0x0000813800200020ull,
|
||||
0x900081b800200020ull, 0x0004da00ffff0001ull, 0x000455ab68010b0eull,
|
||||
0x00045fba46010000ull, 0x9046898120002000ull, 0x0004418068010028ull,
|
||||
0x90665300680100f0ull, 0x0004413f68004070ull, 0x00065380680100f0ull,
|
||||
0x00045a346803a0f0ull, 0x000401b448000001ull, 0x00045cb968030870ull,
|
||||
0x0007debd00100010ull, 0x0000813b80008000ull, 0x000441bb68004070ull,
|
||||
0xd001c00000000000ull, 0xd021c00000000000ull, 0x00045f80680100f0ull,
|
||||
0x0004c639ff000200ull, 0x0004403f72010000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x000041ba68034078ull, 0x0000512268030870ull,
|
||||
0x000041bc68034070ull, 0x00005d3a68030870ull, 0x00045cb942080000ull,
|
||||
0x0004552a4e09312dull, 0x00045cb968082868ull, 0x0004410246090000ull,
|
||||
0x0000813800800080ull, 0x000401a486000005ull, 0x000615ab74000123ull,
|
||||
0x0007122448000004ull, 0x0000813901000000ull, 0x000481b800010001ull,
|
||||
0x000685b800020002ull, 0xa006823800010001ull, 0x0006c639ff000400ull,
|
||||
0x00085f3e68010a00ull, 0xa0885f3e68010f01ull, 0x00085f3e68010405ull,
|
||||
0x00085f3e68010906ull, 0xa0485f3e68010e07ull, 0xa061c00000000000ull,
|
||||
0xa4085f3e68010b28ull, 0xa421c00000000000ull, 0x00095f3e68010940ull,
|
||||
0xa066403e72010000ull, 0x000941be68034039ull, 0x00085f3e68010305ull,
|
||||
0xa4685f3e68010028ull, 0x00095f3e68030030ull, 0x00095f3e68010416ull,
|
||||
0x0001c00000000000ull, 0x00065cb942080000ull, 0xa046552a4e09312dull,
|
||||
0xa446c639ff000500ull, 0x0006debd00010001ull, 0x0006403e72010001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x00065cb942080000ull, 0x0006552a4e09312dull,
|
||||
0x00065cb968082868ull, 0x0006410246090000ull, 0x9060813901000000ull,
|
||||
0x0004c639ff000800ull, 0x0004400072010000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x00045cb942080000ull,
|
||||
0x9084552a4e09312dull, 0x90a4c639ff000900ull, 0x00045f80680100f0ull,
|
||||
0x0004403f72010001ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x00045cb942080000ull, 0x9004552a4e09312dull,
|
||||
0x0004c639ff000a00ull, 0x0004400072010000ull, 0x00048181ff00ff00ull,
|
||||
0x0007820101000100ull, 0x0006898100ff00ffull, 0x00048301ffff0180ull,
|
||||
0x0008d5ab10001000ull, 0x0004d4a900010001ull, 0x0001c00000000000ull,
|
||||
0x00045cb942080000ull, 0x9024552a4e09312dull, 0x0004c639ff000b00ull,
|
||||
0x90445f80680100f0ull, 0x000459b368020070ull, 0x000401024000000cull,
|
||||
0x0006823fffffffffull, 0x00088281ffffffffull, 0x000ad5ab20002000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0004403f72010001ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x000c8b3fffffc200ull, 0x000c8b01ffff0001ull,
|
||||
0x000ddebd00020002ull, 0x00045cb942080000ull, 0x0004552a4e09312dull,
|
||||
0x00045cb968082868ull, 0x0004410246090000ull, 0x0000813901000000ull,
|
||||
0x000481b800080008ull, 0x9846c639ff001200ull, 0x9861c00000000000ull,
|
||||
0x00064180680100f0ull, 0x0006400372010000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x000683891f000200ull,
|
||||
0x000ed52a00800080ull, 0x000e5e3c68020070ull, 0x00065cb942080000ull,
|
||||
0x0006552a4e09312dull, 0x00065cb968082868ull, 0x0006410246090000ull,
|
||||
0x0000813d00020002ull, 0x0004893901000000ull, 0x9004893800040004ull,
|
||||
0x9024c639ff001300ull, 0x00044180680100f0ull, 0x9044400372010001ull,
|
||||
0x0001c00000000000ull, 0x00045f3e68010044ull, 0x0004debd00040004ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000483891f000200ull, 0x000ed52a00800080ull, 0x000e5e3c68020070ull,
|
||||
0x00045cb942080000ull, 0x0004552a4e09312dull, 0x00045cb968082868ull,
|
||||
0x0004410246090000ull, 0x000581b902000000ull, 0x9826c639ff001800ull,
|
||||
0x9801c00000000000ull, 0x00064180680100f0ull, 0x0006400172030000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000682091f000200ull, 0x000883aa00800080ull, 0x000ed52a00400040ull,
|
||||
0x000e5e3c68020870ull, 0x000fd52a00800080ull, 0x000f5e3c68020070ull,
|
||||
0x000983891f000000ull, 0x000f54a968090148ull, 0x000f59b368020870ull,
|
||||
0x00065cb942080000ull, 0x0006552a4e09312dull, 0x00065cb968082868ull,
|
||||
0x0006410246090000ull, 0x000081b902000000ull, 0x9826c639ff001900ull,
|
||||
0x9801c00000000000ull, 0x00064180680100f0ull, 0x0006400172030001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000682091f000200ull, 0x000883aa00800080ull, 0x000ed52a00400040ull,
|
||||
0x000e5e3c68020870ull, 0x000fd52a00800080ull, 0x000f5e3c68020070ull,
|
||||
0x000983891f000000ull, 0x000f54a968090148ull, 0x000f59b368020870ull,
|
||||
0x00065cb942080000ull, 0x0006552a4e09312dull, 0x00065cb968082868ull,
|
||||
0x0006410246090000ull, 0x000081b902000000ull, 0x9826c639ff001a00ull,
|
||||
0x9801c00000000000ull, 0x00064180680100f0ull, 0x0006400172030000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000682091f000200ull, 0x000883aa00800080ull, 0x000ed52a00400040ull,
|
||||
0x000e5e3c68020870ull, 0x000fd52a00800080ull, 0x000f5e3c68020070ull,
|
||||
0x000983891f000000ull, 0x000f54a968090148ull, 0x000f59b368020870ull,
|
||||
0x00065cb942080000ull, 0x0006552a4e09312dull, 0x00065cb968082868ull,
|
||||
0x0006410246090000ull, 0x000081b902000000ull, 0x9826c639ff001b00ull,
|
||||
0x9801c00000000000ull, 0x00064180680100f0ull, 0x0006400172030001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000682091f000200ull, 0x000883aa00800080ull, 0x000ed52a00400040ull,
|
||||
0x000e5e3c68020870ull, 0x000fd52a00800080ull, 0x000f5e3c68020070ull,
|
||||
0x000983891f000000ull, 0x000f54a968090148ull, 0x000f59b368020870ull,
|
||||
0x00065cb942080000ull, 0x0006552a4e09312dull, 0x00065cb968082868ull,
|
||||
0x0006410246090000ull, 0x9000813902000000ull, 0x000481b800400040ull,
|
||||
0x00068981ffff8847ull, 0x00068581ffff8848ull, 0x0006debd00080008ull,
|
||||
0x0006c639ff001e00ull, 0x0006010240000002ull, 0x9801c00000000000ull,
|
||||
0x9821c00000000000ull, 0x00065f80680100f0ull, 0x0006403f72010000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x00065cb942080000ull, 0x0006552a4e09312dull, 0x00065cb968082868ull,
|
||||
0x0006010240000004ull, 0x0006823902000000ull, 0x00065f3e68010629ull,
|
||||
0xac28828101000100ull, 0x000b010240000004ull, 0xa42b820101000100ull,
|
||||
0x0009010240000004ull, 0xac29828101000100ull, 0x000b010240000004ull,
|
||||
0xa42b820101000100ull, 0x0009010240000004ull, 0xac29828101000100ull,
|
||||
0x000b010240000004ull, 0x0006823904000000ull, 0x0008d4a907c00200ull,
|
||||
0x0008593268020070ull, 0x0008dcb902000200ull, 0x9000813902000000ull,
|
||||
0x0001c00000000000ull, 0x00040181840005ffull, 0x0006010240000008ull,
|
||||
0x9801c00000000000ull, 0x0006debd00200020ull, 0x00048181ffff0806ull,
|
||||
0x0006d4a907c00180ull, 0x00048201ffff8035ull, 0x00068581ffff8035ull,
|
||||
0x0008d4a907c001c0ull, 0x0006dcb97c007c00ull, 0x00048201ffff0800ull,
|
||||
0x00088601ffff86ddull, 0x00068581ffff0800ull, 0x00068581ffff86ddull,
|
||||
0x0008d4a907c00200ull, 0x0009dcb97c007c00ull, 0x0007823d00200020ull,
|
||||
0x000685bd00200020ull, 0x0008d4a907c00140ull, 0x0004010240000002ull,
|
||||
0x0006593268020070ull, 0x000042a486020000ull, 0x000a15ab74000124ull,
|
||||
0x9000813904000000ull, 0x0001c00000000000ull, 0x00048181f0004000ull,
|
||||
0x9886593268020070ull, 0x0006d4a907c00200ull, 0x00068201ff000000ull,
|
||||
0xa40815ab74000345ull, 0x0009debd01000100ull, 0xa429418068010038ull,
|
||||
0x00095a3468010870ull, 0x0009028386000005ull, 0x000a068186000014ull,
|
||||
0xacca15ab74000343ull, 0xacebc639ff002200ull, 0x000b5f80680100f0ull,
|
||||
0xac8b403f72010000ull, 0x000b8203000f0005ull, 0x000b5a3468010070ull,
|
||||
0x0009d4a907c00240ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x000b5cb942080000ull, 0xad0b552a4e09312dull,
|
||||
0xad2bc639ff002700ull, 0x000b5f80680100f0ull, 0xac6b403f72010001ull,
|
||||
0x0001c00000000000ull, 0x000b82013fff0000ull, 0x0009d52a00010001ull,
|
||||
0x0009d4a9f8006800ull, 0x0009593268020870ull, 0x0006418068030230ull,
|
||||
0x000b5cb942080000ull, 0x000b552a4e09312dull, 0x0006410240030000ull,
|
||||
0x9c01c00000000000ull, 0x0001c00000000000ull, 0x00078201f0006000ull,
|
||||
0x0008593268020070ull, 0x0008d4a907c00280ull, 0xa069d4a907c00000ull,
|
||||
0x00085a3468010874ull, 0x0008818100ff0000ull, 0x000615ab74000345ull,
|
||||
0x00075a3468010078ull, 0x9c8741b9680040f0ull, 0x9ca7c603ff001f00ull,
|
||||
0x00075f80680100f0ull, 0x0007403f72010001ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0007418342080000ull,
|
||||
0x9cc7552a4e09312dull, 0x9ce7c603ff002000ull, 0x00075f80680100f0ull,
|
||||
0x0007403f72010000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0007418342080000ull, 0x9d07552a4e09312dull,
|
||||
0x9d27c603ff002100ull, 0x00075f80680100f0ull, 0x0007403f72010001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0007418342080000ull, 0x0007552a4e09312dull, 0x9d475c80680300f0ull,
|
||||
0x9d67c639ff002200ull, 0x00075f80680100f0ull, 0x0007403f72010000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x00075cb942080000ull, 0x0007552a4e09312dull, 0x9d8741b9680040f0ull,
|
||||
0x9da7c603ff002400ull, 0x00075f80680100f0ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0007403f72010000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0007418342080000ull, 0x9dc7552a4e09312dull,
|
||||
0x9de7c603ff002500ull, 0x00075f80680100f0ull, 0x0007403f72010001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0007418342080000ull, 0x0007552a4e09312dull, 0x0007010240000020ull,
|
||||
0x9c01c00000000000ull, 0x9c27c603ff002600ull, 0x00075f80680100f0ull,
|
||||
0x0007403f72010000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0007418342080000ull, 0x0007552a4e09312dull,
|
||||
0x9c475c80680300f0ull, 0x9c67c639ff002700ull, 0x00075f80680100f0ull,
|
||||
0x0007403f72010001ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x00075cb942080000ull, 0x0007552a4e09312dull,
|
||||
0x0007010240000008ull, 0xa80782b400ff0000ull, 0x000ad4a907c002c0ull,
|
||||
0x000a5a3468010078ull, 0x000a410244010000ull, 0xa80782b400ff003cull,
|
||||
0x000ad4a907c002c0ull, 0x000a5a3468010078ull, 0x000a410244010000ull,
|
||||
0xa80782b400ff002bull, 0x000ad4a907c002c0ull, 0x000a5a3468010078ull,
|
||||
0x000a410244010000ull, 0xa80782b400ff002cull, 0x000ad4a9ffc06ac0ull,
|
||||
0x000a593268020870ull, 0x000ad52a00010001ull, 0x000a5a3468010078ull,
|
||||
0x000a010240000008ull, 0x0007debd01000100ull, 0x000481bd01000100ull,
|
||||
0x0006c639ff002300ull, 0x000641aa68034000ull, 0x000641a968034846ull,
|
||||
0x0006403472030001ull, 0x0004822907000200ull, 0x000915ab74000341ull,
|
||||
0x000082aa00010001ull, 0x000a86ab00ff0045ull, 0x000adcb978007800ull,
|
||||
0x0000822907000200ull, 0x00088a3908000000ull, 0x00065cb942080000ull,
|
||||
0x0006552a4e09312dull, 0x00065cb968082868ull, 0x0006410246090000ull,
|
||||
0x000042a486020000ull, 0x000a15ab74000343ull, 0x000081b940004000ull,
|
||||
0x000685a907c00000ull, 0x000782b807000100ull, 0x000a41b268004070ull,
|
||||
0x000a410040030000ull, 0x000a41ba68004078ull, 0x000a410240030000ull,
|
||||
0xa801c00000000000ull, 0xa821c00000000000ull, 0x000a4180680100f0ull,
|
||||
0x000ac639ff003900ull, 0x000a400372010001ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x000a83891f000000ull,
|
||||
0x000f542868090a48ull, 0x000f583068020070ull, 0x000a5cb942080000ull,
|
||||
0x000a552a4e09312dull, 0x000a5cb968082868ull, 0x000a410246090000ull,
|
||||
0x982881b400ff0011ull, 0x9881c00000000000ull, 0x00064180680100f0ull,
|
||||
0x00068283ffff12b5ull, 0x000a8a8108000800ull, 0x000ad4a9f8009800ull,
|
||||
0x00068303ffff17c1ull, 0x000c8b01c0000000ull, 0xb0ac5bb768010a58ull,
|
||||
0x000cd4a9f800b800ull, 0x000c8281ffff6558ull, 0x000adbb701000100ull,
|
||||
0x000c8281ffff86ddull, 0x000a8681ffff0800ull, 0x000adbb702000200ull,
|
||||
0x000682a9c8009800ull, 0x000adebd02000200ull, 0x000a593268020870ull,
|
||||
0x000a010240000008ull, 0x9c21c00000000000ull, 0x0007813400ff002full,
|
||||
0x90048201ffff6558ull, 0x00098381ffff0800ull, 0x00088281b0002000ull,
|
||||
0x000a593268020870ull, 0x000ad4a9f800a800ull, 0x000adebd02000200ull,
|
||||
0x000e593268020870ull, 0x000ed4a9f800a000ull, 0x000e010240000004ull,
|
||||
0x000e828180008000ull, 0x000a010240000004ull, 0x000e828120002000ull,
|
||||
0x000a010240000004ull, 0x000e828110001000ull, 0x000a010240000004ull,
|
||||
0x000082bd02000200ull, 0xa80ac639ff002800ull, 0xa861c00000000000ull,
|
||||
0x000a418368010526ull, 0xa84a418368010878ull, 0x000a5bb768030078ull,
|
||||
0x000a400172030000ull, 0x000a5b00680100f0ull, 0x000041b468034878ull,
|
||||
0x00005fbf68030878ull, 0x00068229c8009800ull, 0x0008010248000008ull,
|
||||
0xa001c00000000000ull, 0x000843a486020000ull, 0x00088101ffff0000ull,
|
||||
0x000415ab74000464ull, 0x000e15ab74000461ull, 0x0008010240000008ull,
|
||||
0x000c41b76800425aull, 0x000c410240030000ull, 0x000a010240000008ull,
|
||||
0x000a5cb942080000ull, 0x000a552a4e09312dull, 0x000a5cb968082868ull,
|
||||
0x000a410246090000ull, 0x0000422486020000ull, 0x000815ab74000461ull,
|
||||
0x000081b940004000ull, 0x000685a9f8000000ull, 0x000782b807000200ull,
|
||||
0x000a41b268004078ull, 0x000a410040030000ull, 0x000a41ba68004078ull,
|
||||
0x000a410240030000ull, 0xa801c00000000000ull, 0xa821c00000000000ull,
|
||||
0x000a4180680100f0ull, 0x000ac639ff003900ull, 0x000a400372010001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x000a83891f000000ull, 0x000f542868090a48ull, 0x000f583068020070ull,
|
||||
0x000a5cb942080000ull, 0x000a552a4e09312dull, 0x000a5cb968082868ull,
|
||||
0x000a410246090000ull, 0x000081a9f800b800ull, 0x000689b701000100ull,
|
||||
0x000685a9f8009800ull, 0x000685a9f800a800ull, 0x00078229f800b800ull,
|
||||
0x000601024000000cull, 0x9801c00000000000ull, 0x00088a3702000200ull,
|
||||
0x00088629f800a000ull, 0x00068101ffff8100ull, 0x0004010240000004ull,
|
||||
0x9801c00000000000ull, 0x0009dcb910001000ull, 0x00068101ffff86ddull,
|
||||
0x00048501ffff0800ull, 0x0005dcb978003800ull, 0x0006010240000002ull,
|
||||
0x000081a9f8000000ull, 0x9007813910000000ull, 0x0001c00000000000ull,
|
||||
0x00048181f0004000ull, 0x988658b168020070ull, 0x0006d428001f0008ull,
|
||||
0x00068201ff000000ull, 0xa40815ab74000545ull, 0x0009debd04000400ull,
|
||||
0xa429418068010038ull, 0x00095a3468010870ull, 0x0009028386000005ull,
|
||||
0xac8a068186000014ull, 0x000a15ab74000543ull, 0x000b5a3468010070ull,
|
||||
0xac6b8303000f0005ull, 0x000dd428001f0009ull, 0x000b83013fff0000ull,
|
||||
0x000dd42803e001a0ull, 0x000d58b168020870ull, 0x000ddcb960006000ull,
|
||||
0x0006418068030230ull, 0x0006410240030000ull, 0x9c01c00000000000ull,
|
||||
0x0001c00000000000ull, 0x00078201f0006000ull, 0x000858b168020070ull,
|
||||
0xa068d428001f000aull, 0x00085a3468010874ull, 0x0008818100ff0000ull,
|
||||
0x000615ab74000545ull, 0x00075a3468010078ull, 0x0007010240000028ull,
|
||||
0xa80782b400ff0000ull, 0x000ad428001f000bull, 0x000a5a3468010078ull,
|
||||
0x000a410244010000ull, 0xa80782b400ff003cull, 0x000ad428001f000bull,
|
||||
0x000a5a3468010078ull, 0x000a410244010000ull, 0xa80782b400ff002bull,
|
||||
0x000ad428001f000bull, 0x000a5a3468010078ull, 0x000a410244010000ull,
|
||||
0xa80782b400ff002cull, 0x000ad42803ff01abull, 0x000adcb960006000ull,
|
||||
0x000a58b168020870ull, 0x000a5a3468010078ull, 0x000a010240000008ull,
|
||||
0x0007debd04000400ull, 0x000481bd04000400ull, 0x0006c639ff002b00ull,
|
||||
0x0006832803e001a0ull, 0x000cc18300010001ull, 0x000dc18300010000ull,
|
||||
0x000641a868034840ull, 0x0006403472030001ull, 0x00048228001c0008ull,
|
||||
0x000915ab74000541ull, 0x000082ab00ff0045ull, 0x000adcb960006000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x00065cb942080000ull,
|
||||
0x0006552a4e09312dull, 0x00065cb968082868ull, 0x0006410246090000ull,
|
||||
0x000042a486020000ull, 0x000a15ab74000543ull, 0x000081b940004000ull,
|
||||
0x000685a8001f0000ull, 0x000782b807000300ull, 0x000a41b168004070ull,
|
||||
0x000a410040030000ull, 0x000a41ba68004078ull, 0x000a410240030000ull,
|
||||
0xa801c00000000000ull, 0xa821c00000000000ull, 0x000a4180680100f0ull,
|
||||
0x000ac639ff003900ull, 0x000a400372010001ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x000a83891f000000ull,
|
||||
0x000f542868090a48ull, 0x000f583068020070ull, 0x000a5cb942080000ull,
|
||||
0x000a552a4e09312dull, 0x000a5cb968082868ull, 0x000a410246090000ull,
|
||||
0x00008329ff000200ull, 0x000c8728001c0008ull, 0x000c813920000000ull,
|
||||
0x000481b400ff006cull, 0x0006d42803e001c0ull, 0x000658b168020870ull,
|
||||
0xa047823400ff0033ull, 0x0008d42803e00180ull, 0xa0685f80680100f0ull,
|
||||
0xa007823400ff0032ull, 0x0008d42803e00180ull, 0xa0285f80680100f0ull,
|
||||
0x0007822803e00180ull, 0x0008c639ff002e00ull, 0x0008403f72010000ull,
|
||||
0x000858b168020870ull, 0x00085abf680040f0ull, 0x00085d80680100f0ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x00085cb942080000ull, 0x0008552a4e09312dull, 0x00085cb968082868ull,
|
||||
0x0008410246090000ull, 0x986981b400ff002full, 0x0006d42803e00280ull,
|
||||
0x00065a80680100f0ull, 0x000658b168020870ull, 0x000481b400ff0084ull,
|
||||
0x0006d42803e00240ull, 0x0004823400ff0011ull, 0x0008d42803e00220ull,
|
||||
0x98c481b400ff0006ull, 0x0006d42803e00200ull, 0x00065ebd68010b31ull,
|
||||
0x000641806801003cull, 0x0006028386000005ull, 0x000a15ab74000661ull,
|
||||
0x0006418068030230ull, 0x0008c180ffff0008ull, 0x0008863400ff0006ull,
|
||||
0x0008418240030000ull, 0x000842a486030000ull, 0x000a15ab74000661ull,
|
||||
0x9008863400ff0084ull, 0x0004c639ff002f00ull, 0x0004400072010001ull,
|
||||
0x000858b168020870ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x00085cb942080000ull, 0x9028552a4e09312dull,
|
||||
0x0004c639ff003000ull, 0x0004403472010000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x000858b168020870ull, 0x0001c00000000000ull,
|
||||
0x000081b940004000ull, 0x000685a803e00000ull, 0x00045cb942080000ull,
|
||||
0x0004552a4e09312dull, 0x00045cb968082868ull, 0x0004410246090000ull,
|
||||
0x000483891f000000ull, 0x000f542868090a48ull, 0x000f583068020070ull,
|
||||
0x000042a486020000ull, 0x000a15ab74000661ull, 0x000782b807000400ull,
|
||||
0x000a41b168004078ull, 0x000a410040030000ull, 0x000a41ba68004078ull,
|
||||
0x000a410240030000ull, 0xa801c00000000000ull, 0xa821c00000000000ull,
|
||||
0x000a4180680100f0ull, 0x000ac639ff003900ull, 0x000a400372010001ull,
|
||||
0x0001c00000000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull, 0x000041bf68034878ull, 0x00005a3468030878ull,
|
||||
0x000a83891f000000ull, 0x000f542868090a48ull, 0x000f583068020070ull,
|
||||
0x000a5cb942080000ull, 0x000a552a4e09312dull, 0x000a5cb968082868ull,
|
||||
0x000a410246090000ull, 0x00005fb968004250ull, 0x0000003f70000000ull,
|
||||
0x000041b968034070ull, 0x0000512268030070ull, 0x0000813800200020ull,
|
||||
0x0004413a68024070ull, 0x9001c00000000000ull, 0x000081b800200020ull,
|
||||
0x9026898180008000ull, 0x0004890110001000ull, 0x000456ad680100a0ull,
|
||||
0x0006898180008000ull, 0x000652a56801001dull, 0x000456ad68090b5bull,
|
||||
0x00055680680900f0ull, 0x0005debd00400040ull, 0x00005600680800f0ull,
|
||||
0x0000833d00200020ull, 0x000c872907c00000ull, 0x000dd62c20000000ull,
|
||||
0x0000822902800280ull, 0x000841b268034070ull, 0x000982a8000a000aull,
|
||||
0x000a41b168034070ull, 0x000b822907c00000ull, 0x0000003f70000800ull,
|
||||
0x000941b268034070ull, 0x0000418048030000ull, 0x0000018340000008ull,
|
||||
0x0009018348000004ull, 0x000050a168030c20ull, 0x000082aa00800080ull,
|
||||
0x000850a168080c2bull, 0x0000820800010001ull, 0x000850a168000c20ull,
|
||||
0x000752a56808001eull, 0x000a822a00400040ull, 0x00088a0900010001ull,
|
||||
0x000841bc68034078ull, 0x000941bc68034070ull, 0x000a583068030870ull,
|
||||
0x0000813d00400000ull, 0x0005c180ffff0000ull, 0x00058288001e0000ull,
|
||||
0x000b8208001e0008ull, 0x00085d2168004030ull, 0x00098308001e0010ull,
|
||||
0x00088608001e0010ull, 0x000c5d2168004070ull, 0x0008418068080025ull,
|
||||
0x000841ba6803a0f0ull, 0x000856ad40030000ull, 0x0008c180ffff0000ull,
|
||||
0x0005820807000500ull, 0x00088a3d00010001ull, 0x000841be68004050ull,
|
||||
0x0005828807000300ull, 0x000a8abd00040004ull, 0x000a41be68004040ull,
|
||||
0x0005820807000100ull, 0x00088a2a00800080ull, 0x0008413068004078ull,
|
||||
0xa021c00000000000ull, 0x0005828807000200ull, 0x000841806801002dull,
|
||||
0x000a8abd00080008ull, 0x000a41be68004026ull, 0x0005820807000400ull,
|
||||
0x00088a2907000200ull, 0x000841b46800405aull, 0x000556ad40030000ull,
|
||||
0x000081bd00100010ull, 0x0006c180ffff0000ull, 0x0006822a00800080ull,
|
||||
0x00088a0900100010ull, 0x0008413c68024070ull, 0xa021c00000000000ull,
|
||||
0x0006832907000200ull, 0x0008c181f0008000ull, 0x000841834c00ffffull,
|
||||
0x0006822a00400040ull, 0x00088a0900200020ull, 0x0008413c68024078ull,
|
||||
0xa021c00000000000ull, 0x000c8b0900400040ull, 0x0008dc01f0008000ull,
|
||||
0x000841b84c03ffffull, 0x000c8b2a00010000ull, 0x000c41b44c0300ffull,
|
||||
0x000682a9f800a800ull, 0x000a86a9f8009800ull, 0x000a8a8904000400ull,
|
||||
0x000a41b64c03ffffull, 0x000a41b74c0300ffull, 0x0000828901000100ull,
|
||||
0x000a822803e00180ull, 0x0008413168024078ull, 0x0008833400ff0033ull,
|
||||
0x000c010240000004ull, 0xa001c00000000000ull, 0xa021c00000000000ull,
|
||||
0x000841814c03ffffull, 0x000841814c03ffffull, 0x000a822803e00280ull,
|
||||
0x000841b54c03ffffull, 0x000682287c005800ull, 0x00088a0902000200ull,
|
||||
0x0008413068024070ull, 0xa001c00000000000ull, 0x0006830900020002ull,
|
||||
0x00088281e0002000ull, 0xa84a868108000800ull, 0xa861c00000000000ull,
|
||||
0x000a41814c03ffffull, 0x000a41814c03ffffull, 0x00065380680300f0ull,
|
||||
0x000c5321680040b0ull, 0x000dd3260fff0fffull, 0x0006810900800080ull,
|
||||
0x0000003f70000400ull, 0x000082a907000200ull, 0x000a413268024070ull,
|
||||
0xa50a822902800280ull, 0x0004893d08000800ull, 0x00098301ffffffffull,
|
||||
0xa4c98381f000e000ull, 0x00095f00680100f0ull, 0xa5295f3e64010000ull,
|
||||
0x0001c00000000000ull, 0xa4ec8b01ffffffffull, 0x00095d00680100f0ull,
|
||||
0xa1895d3a64010000ull, 0x000cd5ab80008000ull, 0x00088a01ff00ff00ull,
|
||||
0x0008d5ab40004000ull, 0x000ed5ab40004000ull, 0x0004893d40000000ull,
|
||||
0x00005700680800f0ull, 0x00005780680900f0ull, 0x00008229f800a000ull,
|
||||
0x0008c180ffff0018ull, 0x000857af680320f0ull, 0x0007d72ef1ff0000ull,
|
||||
0x0007d7aff0000000ull, 0x0004d72e00fc0000ull, 0x0000812c00020002ull,
|
||||
0x0004892907c00200ull, 0x000441a7680040f0ull, 0x000441be4c03ffffull,
|
||||
0x000441ba4c03ffffull, 0x000481a803c00200ull, 0x0006413168024078ull,
|
||||
0x9801c00000000000ull, 0x9821c00000000000ull, 0x00065f80680100f0ull,
|
||||
0x00065fbf64010000ull, 0x000641bf4c03ffffull, 0x000452a568030250ull,
|
||||
0x0000000008000000ull, 0x0001c00000000000ull, 0x0001c00000000000ull,
|
||||
0x0001c00000000000ull
|
||||
};
|
||||
213
arch/mips/mach-octeon/include/mach/cvmx-pko.h
Normal file
213
arch/mips/mach-octeon/include/mach/cvmx-pko.h
Normal file
@@ -0,0 +1,213 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018-2022 Marvell International Ltd.
|
||||
*
|
||||
* Backward compatibility for packet transmission using legacy PKO command.
|
||||
*/
|
||||
|
||||
#ifndef __CVMX_PKO_H__
|
||||
#define __CVMX_PKO_H__
|
||||
|
||||
extern cvmx_pko_return_value_t
|
||||
cvmx_pko3_legacy_xmit(unsigned int dq, cvmx_pko_command_word0_t pko_command,
|
||||
cvmx_buf_ptr_t packet, uint64_t addr, bool tag_sw);
|
||||
|
||||
/**
|
||||
* Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly
|
||||
* once before this, and the same parameters must be passed to both
|
||||
* cvmx_pko_send_packet_prepare() and cvmx_pko_send_packet_finish().
|
||||
*
|
||||
* WARNING: This function may have to look up the proper PKO port in
|
||||
* the IPD port to PKO port map, and is thus slower than calling
|
||||
* cvmx_pko_send_packet_finish_pkoid() directly if the PKO port
|
||||
* identifier is known.
|
||||
*
|
||||
* @param ipd_port The IPD port corresponding the to pko port the packet is for
|
||||
* @param queue Queue to use
|
||||
* @param pko_command
|
||||
* PKO HW command word
|
||||
* @param packet to send
|
||||
* @param use_locking
|
||||
* CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG,
|
||||
* or CVMX_PKO_LOCK_CMD_QUEUE
|
||||
*
|
||||
* @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
|
||||
*/
|
||||
static inline cvmx_pko_return_value_t
|
||||
cvmx_pko_send_packet_finish(u64 ipd_port, uint64_t queue,
|
||||
cvmx_pko_command_word0_t pko_command,
|
||||
cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
|
||||
{
|
||||
cvmx_cmd_queue_result_t result;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
|
||||
return cvmx_pko3_legacy_xmit(queue, pko_command, packet, 0,
|
||||
use_locking ==
|
||||
CVMX_PKO_LOCK_ATOMIC_TAG);
|
||||
}
|
||||
|
||||
if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
|
||||
cvmx_pow_tag_sw_wait();
|
||||
|
||||
result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
|
||||
(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
|
||||
pko_command.u64, packet.u64);
|
||||
if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
|
||||
cvmx_pko_doorbell(ipd_port, queue, 2);
|
||||
return CVMX_PKO_SUCCESS;
|
||||
} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) ||
|
||||
(result == CVMX_CMD_QUEUE_FULL)) {
|
||||
return CVMX_PKO_NO_MEMORY;
|
||||
} else {
|
||||
return CVMX_PKO_INVALID_QUEUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly
|
||||
* once before this, and the same parameters must be passed to both
|
||||
* cvmx_pko_send_packet_prepare() and cvmx_pko_send_packet_finish().
|
||||
*
|
||||
* WARNING: This function may have to look up the proper PKO port in
|
||||
* the IPD port to PKO port map, and is thus slower than calling
|
||||
* cvmx_pko_send_packet_finish3_pkoid() directly if the PKO port
|
||||
* identifier is known.
|
||||
*
|
||||
* @param ipd_port The IPD port corresponding the to pko port the packet is for
|
||||
* @param queue Queue to use
|
||||
* @param pko_command
|
||||
* PKO HW command word
|
||||
* @param packet to send
|
||||
* @param addr Physical address of a work queue entry or physical address to zero
|
||||
* on complete.
|
||||
* @param use_locking
|
||||
* CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG,
|
||||
* or CVMX_PKO_LOCK_CMD_QUEUE
|
||||
*
|
||||
* @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
|
||||
*/
|
||||
static inline cvmx_pko_return_value_t
|
||||
cvmx_pko_send_packet_finish3(u64 ipd_port, uint64_t queue,
|
||||
cvmx_pko_command_word0_t pko_command,
|
||||
cvmx_buf_ptr_t packet, uint64_t addr,
|
||||
cvmx_pko_lock_t use_locking)
|
||||
{
|
||||
cvmx_cmd_queue_result_t result;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
|
||||
return cvmx_pko3_legacy_xmit(queue, pko_command, packet, addr,
|
||||
use_locking ==
|
||||
CVMX_PKO_LOCK_ATOMIC_TAG);
|
||||
}
|
||||
|
||||
if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
|
||||
cvmx_pow_tag_sw_wait();
|
||||
|
||||
result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
|
||||
(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
|
||||
pko_command.u64, packet.u64, addr);
|
||||
if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
|
||||
cvmx_pko_doorbell(ipd_port, queue, 3);
|
||||
return CVMX_PKO_SUCCESS;
|
||||
} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) ||
|
||||
(result == CVMX_CMD_QUEUE_FULL)) {
|
||||
return CVMX_PKO_NO_MEMORY;
|
||||
} else {
|
||||
return CVMX_PKO_INVALID_QUEUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly
|
||||
* once before this, and the same parameters must be passed to both
|
||||
* cvmx_pko_send_packet_prepare() and cvmx_pko_send_packet_finish_pkoid().
|
||||
*
|
||||
* @param pko_port Port to send it on
|
||||
* @param queue Queue to use
|
||||
* @param pko_command
|
||||
* PKO HW command word
|
||||
* @param packet to send
|
||||
* @param use_locking
|
||||
* CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG,
|
||||
* or CVMX_PKO_LOCK_CMD_QUEUE
|
||||
*
|
||||
* @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
|
||||
*/
|
||||
static inline cvmx_pko_return_value_t
|
||||
cvmx_pko_send_packet_finish_pkoid(int pko_port, uint64_t queue,
|
||||
cvmx_pko_command_word0_t pko_command,
|
||||
cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
|
||||
{
|
||||
cvmx_cmd_queue_result_t result;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
|
||||
return cvmx_pko3_legacy_xmit(queue, pko_command, packet, 0,
|
||||
use_locking ==
|
||||
CVMX_PKO_LOCK_ATOMIC_TAG);
|
||||
}
|
||||
|
||||
if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
|
||||
cvmx_pow_tag_sw_wait();
|
||||
result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
|
||||
(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
|
||||
pko_command.u64, packet.u64);
|
||||
if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
|
||||
cvmx_pko_doorbell_pkoid(pko_port, queue, 2);
|
||||
return CVMX_PKO_SUCCESS;
|
||||
} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) ||
|
||||
(result == CVMX_CMD_QUEUE_FULL)) {
|
||||
return CVMX_PKO_NO_MEMORY;
|
||||
} else {
|
||||
return CVMX_PKO_INVALID_QUEUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly
|
||||
* once before this, and the same parameters must be passed to both
|
||||
* cvmx_pko_send_packet_prepare() and cvmx_pko_send_packet_finish_pkoid().
|
||||
*
|
||||
* @param pko_port The PKO port the packet is for
|
||||
* @param queue Queue to use
|
||||
* @param pko_command
|
||||
* PKO HW command word
|
||||
* @param packet to send
|
||||
* @param addr Plysical address of a work queue entry or physical address to zero
|
||||
* on complete.
|
||||
* @param use_locking
|
||||
* CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG,
|
||||
* or CVMX_PKO_LOCK_CMD_QUEUE
|
||||
*
|
||||
* @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
|
||||
*/
|
||||
static inline cvmx_pko_return_value_t
|
||||
cvmx_pko_send_packet_finish3_pkoid(u64 pko_port, uint64_t queue,
|
||||
cvmx_pko_command_word0_t pko_command,
|
||||
cvmx_buf_ptr_t packet, uint64_t addr,
|
||||
cvmx_pko_lock_t use_locking)
|
||||
{
|
||||
cvmx_cmd_queue_result_t result;
|
||||
|
||||
if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
|
||||
return cvmx_pko3_legacy_xmit(queue, pko_command, packet, addr,
|
||||
use_locking ==
|
||||
CVMX_PKO_LOCK_ATOMIC_TAG);
|
||||
}
|
||||
|
||||
if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
|
||||
cvmx_pow_tag_sw_wait();
|
||||
result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
|
||||
(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
|
||||
pko_command.u64, packet.u64, addr);
|
||||
if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
|
||||
cvmx_pko_doorbell_pkoid(pko_port, queue, 3);
|
||||
return CVMX_PKO_SUCCESS;
|
||||
} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) ||
|
||||
(result == CVMX_CMD_QUEUE_FULL)) {
|
||||
return CVMX_PKO_NO_MEMORY;
|
||||
} else {
|
||||
return CVMX_PKO_INVALID_QUEUE;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __CVMX_PKO_H__ */
|
||||
36
arch/mips/mach-octeon/include/mach/cvmx-pko3-resources.h
Normal file
36
arch/mips/mach-octeon/include/mach/cvmx-pko3-resources.h
Normal file
@@ -0,0 +1,36 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018-2022 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __CVMX_PKO3_RESOURCES_H__
|
||||
#define __CVMX_PKO3_RESOURCES_H__
|
||||
|
||||
/*
|
||||
* Allocate or reserve contiguous list of PKO queues.
|
||||
*
|
||||
* @param node is the node number for PKO queues.
|
||||
* @param level is the PKO queue level.
|
||||
* @param owner is the owner of PKO queue resources.
|
||||
* @param base_queue is the PKO queue base number(specify -1 to allocate).
|
||||
* @param num_queues is the number of PKO queues that have to be reserved or allocated.
|
||||
* @return returns queue_base if successful or -1 on failure.
|
||||
*/
|
||||
int cvmx_pko_alloc_queues(int node, int level, int owner, int base_queue,
|
||||
int num_queues);
|
||||
|
||||
/**
|
||||
* Free an allocated/reserved PKO queues for a certain level and owner
|
||||
*
|
||||
* @param node on which to allocate/reserve PKO queues
|
||||
* @param level of PKO queue
|
||||
* @param owner of reserved/allocated resources
|
||||
* @return 0 on success, -1 on failure
|
||||
*/
|
||||
int cvmx_pko_free_queues(int node, int level, int owner);
|
||||
|
||||
int __cvmx_pko3_dq_param_setup(unsigned node);
|
||||
|
||||
int cvmx_pko3_num_level_queues(enum cvmx_pko3_level_e level);
|
||||
|
||||
#endif /* __CVMX_PKO3_RESOURCES_H__ */
|
||||
1052
arch/mips/mach-octeon/include/mach/cvmx-pko3.h
Normal file
1052
arch/mips/mach-octeon/include/mach/cvmx-pko3.h
Normal file
File diff suppressed because it is too large
Load Diff
23
arch/mips/mach-octeon/include/mach/cvmx-range.h
Normal file
23
arch/mips/mach-octeon/include/mach/cvmx-range.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018-2022 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __CVMX_RANGE_H__
|
||||
#define __CVMX_RANGE_H__
|
||||
|
||||
int cvmx_range_init(u64 range_addr, int size);
|
||||
int cvmx_range_alloc(u64 range_addr, uint64_t owner, uint64_t cnt, int align);
|
||||
int cvmx_range_alloc_ordered(u64 range_addr, uint64_t owner, u64 cnt, int align,
|
||||
int reverse);
|
||||
int cvmx_range_alloc_non_contiguos(u64 range_addr, uint64_t owner, u64 cnt,
|
||||
int elements[]);
|
||||
int cvmx_range_reserve(u64 range_addr, uint64_t owner, u64 base, uint64_t cnt);
|
||||
int cvmx_range_free_with_base(u64 range_addr, int base, int cnt);
|
||||
int cvmx_range_free_with_owner(u64 range_addr, uint64_t owner);
|
||||
u64 cvmx_range_get_owner(u64 range_addr, uint64_t base);
|
||||
void cvmx_range_show(uint64_t range_addr);
|
||||
int cvmx_range_memory_size(int nelements);
|
||||
int cvmx_range_free_mutiple(u64 range_addr, int bases[], int count);
|
||||
|
||||
#endif // __CVMX_RANGE_H__
|
||||
Reference in New Issue
Block a user