Remove unused CONFIG_ADDR_STREAMING defines
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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d16da93430
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@ -67,7 +67,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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/*
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@ -70,7 +70,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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@ -79,7 +79,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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@ -62,7 +62,6 @@
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/* below can be toggled for performance analysis. otherwise use default */
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#undef CONFIG_BTB /* toggle branch predition */
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#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
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@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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@ -66,7 +66,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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/*
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* Only possible on E500 Version 2 or newer cores.
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@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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/*
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@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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@ -73,7 +73,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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@ -61,7 +61,6 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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/*
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* Only possible on E500 Version 2 or newer cores.
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@ -71,7 +71,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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@ -71,7 +71,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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@ -72,7 +72,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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@ -75,7 +75,6 @@
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/* below can be toggled for performance analysis. otherwise use default */
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#undef CONFIG_BTB /* toggle branch predition */
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#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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@ -106,7 +106,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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@ -59,7 +59,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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/*
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@ -69,7 +69,6 @@
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/* below can be toggled for performance analysis. otherwise use default */
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#undef CONFIG_BTB /* toggle branch predition */
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#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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@ -82,7 +82,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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@ -64,7 +64,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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@ -64,7 +64,6 @@
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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