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Merge branch 'master' of git://git.denx.de/u-boot-x86

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This commit is contained in:
Tom Rini 2016-07-12 08:15:17 -04:00
commit b8e599746c
35 changed files with 773 additions and 23 deletions
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4
arch/x86/Kconfig
View File

@ -8,6 +8,9 @@ choice
prompt "Mainboard vendor"
default VENDOR_EMULATION
config VENDOR_ADVANTECH
bool "advantech"
config VENDOR_CONGATEC
bool "congatec"
@ -29,6 +32,7 @@ config VENDOR_INTEL
endchoice
# board-specific options below
source "board/advantech/Kconfig"
source "board/congatec/Kconfig"
source "board/coreboot/Kconfig"
source "board/efi/Kconfig"

11
arch/x86/cpu/baytrail/Kconfig
View File

@ -7,3 +7,14 @@
config INTEL_BAYTRAIL
bool
select HAVE_FSP if !EFI
if INTEL_BAYTRAIL
config INTERNAL_UART
bool "Enable the SoC integrated legacy UART"
help
There is a legacy UART integrated into the Bay Trail SoC.
A maximum baud rate of 115200 bps is supported. For this
reason, it is recommended that the UART port be used for
debug purposes only, eg: U-Boot console.
endif

26
arch/x86/cpu/baytrail/acpi.c
View File

@ -5,10 +5,14 @@
*/
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <asm/acpi_table.h>
#include <asm/ioapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
@ -161,3 +165,25 @@ u32 acpi_fill_madt(u32 current)
return current;
}
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
struct udevice *dev;
int ret;
/* at least we have one processor */
gnvs->pcnt = 1;
/* override the processor count with actual number */
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret == 0 && dev != NULL) {
ret = cpu_get_count(dev);
if (ret > 0)
gnvs->pcnt = ret;
}
/* determine whether internal uart is on */
if (IS_ENABLED(CONFIG_INTERNAL_UART))
gnvs->iuart_en = 1;
else
gnvs->iuart_en = 0;
}

5
arch/x86/cpu/ivybridge/sdram.c
View File

@ -458,6 +458,11 @@ int dram_init(void)
struct udevice *dev, *me_dev;
int ret;
/* We need the pinctrl set up early */
ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
if (ret)
return ret;
ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
if (ret)
return ret;

7
arch/x86/cpu/quark/acpi.c
View File

@ -9,6 +9,7 @@
#include <asm/ioapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
@ -161,3 +162,9 @@ u32 acpi_fill_madt(u32 current)
return current;
}
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
/* quark is a uni-processor */
gnvs->pcnt = 1;
}

3
arch/x86/dts/Makefile
View File

@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \
minnowmax.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
broadwell_som-6896.dtb
broadwell_som-6896.dtb \
baytrail_som-db5800-som-6867.dtb
targets += $(dtb-y)

289
arch/x86/dts/baytrail_som-db5800-som-6867.dts Normal file
View File

@ -0,0 +1,289 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Advantech SOM-DB5800-SOM-6867";
compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
aliases {
serial0 = &serial;
spi0 = &spi;
};
config {
silent_console = <0>;
};
pch_pinctrl {
compatible = "intel,x86-pinctrl";
reg = <0 0>;
/* HDA_RSTB */
soc_gpio_s0_8@0 {
pad-offset = <0x220>;
mode-func = <2>;
};
/* HDA_SYNC */
soc_gpio_s0_9@0 {
pad-offset = <0x250>;
mode-func = <2>;
pull-assign = <1>;
};
/* HDA_CLK */
soc_gpio_s0_10@0 {
pad-offset = <0x240>;
mode-func = <2>;
};
/* HDA_SDO */
soc_gpio_s0_11@0 {
pad-offset = <0x260>;
mode-func = <2>;
pull-assign = <1>;
};
/* HDA_SDI0 */
soc_gpio_s0_12@0 {
pad-offset = <0x270>;
mode-func = <2>;
};
};
chosen {
stdout-path = "/serial";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <1>;
intel,apic-id = <2>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <2>;
intel,apic-id = <4>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,baytrail-cpu";
reg = <3>;
intel,apic-id = <6>;
};
};
pci {
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "pci8086,0f1c", "intel,pch9";
#address-cells = <1>;
#size-cells = <1>;
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
intel,actl-addr = <0>;
intel,pirq-link = <8 8>;
intel,pirq-mask = <0xdee0>;
intel,pirq-routing = <
/* BayTrail PCI devices */
PCI_BDF(0, 2, 0) INTA PIRQA
PCI_BDF(0, 3, 0) INTA PIRQA
PCI_BDF(0, 16, 0) INTA PIRQA
PCI_BDF(0, 17, 0) INTA PIRQA
PCI_BDF(0, 18, 0) INTA PIRQA
PCI_BDF(0, 19, 0) INTA PIRQA
PCI_BDF(0, 20, 0) INTA PIRQA
PCI_BDF(0, 21, 0) INTA PIRQA
PCI_BDF(0, 22, 0) INTA PIRQA
PCI_BDF(0, 23, 0) INTA PIRQA
PCI_BDF(0, 24, 0) INTA PIRQA
PCI_BDF(0, 24, 1) INTC PIRQC
PCI_BDF(0, 24, 2) INTD PIRQD
PCI_BDF(0, 24, 3) INTB PIRQB
PCI_BDF(0, 24, 4) INTA PIRQA
PCI_BDF(0, 24, 5) INTC PIRQC
PCI_BDF(0, 24, 6) INTD PIRQD
PCI_BDF(0, 24, 7) INTB PIRQB
PCI_BDF(0, 26, 0) INTA PIRQA
PCI_BDF(0, 27, 0) INTA PIRQA
PCI_BDF(0, 28, 0) INTA PIRQA
PCI_BDF(0, 28, 1) INTB PIRQB
PCI_BDF(0, 28, 2) INTC PIRQC
PCI_BDF(0, 28, 3) INTD PIRQD
PCI_BDF(0, 29, 0) INTA PIRQA
PCI_BDF(0, 30, 0) INTA PIRQA
PCI_BDF(0, 30, 1) INTD PIRQD
PCI_BDF(0, 30, 2) INTB PIRQB
PCI_BDF(0, 30, 3) INTC PIRQC
PCI_BDF(0, 30, 4) INTD PIRQD
PCI_BDF(0, 30, 5) INTB PIRQB
PCI_BDF(0, 31, 3) INTB PIRQB
/*
* PCIe root ports downstream
* interrupts
*/
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(1, 0, 0) INTB PIRQB
PCI_BDF(1, 0, 0) INTC PIRQC
PCI_BDF(1, 0, 0) INTD PIRQD
PCI_BDF(2, 0, 0) INTA PIRQB
PCI_BDF(2, 0, 0) INTB PIRQC
PCI_BDF(2, 0, 0) INTC PIRQD
PCI_BDF(2, 0, 0) INTD PIRQA
PCI_BDF(3, 0, 0) INTA PIRQC
PCI_BDF(3, 0, 0) INTB PIRQD
PCI_BDF(3, 0, 0) INTC PIRQA
PCI_BDF(3, 0, 0) INTD PIRQB
PCI_BDF(4, 0, 0) INTA PIRQD
PCI_BDF(4, 0, 0) INTB PIRQA
PCI_BDF(4, 0, 0) INTC PIRQB
PCI_BDF(4, 0, 0) INTD PIRQC
>;
};
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "macronix,mx25l6405d",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
};
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x20>;
bank-name = "C";
};
gpiod {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x60 0x20>;
bank-name = "D";
};
gpioe {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x80 0x20>;
bank-name = "E";
};
gpiof {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0xA0 0x20>;
bank-name = "F";
};
};
};
fsp {
compatible = "intel,baytrail-fsp";
fsp,mrc-init-tseg-size = <0>;
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <1>;
fsp,enable-azalia;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
fsp,enable-i2c1;
fsp,enable-i2c2;
fsp,enable-i2c3;
fsp,enable-i2c4;
fsp,enable-i2c5;
fsp,enable-i2c6;
fsp,enable-pwm0;
fsp,enable-pwm1;
fsp,igd-dvmt50-pre-alloc = <2>;
fsp,aperture-size = <2>;
fsp,gtt-size = <2>;
fsp,scc-enable-pci-mode;
fsp,os-selection = <4>;
fsp,enable-igd;
fsp,serial-debug-port-address = <0x3f8>;
fsp,serial-debug-port-type = <1>;
};
microcode {
update@0 {
#include "microcode/m0130673325.dtsi"
};
update@1 {
#include "microcode/m0130679907.dtsi"
};
};
};

19
arch/x86/include/asm/acpi/global_nvs.h Normal file
View File

@ -0,0 +1,19 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ACPI_GNVS_H_
#define _ACPI_GNVS_H_
/*
* This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and
* ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
* to declare the GNVS OperationRegion, as well as write_acpi_tables()
* for the GNVS address runtime fix up.
*/
#define ACPI_GNVS_ADDR 0xdeadbeef
#define ACPI_GNVS_SIZE 0x100
#endif /* _ACPI_GNVS_H_ */

4
arch/x86/include/asm/acpi_table.h
View File

@ -299,6 +299,9 @@ struct acpi_mcfg_mmconfig {
/* PM1_CNT bit defines */
#define PM1_CNT_SCI_EN (1 << 0)
/* ACPI global NVS structure */
struct acpi_global_nvs;
/* These can be used by the target port */
void acpi_fill_header(struct acpi_table_header *header, char *signature);
@ -312,4 +315,5 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
u32 acpi_fill_madt(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
u32 write_acpi_tables(u32 start);

15
arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl Normal file
View File

@ -0,0 +1,15 @@
/*
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/acpi/global_nvs.h>
OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
Field(GNVS, ByteAcc, NoLock, Preserve)
{
Offset (0x00),
PCNT, 8, /* processor count */
IURE, 8, /* internal UART enabled */
}

19
arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
View File

@ -119,17 +119,14 @@ Device (LPCB)
Method(_STA, 0, Serialized)
{
/*
* TODO:
*
* Need to hide the internal UART depending on whether
* internal UART is enabled or not so that external
* SuperIO UART can be exposed to system.
*/
Store(1, UI3E)
Store(1, UI4E)
Store(1, C1EN)
Return (STA_VISIBLE)
If (LEqual(IURE, 1)) {
Store(1, UI3E)
Store(1, UI4E)
Store(1, C1EN)
Return (STA_VISIBLE)
} Else {
Return (STA_MISSING)
}
}

3
arch/x86/include/asm/arch-baytrail/acpi/platform.asl
View File

@ -22,6 +22,9 @@ Method(_WAK, 1)
Return (Package() {0, 0})
}
/* ACPI global NVS */
#include "global_nvs.asl"
/* TODO: add CPU ASL support */
Scope (\_SB)

21
arch/x86/include/asm/arch-baytrail/global_nvs.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _GLOBAL_NVS_H_
#define _GLOBAL_NVS_H_
struct __packed acpi_global_nvs {
u8 pcnt; /* processor count */
u8 iuart_en; /* internal UART enabled */
/*
* Add padding so sizeof(struct acpi_global_nvs) == 0x100.
* This must match the size defined in the global_nvs.asl.
*/
u8 rsvd[254];
};
#endif /* _GLOBAL_NVS_H_ */

14
arch/x86/include/asm/arch-quark/acpi/global_nvs.asl Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/acpi/global_nvs.h>
OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
Field(GNVS, ByteAcc, NoLock, Preserve)
{
Offset (0x00),
PCNT, 8, /* processor count */
}

3
arch/x86/include/asm/arch-quark/acpi/platform.asl
View File

@ -22,6 +22,9 @@ Method(_WAK, 1)
Return (Package() {0, 0})
}
/* ACPI global NVS */
#include "global_nvs.asl"
/* TODO: add CPU ASL support */
Scope (\_SB)

20
arch/x86/include/asm/arch-quark/global_nvs.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _GLOBAL_NVS_H_
#define _GLOBAL_NVS_H_
struct __packed acpi_global_nvs {
u8 pcnt; /* processor count */
/*
* Add padding so sizeof(struct acpi_global_nvs) == 0x100.
* This must match the size defined in the global_nvs.asl.
*/
u8 rsvd[255];
};
#endif /* _GLOBAL_NVS_H_ */

22
arch/x86/lib/acpi_table.c
View File

@ -11,10 +11,12 @@
#include <cpu.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <asm/acpi/global_nvs.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
/*
* IASL compiles the dsdt entries and writes the hex values
@ -336,6 +338,7 @@ u32 write_acpi_tables(u32 start)
struct acpi_fadt *fadt;
struct acpi_mcfg *mcfg;
struct acpi_madt *madt;
int i;
current = start;
@ -383,6 +386,25 @@ u32 write_acpi_tables(u32 start)
current += dsdt->length - sizeof(struct acpi_table_header);
current = ALIGN(current, 16);
/* Pack GNVS into the ACPI table area */
for (i = 0; i < dsdt->length; i++) {
u32 *gnvs = (u32 *)((u32)dsdt + i);
if (*gnvs == ACPI_GNVS_ADDR) {
debug("Fix up global NVS in DSDT to 0x%08x\n", current);
*gnvs = current;
break;
}
}
/* Update DSDT checksum since we patched the GNVS address */
dsdt->checksum = 0;
dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
/* Fill in platform-specific global NVS variables */
acpi_create_gnvs((struct acpi_global_nvs *)current);
current += sizeof(struct acpi_global_nvs);
current = ALIGN(current, 16);
debug("ACPI: * FADT\n");
fadt = (struct acpi_fadt *)current;
current += sizeof(struct acpi_fadt);

2
arch/x86/lib/fsp/fsp_support.c
View File

@ -110,7 +110,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
struct upd_region *fsp_upd;
#endif
#ifdef CONFIG_DEBUG_UART
#ifdef CONFIG_INTERNAL_UART
setup_internal_uart(1);
#endif

28
board/advantech/Kconfig Normal file
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@ -0,0 +1,28 @@
if VENDOR_ADVANTECH
choice
prompt "Mainboard model"
optional
config TARGET_SOM_DB5800_SOM_6867
bool "Advantech SOM-DB5800 & SOM-6867"
help
Advantech SOM-DB5800 COM Express development board with SOM-6867
installed.
SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
Atom E3845 or Celeron N2920 processor.
SOM-DB5800 is a COM Express Development board with:
10/100/1000 Ethernet
PCIe slots
4x USB ports
HDMI/DisplayPort/DVI, LVDS, VGA
SATA ports
ALC892 HD Audio Codec
endchoice
source "board/advantech/som-db5800-som-6867/Kconfig"
endif

3
board/advantech/som-db5800-som-6867/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
dsdt.aml
dsdt.asl.tmp
dsdt.c

28
board/advantech/som-db5800-som-6867/Kconfig Normal file
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@ -0,0 +1,28 @@
if TARGET_SOM_DB5800_SOM_6867
config SYS_BOARD
default "som-db5800-som-6867"
config SYS_VENDOR
default "advantech"
config SYS_SOC
default "baytrail"
config SYS_CONFIG_NAME
default "som-db5800-som-6867"
config SYS_TEXT_BASE
default 0xfff00000 if !EFI_STUB
default 0x01110000 if EFI_STUB
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
default 0xe0000000
endif

7
board/advantech/som-db5800-som-6867/MAINTAINERS Normal file
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@ -0,0 +1,7 @@
Advantech SOM-DB5800-SOM-6867
M: George McCollister <george.mccollister@gmail.com>
S: Maintained
F: board/advantech/som-db5800-som-6867
F: include/configs/som-db5800-som-6867.h
F: configs/som-db5800-som-6867_defconfig
F: arch/x86/dts/baytrail_som-db5800-som-6867.dts

8
board/advantech/som-db5800-som-6867/Makefile Normal file
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@ -0,0 +1,8 @@
#
# Copyright (C) 2015, Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += som-db5800-som-6867.o start.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o

11
board/advantech/som-db5800-som-6867/acpi/mainboard.asl Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Power Button */
Device (PWRB)
{
Name(_HID, EISAID("PNP0C0C"))
}

14
board/advantech/som-db5800-som-6867/dsdt.asl Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
{
/* platform specific */
#include <asm/arch/acpi/platform.asl>
/* board specific */
#include "acpi/mainboard.asl"
}

24
board/advantech/som-db5800-som-6867/som-db5800-som-6867.c Normal file
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@ -0,0 +1,24 @@
/*
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
* Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int board_early_init_f(void)
{
/*
* The FSP enables the BayTrail internal legacy UART (again).
* Disable it again, so that the one on the EC can be used.
*/
setup_internal_uart(0);
return 0;
}
int arch_early_init_r(void)
{
return 0;
}

9
board/advantech/som-db5800-som-6867/start.S Normal file
View File

@ -0,0 +1,9 @@
/*
* Copyright (C) 2015, Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl early_board_init
early_board_init:
jmp early_board_init_ret

2
board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
View File

@ -12,6 +12,7 @@
int board_early_init_f(void)
{
#ifndef CONFIG_INTERNAL_UART
/*
* The FSP enables the BayTrail internal legacy UART (again).
* Disable it again, so that the Winbond one can be used.
@ -21,6 +22,7 @@ int board_early_init_f(void)
/* Enable the legacy UART in the Winbond W83627 Super IO chip */
winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
UART0_BASE, UART0_IRQ);
#endif
return 0;
}

1
configs/bayleybay_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
CONFIG_TARGET_BAYLEYBAY=y
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y

63
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig Normal file
View File

@ -0,0 +1,63 @@
CONFIG_X86=y
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_WINBOND_W83627=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_USE_PRIVATE_LIBGCC=y

1
configs/minnowmax_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y

61
configs/som-db5800-som-6867_defconfig Normal file
View File

@ -0,0 +1,61 @@
CONFIG_X86=y
CONFIG_VENDOR_ADVANTECH=y
CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
CONFIG_TARGET_SOM_DB5800_SOM_6867=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_MMC is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y

2
doc/README.x86
View File

@ -1020,8 +1020,6 @@ Features not supported so far (to make it a complete ACPI solution):
* S3 (Suspend to RAM), S4 (Suspend to Disk).
Features that are optional:
* ACPI global NVS support. We may need it to simplify ASL code logic if
utilizing NVS variables. Most likely we will need this sooner or later.
* Dynamic AML bytecodes insertion at run-time. We may need this to support
SSDT table generation and DSDT fix up.
* SMI support. Since U-Boot is a modern bootloader, we don't want to bring

11
drivers/pci/pci_rom.c
View File

@ -39,14 +39,9 @@ __weak bool board_should_run_oprom(struct udevice *dev)
return true;
}
static bool should_load_oprom(struct udevice *dev)
__weak bool board_should_load_oprom(struct udevice *dev)
{
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
return 1;
if (board_should_run_oprom(dev))
return 1;
return 0;
return true;
}
__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
@ -278,7 +273,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
return -ENODEV;
}
if (!should_load_oprom(dev))
if (!board_should_load_oprom(dev))
return -ENXIO;
ret = pci_rom_probe(dev, &rom);

36
include/configs/som-db5800-som-6867.h Normal file
View File

@ -0,0 +1,36 @@
/*
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ef000
#endif /* __CONFIG_H */