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Amazon Kindle Fire (first generation) codename kc1 support

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The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.

It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This commit is contained in:
Paul Kocialkowski 2016-02-27 19:19:00 +01:00 committed by Tom Rini
parent 14689ad79e
commit ae51b5709e
8 changed files with 474 additions and 0 deletions
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4
arch/arm/cpu/armv7/omap4/Kconfig
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@ -13,6 +13,9 @@ config TARGET_OMAP4_PANDA
config TARGET_OMAP4_SDP4430
bool "TI OMAP4 SDP4430"
config TARGET_KC1
bool "Amazon Kindle Fire (first generation)"
endchoice
config SYS_SOC
@ -21,5 +24,6 @@ config SYS_SOC
source "board/gumstix/duovero/Kconfig"
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
source "board/amazon/kc1/Kconfig"
endif

12
board/amazon/kc1/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_KC1
config SYS_BOARD
default "kc1"
config SYS_VENDOR
default "amazon"
config SYS_CONFIG_NAME
default "kc1"
endif

6
board/amazon/kc1/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
KC1 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: board/amazon/kc1/
F: include/configs/kc1.h
F: configs/kc1_defconfig

9
board/amazon/kc1/Makefile Normal file
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@ -0,0 +1,9 @@
#
# Amazon Kindle Fire (first generation) codename kc1 config
#
# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := kc1.o

109
board/amazon/kc1/kc1.c Normal file
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@ -0,0 +1,109 @@
/*
* Amazon Kindle Fire (first generation) codename kc1 config
*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <twl6030.h>
#include "kc1.h"
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
.board_string = "kc1"
};
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array,
sizeof(core_padconf_array) / sizeof(struct pad_conf_entry));
}
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
if (cs == CS1)
return NULL;
*lpddr2_dev_details = elpida_2G_S4_details;
return lpddr2_dev_details;
}
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
*cs0_device_timings = &elpida_2G_S4_timings;
*cs1_device_timings = NULL;
}
int board_init(void)
{
/* GPMC init */
gpmc_init();
/* MACH number */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
/* ATAGs location */
gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100;
return 0;
}
int misc_init_r(void)
{
/* Serial number */
omap_die_id_serial();
return 0;
}
u32 get_board_rev(void)
{
u32 value = 0;
gpio_request(KC1_GPIO_MBID0, "MBID0");
gpio_request(KC1_GPIO_MBID1, "MBID1");
gpio_request(KC1_GPIO_MBID2, "MBID2");
gpio_request(KC1_GPIO_MBID3, "MBID3");
gpio_direction_input(KC1_GPIO_MBID0);
gpio_direction_input(KC1_GPIO_MBID1);
gpio_direction_input(KC1_GPIO_MBID2);
gpio_direction_input(KC1_GPIO_MBID3);
value |= (gpio_get_value(KC1_GPIO_MBID0) << 0);
value |= (gpio_get_value(KC1_GPIO_MBID1) << 1);
value |= (gpio_get_value(KC1_GPIO_MBID2) << 2);
value |= (gpio_get_value(KC1_GPIO_MBID3) << 3);
return value;
}
void get_board_serial(struct tag_serialnr *serialnr)
{
omap_die_id_get_board_serial(serialnr);
}
#ifndef CONFIG_SPL_BUILD
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif
void board_mmc_power_init(void)
{
twl6030_power_mmc_init(1);
}

92
board/amazon/kc1/kc1.h Normal file
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@ -0,0 +1,92 @@
/*
* Amazon Kindle Fire (first generation) codename kc1 config
*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _KC1_H_
#define _KC1_H_
#include <asm/arch/mux_omap4.h>
#define KC1_GPIO_MBID1 173
#define KC1_GPIO_MBID0 174
#define KC1_GPIO_MBID3 177
#define KC1_GPIO_MBID2 178
const struct pad_conf_entry core_padconf_array[] = {
/* GPMC */
{ GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
{ GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
{ GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
{ GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
{ GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
{ GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
{ GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
{ GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
{ GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
{ GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
/* CAM */
{ CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
{ CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
{ CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
/* HDQ */
{ HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
/* I2C1 */
{ I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */
{ I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */
/* I2C2 */
{ I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */
{ I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */
/* I2C3 */
{ I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */
{ I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */
/* I2C4 */
{ I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */
{ I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */
/* MCSPI1 */
{ MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
{ MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */
/* UART3 */
{ UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */
{ UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */
{ UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */
{ UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */
/* SDMMC5 */
{ SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */
{ SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */
{ SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */
{ SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */
{ SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */
{ SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */
/* MCSPI4 */
{ MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */
{ MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */
{ MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */
{ MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */
/* UART4 */
{ UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */
{ UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */
/* UNIPRO */
{ UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
{ UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
{ UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
{ UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
{ UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
{ UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
{ UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */
{ UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */
};
#endif

12
configs/kc1_defconfig Normal file
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@ -0,0 +1,12 @@
CONFIG_ARM=y
CONFIG_OMAP44XX=y
CONFIG_TARGET_KC1=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="kc1 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y

230
include/configs/kc1.h Normal file
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@ -0,0 +1,230 @@
/*
* Amazon Kindle Fire (first generation) codename kc1 config
*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
/*
* Build
*/
#define CONFIG_SYS_THUMB_BUILD
/*
* CPU
*/
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Platform
*/
#define CONFIG_OMAP
#define CONFIG_OMAP4430
#define CONFIG_OMAP_COMMON
/*
* Board
*/
#define CONFIG_MISC_INIT_R
/*
* Clocks
*/
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_SYS_PTV 2
/*
* DRAM
*/
#define CONFIG_NR_DRAM_BANKS 1
/*
* Memory
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
/*
* GPIO
*/
#define CONFIG_OMAP_GPIO
/*
* I2C
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_CMD_I2C
/*
* Flash
*/
#define CONFIG_SYS_NO_FLASH
/*
* MMC
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
/*
* Power
*/
#define CONFIG_TWL6030_POWER
/*
* Partitions
*/
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
/*
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (48 * 1024)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
/*
* Console
*/
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+ 16)
/*
* Serial
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
/*
* Environment
*/
#define CONFIG_ENV_SIZE (128 * 1024)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x82000000\0" \
"loadaddr=0x82000000\0" \
"fdt_addr_r=0x88000000\0" \
"fdtaddr=0x88000000\0" \
"ramdisk_addr_r=0x88080000\0" \
"pxefile_addr_r=0x80100000\0" \
"scriptaddr=0x80000000\0" \
"bootm_size=0x10000000\0" \
"boot_mmc_dev=0\0" \
"kernel_mmc_part=7\0" \
"recovery_mmc_part=5\0" \
"bootargs=mem=512M console=ttyO2\0"
/*
* ATAGs
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG
/*
* Boot
*/
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_BOOTCOMMAND \
"setenv boot_mmc_part ${kernel_mmc_part}; " \
"part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
"part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
"mmc dev ${boot_mmc_dev}; " \
"mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
"bootm ${kernel_addr_r};"
/*
* Defaults
*/
#include <config_defaults.h>
#include <config_distro_defaults.h>
#endif