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armv8: fsl-layerscape: properly configure qdma ICID

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The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Laurentiu Tudor 2018-12-12 13:45:51 +02:00 committed by York Sun
parent 7a0425dd96
commit a954f6fe70
2 changed files with 6 additions and 1 deletions
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6
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob);
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_QDMA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, dma_icid,\
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
QDMA_BASE_ADDR), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -94,6 +94,7 @@
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
#define QMAN_CQSIDR_REG 0x20a80
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL