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dts: zynq: Add zynq spi controller nodes

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This patch adds zynq spi controller nodes in zynq-7000.dtsi.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Jagan Teki 2015-06-27 00:51:33 +05:30
parent 9f7a45020b
commit a8a8fc9cee
2 changed files with 51 additions and 0 deletions
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24
arch/arm/dts/zynq-7000.dtsi
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@ -109,6 +109,30 @@
interrupts = <0 50 4>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;

27
doc/device-tree-bindings/spi/spi-zynq.txt Normal file
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@ -0,0 +1,27 @@
Zynq SPI controller Device Tree Bindings
----------------------------------------
Required properties:
- compatible : Should be "xlnx,spi-zynq".
- reg : Physical base address and size of SPI registers map.
- status : Status will be disabled in dtsi and enabled in required dts.
- interrupt-parent : Must be core interrupt controller.
- interrupts : Property with a value describing the interrupt
number.
- clocks : Clock phandles (see clock bindings for details).
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
Example:
spi@e0006000 {
compatible = "xlnx,zynq-spi";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
} ;