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Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

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This reverts commit 57897c13de.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Vignesh R 2018-01-24 10:44:06 +05:30 committed by Jagan Teki
parent 948ad4f075
commit a743e2ba38
4 changed files with 6 additions and 23 deletions
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26
drivers/spi/cadence_qspi_apb.c
View File

@ -30,7 +30,6 @@
#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
#include <bouncebuf.h>
#include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */
@ -722,17 +721,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int remaining = n_tx;
unsigned int write_bytes;
int ret;
struct bounce_buffer bb;
u8 *bb_txbuf;
/*
* Handle non-4-byte aligned accesses via bounce buffer to
* avoid data abort.
*/
ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
if (ret)
return ret;
bb_txbuf = bb.bounce_buffer;
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
@ -743,11 +731,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
if (write_bytes % 4)
writesb(plat->ahbbase,
bb_txbuf + rounddown(write_bytes, 4),
write_bytes % 4);
/* Handle non-4-byte aligned access to avoid data abort. */
if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
writesb(plat->ahbbase, txbuf, write_bytes);
else
writesl(plat->ahbbase, txbuf, write_bytes >> 2);
ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
@ -757,7 +745,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
goto failwr;
}
bb_txbuf += write_bytes;
txbuf += write_bytes;
remaining -= write_bytes;
}
@ -768,7 +756,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
bounce_buffer_stop(&bb);
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
@ -779,7 +766,6 @@ failwr:
/* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
bounce_buffer_stop(&bb);
return ret;
}

1
include/configs/k2g_evm.h
View File

@ -93,7 +93,6 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_REF_CLK 384000000
#define CONFIG_BOUNCE_BUFFER
#endif
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS

1
include/configs/socfpga_common.h
View File

@ -184,7 +184,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_BOUNCE_BUFFER
/*
* Designware SPI support

1
include/configs/stv0991.h
View File

@ -64,7 +64,6 @@
+ */
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
#define CONFIG_BOUNCE_BUFFER
#endif