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fpga: zynqpl: Check fpga config completion

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This patch checks fpga config completion when a bitstream is loaded
into PL.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy
2019-03-12 20:20:20 +05:30
committed by Michal Simek
parent 8658eadb39
commit a3d1bdb137
1 changed files with 13 additions and 13 deletions
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26
drivers/fpga/zynqpl.c
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@@ -548,22 +548,22 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
return FPGA_FAIL; return FPGA_FAIL;
isr_status = readl(&devcfg_base->int_sts); if (bstype == BIT_FULL) {
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts); isr_status = readl(&devcfg_base->int_sts);
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
printf("%s: FPGA config done\n", __func__);
zynq_slcr_devcfg_enable();
} }
printf("%s: FPGA config done\n", __func__);
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS; return FPGA_SUCCESS;
} }
#endif #endif