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fpga: zynqpl: Add bstype argument to zynq_decrypt_load()

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This patch adds 'bstype' argument to zynq_decrypt_load() to specify whether
the input source is a bitstream/non-bitstream/partial bitstream image.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy
2019-03-12 20:20:19 +05:30
committed by Michal Simek
parent b266b3847f
commit 8658eadb39
3 changed files with 10 additions and 5 deletions
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7
board/xilinx/zynq/cmds.c
View File

@@ -396,7 +396,8 @@ static int zynq_verify_image(u32 src_ptr)
status = zynq_decrypt_load(part_load_addr,
part_img_len,
part_dst_addr,
part_data_len);
part_data_len,
BIT_NONE);
if (status != 0) {
printf("DECRYPTION_FAIL\n");
return -1;
@@ -431,6 +432,7 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
char *endp;
u32 srcaddr, srclen, dstaddr, dstlen;
int status;
u8 imgtype = BIT_NONE;
srcaddr = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
@@ -454,7 +456,8 @@ static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
if (dstlen % 4)
dstlen = roundup(dstlen, 4);
status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
dstlen >> 2, imgtype);
if (status != 0)
return CMD_RET_FAILURE;

5
drivers/fpga/zynqpl.c
View File

@@ -505,7 +505,8 @@ struct xilinx_fpga_op zynq_op = {
* Load the encrypted image from src addr and decrypt the image and
* place it back the decrypted image into dstaddr.
*/
int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
u8 bstype)
{
u32 isr_status, ts;
@@ -522,7 +523,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
return FPGA_FAIL;
}
if (zynq_dma_xfer_init(BIT_NONE)) {
if (zynq_dma_xfer_init(bstype)) {
printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
return FPGA_FAIL;
}

3
include/zynqpl.h
View File

@@ -12,7 +12,8 @@
#include <xilinx.h>
#ifdef CONFIG_CMD_ZYNQ_AES
int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
u8 bstype);
#endif
extern struct xilinx_fpga_op zynq_op;