leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge git://git.denx.de/u-boot-fsl-qoriq

Browse Source 
Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2 support on sl28
powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile
Bug fixes and updates for keymile, Kontron
This commit is contained in:
Tom Rini
2021-02-08 10:55:28 -05:00
parent 88262788fe 5e7a207ebf
commit a10d06add7
183 changed files with 3894 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/keymile/Kconfig
View File

@@ -114,6 +114,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
Page size of inventory in EEPROM.
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"

29
board/keymile/common/common.c
View File

@@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int set_km_env(void)
{
uchar buf[32];
unsigned int pnvramaddr;
unsigned int pram;
unsigned int varaddr;
@@ -49,10 +48,9 @@ int set_km_env(void)
char *p;
unsigned long rootfssize = 0;
pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
- CONFIG_KM_PNVRAM;
sprintf((char *)buf, "0x%x", pnvramaddr);
env_set("pnvramaddr", (char *)buf);
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
env_set_hex("pnvramaddr", pnvramaddr);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@@ -60,16 +58,14 @@ int set_km_env(void)
strict_strtoul(p, 16, &rootfssize);
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
sprintf((char *)buf, "0x%x", pram);
env_set("pram", (char *)buf);
env_set_ulong("pram", pram);
varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
sprintf((char *)buf, "0x%x", varaddr);
env_set("varaddr", (char *)buf);
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
kernelmem = gd->ram_size - 0x400 * pram;
sprintf((char *)buf, "0x%x", kernelmem);
env_set("kernelmem", (char *)buf);
env_set_hex("kernelmem", kernelmem);
return 0;
}
@@ -243,7 +239,6 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc,
p = env_get("hwkey");
if (p)
rc = strict_strtoul(p, 16, &envhwkey);
if (rc != 0) {
printf("strict_strtoul returns error: %d", rc);
return rc;
@@ -305,15 +300,11 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc,
* set the values in environment variables.
*/
if (bid == ivmbid && hwkey == ivmhwkey) {
char buf[10];
found = 1;
envbid = bid;
envhwkey = hwkey;
sprintf(buf, "%lx", bid);
env_set("boardid", buf);
sprintf(buf, "%lx", hwkey);
env_set("hwkey", buf);
env_set_hex("boardid", bid);
env_set_hex("hwkey", hwkey);
}
} /* end while( ! found ) */
}

5
board/keymile/common/common.h
View File

@@ -136,6 +136,11 @@ int set_km_env(void);
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
int i2c_soft_read_pin(void);
int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */

5
board/keymile/common/ivm.c
View File

@@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
}
if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
/* 3rd ethernet interface */
process_mac(valbuf, page2, 2, true);
env_set((char *)"eth4addr", (char *)valbuf);
}
return 0;
}

19
board/keymile/common/qrio.c
View File

@@ -5,15 +5,28 @@
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include "common.h"
#include "qrio.h"
/* QRIO ID register offset */
#define ID_REV_OFF 0x00
/* QRIO GPIO register offsets */
#define DIRECT_OFF 0x18
#define GPRT_OFF 0x1c
void show_qrio(void)
{
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
printf("QRIO: id = %u, revision = %u\n",
(id_rev >> 8) & 0xff, id_rev & 0xff);
}
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
@@ -129,7 +142,7 @@ void qrio_prst(u8 bit, bool en, bool wden)
void qrio_prstcfg(u8 bit, u8 mode)
{
u32 prstcfg;
unsigned long prstcfg;
u8 i;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
@@ -137,9 +150,9 @@ void qrio_prstcfg(u8 bit, u8 mode)
for (i = 0; i < 2; i++) {
if (mode & (1 << i))
set_bit(2 * bit + i, &prstcfg);
__set_bit(2 * bit + i, &prstcfg);
else
clear_bit(2 * bit + i, &prstcfg);
__clear_bit(2 * bit + i, &prstcfg);
}
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);

1
board/keymile/common/qrio.h
View File

@@ -11,6 +11,7 @@
#define QRIO_GPIO_A 0x40
#define QRIO_GPIO_B 0x60
void show_qrio(void);
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);

17
board/keymile/kmcent2/Kconfig Normal file
View File

@@ -0,0 +1,17 @@
if TARGET_KMCENT2
config SYS_BOARD
default "kmcent2"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmcent2"
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_T1040
select PHYS_64BIT
endif

8
board/keymile/kmcent2/MAINTAINERS Normal file
View File

@@ -0,0 +1,8 @@
KMCENT2 BOARD
M: Niel Fourie <lusus@denx.de>
S: Maintained
F: board/keymile/kmcent2/
F: include/configs/kmcent2.h
F: configs/kmcent2_defconfig
F: arch/powerpc/dts/kmcent2.dts
F: arch/powerpc/dts/kmcent2-u-boot.dtsi

14
board/keymile/kmcent2/Makefile Normal file
View File

@@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2016 Keymile AG
# Rainer Boschung <rainer.boschung@keymile.com>
#
# Copyright 2013 Freescale Semiconductor, Inc.
#
obj-y += kmcent2.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
obj-y += ../common/common.o
obj-y += ../common/ivm.o
obj-y += ../common/qrio.o

88
board/keymile/kmcent2/ddr.c Normal file
View File

@@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/fsl_law.h>
#include <asm/mmu.h>
#include <asm/mpc85xx_gpio.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <hwconfig.h>
#include <i2c.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
#define DQSn_START(n, start) ((start) << DQSn_POS(n))
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
{
if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
/* 1/2 clk delay between wr command and data strobe */
popts->write_data_delay = 4;
/* clk lauched 1/2 applied cylcle after address command */
popts->clk_adjust = 4;
/* 1T timing: command/address held for only 1 cycle */
popts->twot_en = 0;
popts->threet_en = 0;
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x3b;
/* we have only one module, half str should be OK */
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
/* set for DDR3-1600 */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x7;
/* DQS write leveling start time according layout */
popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
DQSn_START(2, 0x06) |
DQSn_START(3, 0x07) |
DQSn_START(4, 0x07));
popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
DQSn_START(6, 0x08) |
DQSn_START(7, 0x08) |
DQSn_START(8, 0x08));
/*
* rtt and wtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
int dram_init(void)
{
phys_size_t dram_size;
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
gd->ram_size = dram_size;
return 0;
}

353
board/keymile/kmcent2/kmcent2.c Normal file
View File

@@ -0,0 +1,353 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/cache.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_liodn.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <fdt_support.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <image.h>
#include <linux/compiler.h>
#include <net.h>
#include <netdev.h>
#include <vsc9953.h>
#include "../common/common.h"
#include "../common/qrio.h"
DECLARE_GLOBAL_DATA_PTR;
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
{
printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
return 0;
}
#define RSTRQSR1_WDT_RR 0x00200000
#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
bool cpuwd_flag = false;
/* board specific IFC configuration: increased bus turnaround time */
setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
/* configure mode for uP reset request */
qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
setbits_be32(&gur->ddrclkdr, 0x40000000);
/* set reset reason according CPU register */
if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
RSTRQSR1_WDT_RR)
cpuwd_flag = true;
qrio_cpuwd_flag(cpuwd_flag);
/* clear CPU bits by writing 1 */
setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
/* configure PRST lines for the application: */
/*
* ETHSW_DDR_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_ETHSW_DDR_RST, true);
/*
* XES_PHY_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_XES_PHY_RST, true);
/*
* ES_PHY_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_ES_PHY_RST, true);
/*
* EFE_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_EFE_RST, true);
/*
* BFTIC4_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_BFTIC4_RST, true);
/*
* DPAXE_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_DPAXE_RST, true);
/*
* PEXSW_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_PEXSW_RST, false, false);
/*
* PEXSW_NT_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_PEXSW_NT_RST, false, false);
/*
* BOBCAT_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_BOBCAT_RST, false, false);
/*
* FEMT_RST:
* reset at power-up and unit reset only and enable WD
*/
qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_FEMT_RST, true);
/*
* FOAM_RST:
* reset at power-up and unit reset only and enable WD
*/
qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_FOAM_RST, true);
return 0;
}
int board_early_init_r(void)
{
int ret = 0;
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
setup_qbman_portals();
qrio_set_leds();
/* enable Application Buffer */
qrio_enable_app_buffer();
return ret;
}
unsigned long get_serial_clock(unsigned long dummy)
{
return (gd->bus_clk / 2);
}
unsigned long get_board_sys_clk(unsigned long dummy)
{
return 66666666;
}
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
/*
* CFE_RST (front phy):
* reset at power-up, unit and core reset, deasset reset w/o WD
*/
qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_CFE_RST, false, false);
/*
* ZL30158_RST (PTP clock generator):
* reset at power-up only, deassert reset and enable WD on it
*/
qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
qrio_prst(KM_ZL30158_RST, false, false);
/*
* ZL30364_RST (EEC generator):
* reset at power-up only, deassert reset and enable WD on it
*/
qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
qrio_prst(KM_ZL30364_RST, false, false);
return 0;
}
#define USED_SRDS_BANK 0
#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
#define BRG01_IOCLK12 0x02000000
#define EC2_GTX_CLK125 0x08000000
int misc_init_r(void)
{
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* check SERDES bank 0 reference clock */
u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
if (actual & SRDS_PLLCR0_POFF)
printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
USED_SRDS_BANK,
serdes_clock_to_string(EXPECTED_SRDS_RFCK),
serdes_clock_to_string(actual));
}
/* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
out_be32(&scfg->qeioclkcr,
in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
/* Fix polarity of Card Detect and Write Protect */
out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
/*
* EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
* to EC2
*/
out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
return 0;
}
int hush_init_var(void)
{
ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
int last_stage_init(void)
{
const char *kmem;
/* DIP switch support on BFTIC */
struct bfticu_iomap *bftic4 =
(struct bfticu_iomap *)SYS_BFTIC_BASE;
u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {
/* start bootloader */
puts("DIP: Enabled\n");
env_set("actual_bank", "0");
}
set_km_env();
/*
* bootm_size is used to fixup the FDT memory node
* set it to kernelmem that has the same value
*/
kmem = env_get("kernelmem");
if (kmem)
env_set("bootm_size", kmem);
return 0;
}
void fdt_fixup_fman_mac_addresses(void *blob)
{
int node, ret;
char path[24];
unsigned char mac_addr[6];
/*
* Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
* get the mac addr from env
*/
if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
printf("eth4addr env variable not defined\n");
return;
}
/* local management port */
strcpy(path, "/soc/fman/ethernet@e8000");
node = fdt_path_offset(blob, path);
if (node < 0) {
printf("no %s\n", path);
return;
}
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("%s\n\terror setting local-mac-address property\n",
path);
}
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_liodn(blob);
fdt_fixup_fman_mac_addresses(blob);
if (hwconfig("qe-tdm"))
fdt_del_diu(blob);
return 0;
}
/* DIC26_SELFTEST GPIO used to start factory test sw */
#define SELFTEST_PORT QRIO_GPIO_A
#define SELFTEST_PIN 0
int post_hotkeys_pressed(void)
{
qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
}

23
board/keymile/kmcent2/law.c Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <asm/fsl_law.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */
};
int num_law_entries = ARRAY_SIZE(law_table);

104
board/keymile/kmcent2/tlb.c Normal file
View File

@@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
0, 2, BOOKE_PAGESZ_128M, 1),
/* *I*G* - PCI1 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI1 I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */
SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 11, BOOKE_PAGESZ_64K, 1),
/* MRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 12, BOOKE_PAGESZ_128M, 1),
/* BFTIC */
SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 13, BOOKE_PAGESZ_128M, 1),
/*
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so do not use them here!!.
*/
/* PAXE */
SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 16, BOOKE_PAGESZ_128M, 1)
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

2
board/kontron/sl28/Makefile
View File

@@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD
obj-y += sl28.o cmds.o
endif
obj-y += common.o ddr.o
obj-y += ddr.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o

10
board/kontron/sl28/common.c
View File

@@ -1,10 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/arch-fsl-layerscape/soc.h>
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}

6
board/kontron/sl28/sl28.c
View File

@@ -19,6 +19,12 @@
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}
int board_init(void)
{
if (CONFIG_IS_ENABLED(FSL_CAAM))

38
board/kontron/sl28/spl.c
View File

@@ -3,10 +3,36 @@
#include <common.h>
#include <asm/io.h>
#include <asm/spl.h>
#include <asm/arch-fsl-layerscape/fsl_serdes.h>
#include <asm/arch-fsl-layerscape/soc.h>
#define DCFG_RCWSR25 0x160
#define GPINFO_HW_VARIANT_MASK 0xff
#define SERDES_LNDGCR0 0x1ea08c0
#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
#define LNDGCR0_PROTS_SATA (0x2 << 7)
#define SERDES_LNDGCR1 0x1ea08c4
#define LNDGCR1_RDAT_INV BIT(31)
/*
* On this board the SMARC PCIe lane D might be switched to SATA mode. This
* makes sense if this lane is connected to a Mini PCI slot and a mSATA card
* is plugged in. In this case, the RX pair is swapped and we need to invert
* the received data.
*/
static void fixup_sata_rx_polarity(void)
{
u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
u32 tmp;
if (prot == LNDGCR0_PROTS_SATA) {
tmp = in_le32(SERDES_LNDGCR1);
tmp |= LNDGCR1_RDAT_INV;
out_le32(SERDES_LNDGCR1, tmp);
}
}
int sl28_variant(void)
{
return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
@@ -17,6 +43,10 @@ int board_fit_config_name_match(const char *name)
int variant = sl28_variant();
switch (variant) {
case 1:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
case 2:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
case 3:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
case 4:
@@ -30,3 +60,11 @@ void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_SPI;
}
int board_early_init_f(void)
{
fixup_sata_rx_polarity();
fsl_lsch3_early_init_f();
return 0;
}