From 5d867bcc2321041445ebb60d437b818bf706162f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 9 Dec 2020 10:53:25 +0100 Subject: [PATCH 01/61] mtd: spi-nor: add unlock all config option Provide an explicit configuration option to disable default "unlock all" of any flash chip which supports locking. It doesn't make sense to automatically unprotect the entire flash on each u-boot startup if the block protection bits are actually used. Traditionally, the unlock was there to be able to write to flash devices which powered-up with the block protection bits set. Over time this feature creeped into all flash devices which support locking. For a more detailed description and discussion see: https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/ Keep things simple in u-boot and just provide a configration option to disable this behavior which can be set per board. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/mtd/spi/Kconfig | 10 ++++++++++ drivers/mtd/spi/spi-nor-core.c | 9 +++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index ea444436ad..f8db8e5213 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -95,6 +95,16 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_UNLOCK_ALL + bool "Unlock the entire SPI flash on u-boot startup" + default y + help + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. + + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..ef426dac02 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2443,10 +2443,11 @@ static int spi_nor_init(struct spi_nor *nor) * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set */ - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || - JEDEC_MFR(nor->info) == SNOR_MFR_SST || - nor->info->flags & SPI_NOR_HAS_LOCK) { + if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) && + (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || + JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || + JEDEC_MFR(nor->info) == SNOR_MFR_SST || + nor->info->flags & SPI_NOR_HAS_LOCK)) { write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); From 46fdf763b8b316d1eec25977e6e7b8051e89e3fd Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 9 Dec 2020 10:53:26 +0100 Subject: [PATCH 02/61] board: kontron: disable flash unlock all Although the status register is protected by the hardware write protection, there is a hardware jumper to disable that hardware write protection. Thus if a user would set this jumper any u-boot start would disable the write protection altogether. Circumvent that by not disabling the write protection in the first place. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index c1a096799c..12720f343e 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -73,6 +73,7 @@ CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y From 64a0fb4cc35ced6ac83e4177889501782b51891d Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 9 Dec 2020 13:31:58 +0200 Subject: [PATCH 03/61] net: memac_phy: add a timeout to MDIO operations We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei Reviewed-by: Madalin Bucur [Rebased] Signed-off-by: Priyanka Jain --- drivers/net/fm/memac_phy.c | 76 +++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 18 deletions(-) diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 8bd32b0ab7..72b500a6d1 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -28,6 +28,8 @@ struct fm_mdio_priv { }; #endif +#define MAX_NUM_RETRIES 1000 + static u32 memac_in_32(u32 *reg) { #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -37,6 +39,42 @@ static u32 memac_in_32(u32 *reg) #endif } +/* + * Wait until the MDIO bus is free + */ +static int memac_wait_until_free(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO bus to be free\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * Wait till the MDIO read or write operation is complete + */ +static int memac_wait_until_done(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO operation to complete\n"); + return -ETIMEDOUT; + } + + return 0; +} + /* * Write value to the PHY for this device to the register at regnum, waiting * until the write is done before it returns. All PHY configuration has to be @@ -48,6 +86,7 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; /* Default to 10G interface */ + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -69,9 +108,9 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the port and dev addr */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -81,16 +120,16 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Write the value to the register */ memac_out_32(®s->mdio_data, MDIO_DATA(value)); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; return 0; } @@ -106,6 +145,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -129,9 +169,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the Port and Device Addrs */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -141,17 +181,17 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Initiate the read */ mdio_ctl |= MDIO_CTL_READ; memac_out_32(®s->mdio_ctl, mdio_ctl); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; /* Return all Fs if nothing was there */ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER) From 166e40bda614a212e6bfeeabb390c4827c1607ff Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Thu, 10 Dec 2020 11:02:47 +0800 Subject: [PATCH 04/61] configs: ls1088aqds: add COMMON_ENV to fix distroboot Add COMMON_ENV(kernelheader_addr_r, fdtheader_addr_r, kernel_addr_r, fdt_addr_r, load_addr) to fix a bug that failed to boot to ubuntu Failed log as follows, ## Executing script at 80000000 load - load binary file from a filesystemUsage: load [ [ [ [bytes [pos]]]]] - Load binary file filename from partition part on device type interface instance dev to address addr in memory. bytes gives the size to load in bytes. If bytes is 0 or omitted, the file is read until the end. pos gives the file byte position to start reading from. If pos is 0 or omitted, the file is read from the start. ... Bad Linux ARM64 Image magic! SCRIPT FAILED: continuing... Signed-off-by: Biwen Li [Updated description] Signed-off-by: Priyanka Jain --- include/configs/ls1088aqds.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b92ec14c69..1626e65056 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -371,10 +371,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) +#define COMMON_ENV \ + "kernelheader_addr_r=0x80200000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" + /* Initial environment variables */ #ifdef CONFIG_NXP_ESBC #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -406,6 +414,7 @@ unsigned long get_board_ddr_clk(void); #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -467,6 +476,7 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_QSPI_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -484,6 +494,7 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SD_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x800\0" \ @@ -501,6 +512,7 @@ unsigned long get_board_ddr_clk(void); #else /* NOR BOOT */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ From cbfa8f7c7ae9a31e664b088119588518abe7ac41 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 11 Dec 2020 14:26:51 +0530 Subject: [PATCH 05/61] armv8: lx2162aqds: disable non existing pcie controllers disable non existing pcie controllers on lx2162aqds Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2162a-qds.dts | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index b16526503d..a2592c990f 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -13,22 +13,20 @@ / { model = "NXP Layerscape LX2162AQDS Board"; compatible = "fsl,lx2162aqds", "fsl,lx2160a"; - - aliases { - pcie@3500000 { - status = "disabled"; - }; - - pcie@3800000 { - status = "disabled"; - }; - - pcie@3900000 { - status = "disabled"; - }; - }; }; &usb1 { status = "disabled"; }; + +&pcie2 { + status = "disabled"; +}; + +&pcie5 { + status = "disabled"; +}; + +&pcie6 { + status = "disabled"; +}; From 905c8e649e58a28a08086375ac3b16cbf32c793b Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 11 Dec 2020 17:31:39 +0800 Subject: [PATCH 06/61] armv8: dts: fsl-lx2162a: add dspi node into qds dts Add dspi node into lx2162aqds device tree Signed-off-by: Zhao Qiang [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/dts/fsl-lx2162a-qds.dts | 105 +++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index a2592c990f..341610ccf4 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -13,6 +13,12 @@ / { model = "NXP Layerscape LX2162AQDS Board"; compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + + aliases { + spi1 = &dspi0; + spi2 = &dspi1; + spi3 = &dspi2; + }; }; &usb1 { @@ -30,3 +36,102 @@ &pcie6 { status = "disabled"; }; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dflash3: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash4: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi2 { + bus-num = <0>; + status = "okay"; + + dflash6: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash7: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; From 440b28a8c6045865d7cc6c77ddf21058182e79a6 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 28 Dec 2020 20:15:10 +0800 Subject: [PATCH 07/61] net: eqos: Reduce the MDIO wait time Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li Reviewed-by: Fugang Duan Signed-off-by: Peng Fan Reviewed-by: Priyanka Jain --- drivers/net/dwc_eth_qos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 944412958d..e8242ca4e1 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_imx_ops = { struct eqos_config __maybe_unused eqos_imx_config = { .reg_access_always_ok = false, - .mdio_wait = 10000, + .mdio_wait = 10, .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, From feed9008b3e60414edb42aaaea76caf6fce88bf9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 8 Jan 2021 00:08:56 +0100 Subject: [PATCH 08/61] board: sl28: move ethernet aliases to variant specific dtsi The variants differ in their network configuration. Move the first two network aliases to the proper variant device tree includes. This is in prepartion for variant 1 and 2 support which has a different network port mapping. The network aliases for the two internal ports will stay in the common dtsi because they are present on all board variants. This might leave a hole if there is no ethernet1 alias. This is intended. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 2 -- arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 6 ++++++ arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 7 +++++++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 9b4e0298a7..84e974e84d 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -10,8 +10,6 @@ i2c1 = &i2c3; i2c2 = &i2c4; rtc0 = &rtc; - ethernet0 = &enetc0; - ethernet1 = &enetc1; ethernet2 = &enetc2; ethernet3 = &enetc6; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi index 79b771e074..879a76415b 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi @@ -1,2 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi index 79b771e074..fce4694682 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi @@ -1,2 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc0; + ethernet1 = &enetc1; + }; +}; From 4029d356e68c1d7d0061aa34065fd0598f98871f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 8 Jan 2021 00:08:57 +0100 Subject: [PATCH 09/61] board: sl28: add network variant 1 support This variant has one network port connected via RGMII and doesn't have any TSN capabilities out-of-the-box. Instead it has all four SerDes lanes available for customer use. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/Makefile | 1 + .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 33 ++++++++++- .../fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi | 8 +++ .../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 57 +++++++++++++++++++ board/kontron/sl28/spl.c | 2 + 5 files changed, 98 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 858b79ac97..882ea0274b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -438,6 +438,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1012a-frdm.dtb \ fsl-ls1012a-frwy.dtb dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ + fsl-ls1028a-kontron-sl28-var1.dtb \ fsl-ls1028a-kontron-sl28-var3.dtb \ fsl-ls1028a-kontron-sl28-var4.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 84e974e84d..585753c14d 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -50,6 +50,17 @@ }; fdt-2 { + description = "fsl-ls1028a-kontron-sl28-var1"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb"; + }; + }; + + fdt-3 { description = "fsl-ls1028a-kontron-sl28-var3"; type = "flat_dt"; arch = "arm"; @@ -60,7 +71,7 @@ }; }; - fdt-3 { + fdt-4 { description = "fsl-ls1028a-kontron-sl28-var4"; type = "flat_dt"; arch = "arm"; @@ -82,16 +93,23 @@ }; conf-2 { - description = "fsl-ls1028a-kontron-sl28-var3"; + description = "fsl-ls1028a-kontron-sl28-var1"; firmware = "uboot"; fdt = "fdt-2"; }; conf-3 { - description = "fsl-ls1028a-kontron-sl28-var4"; + description = "fsl-ls1028a-kontron-sl28-var3"; firmware = "uboot"; fdt = "fdt-3"; }; + + conf-4 { + description = "fsl-ls1028a-kontron-sl28-var4"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-4"; + }; }; }; }; @@ -131,6 +149,11 @@ firmware = "bl31"; loadables = "uboot"; }; + + conf-4 { + firmware = "bl31"; + loadables = "uboot"; + }; }; }; }; @@ -167,6 +190,10 @@ conf-3 { loadables = "uboot", "bl32"; }; + + conf-4 { + loadables = "uboot", "bl32"; + }; }; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi new file mode 100644 index 0000000000..98e8939369 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc1; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts new file mode 100644 index 0000000000..fe708bdbfa --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 1 which has one ethernet port. It is + * different than the base variant, which also has one port, but here the + * port is connected via RGMII. This port is not TSN aware. + * None of the four SerDes lanes are used by the module, instead they are + * all led out to the carrier for customer use. + * + * Copyright (C) 2020 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include + +/ { + model = "Kontron SMARC-sAL28 (4 Lanes)"; + compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc0 { + status = "disabled"; + /delete-property/ phy-handle; +}; + +&enetc1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/delete-node/ &phy0; +&mdio0 { + phy0: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; +}; diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index fa5829eee0..92f8342c45 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -17,6 +17,8 @@ int board_fit_config_name_match(const char *name) int variant = sl28_variant(); switch (variant) { + case 1: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var1"); case 3: return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); case 4: From b463010be067ba4b8ef9b7b80919f592a0f83bfb Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 8 Jan 2021 00:08:58 +0100 Subject: [PATCH 10/61] board: sl28: add network variant 2 support Although this variant has two external network ports, they are not (yet) supported by the bootloader because they are connected via an internal network switch. Otherwise its the same as the other variants. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/Makefile | 1 + .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 33 +++++++++++++++++-- .../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 2 ++ .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 25 ++++++++++++++ board/kontron/sl28/spl.c | 2 ++ 5 files changed, 60 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 882ea0274b..918af8c093 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -439,6 +439,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1012a-frwy.dtb dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ fsl-ls1028a-kontron-sl28-var1.dtb \ + fsl-ls1028a-kontron-sl28-var2.dtb \ fsl-ls1028a-kontron-sl28-var3.dtb \ fsl-ls1028a-kontron-sl28-var4.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 585753c14d..240178ab4e 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -61,6 +61,17 @@ }; fdt-3 { + description = "fsl-ls1028a-kontron-sl28-var2"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb"; + }; + }; + + fdt-4 { description = "fsl-ls1028a-kontron-sl28-var3"; type = "flat_dt"; arch = "arm"; @@ -71,7 +82,7 @@ }; }; - fdt-4 { + fdt-5 { description = "fsl-ls1028a-kontron-sl28-var4"; type = "flat_dt"; arch = "arm"; @@ -99,17 +110,24 @@ }; conf-3 { - description = "fsl-ls1028a-kontron-sl28-var3"; + description = "fsl-ls1028a-kontron-sl28-var2"; firmware = "uboot"; fdt = "fdt-3"; }; conf-4 { - description = "fsl-ls1028a-kontron-sl28-var4"; + description = "fsl-ls1028a-kontron-sl28-var3"; firmware = "uboot"; loadables = "uboot"; fdt = "fdt-4"; }; + + conf-5 { + description = "fsl-ls1028a-kontron-sl28-var4"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-5"; + }; }; }; }; @@ -154,6 +172,11 @@ firmware = "bl31"; loadables = "uboot"; }; + + conf-5 { + firmware = "bl31"; + loadables = "uboot"; + }; }; }; }; @@ -194,6 +217,10 @@ conf-4 { loadables = "uboot", "bl32"; }; + + conf-5 { + loadables = "uboot", "bl32"; + }; }; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi new file mode 100644 index 0000000000..79b771e074 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts new file mode 100644 index 0000000000..1ea1265bcf --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 2 which has no ethernet support in the + * bootloader. + * + * Copyright (C) 2020 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (TSN-on-module)"; + compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc0 { + status = "disabled"; + /delete-property/ phy-handle; +}; + +/delete-node/ &phy0; diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 92f8342c45..0ef67e2886 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -19,6 +19,8 @@ int board_fit_config_name_match(const char *name) switch (variant) { case 1: return strcmp(name, "fsl-ls1028a-kontron-sl28-var1"); + case 2: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var2"); case 3: return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); case 4: From 805b2423b45a4a9273cedcb73c01d900f7e8c77d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 8 Jan 2021 00:08:59 +0100 Subject: [PATCH 11/61] board: sl28: add SATA support Enable SATA support. Although not supported by the usual SATA pins on the SMARC baseboard connector, SATA mode is supported on a PCIe lane. This way one can use a mSATA card in a Mini PCI slot. We need to invert the received data because in this mode the polarity of the SerDes lane is swapped. Provide a fixup in board_early_init_f() for the SPL. board_early_init_f() is then not common between SPL and u-boot proper anymore, thus common.c is removed, as it just contained said function. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 4 +++ board/kontron/sl28/Makefile | 2 +- board/kontron/sl28/common.c | 10 ------- board/kontron/sl28/sl28.c | 6 ++++ board/kontron/sl28/spl.c | 34 +++++++++++++++++++++++ configs/kontron_sl28_defconfig | 1 + include/configs/kontron_sl28.h | 1 + 7 files changed, 47 insertions(+), 11 deletions(-) delete mode 100644 board/kontron/sl28/common.c diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts index 9561a58562..ea77a83d2f 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -172,6 +172,10 @@ }; }; +&sata { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile index 5d220f0744..147ef9872b 100644 --- a/board/kontron/sl28/Makefile +++ b/board/kontron/sl28/Makefile @@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD obj-y += sl28.o cmds.o endif -obj-y += common.o ddr.o +obj-y += ddr.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c deleted file mode 100644 index 14704f7051..0000000000 --- a/board/kontron/sl28/common.c +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 34f17b486b..28e8c4c954 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -19,6 +19,12 @@ DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} + int board_init(void) { if (CONFIG_IS_ENABLED(FSL_CAAM)) diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 0ef67e2886..0e6ad5f37e 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -3,10 +3,36 @@ #include #include #include +#include +#include #define DCFG_RCWSR25 0x160 #define GPINFO_HW_VARIANT_MASK 0xff +#define SERDES_LNDGCR0 0x1ea08c0 +#define LNDGCR0_PROTS_MASK GENMASK(11, 7) +#define LNDGCR0_PROTS_SATA (0x2 << 7) +#define SERDES_LNDGCR1 0x1ea08c4 +#define LNDGCR1_RDAT_INV BIT(31) + +/* + * On this board the SMARC PCIe lane D might be switched to SATA mode. This + * makes sense if this lane is connected to a Mini PCI slot and a mSATA card + * is plugged in. In this case, the RX pair is swapped and we need to invert + * the received data. + */ +static void fixup_sata_rx_polarity(void) +{ + u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK; + u32 tmp; + + if (prot == LNDGCR0_PROTS_SATA) { + tmp = in_le32(SERDES_LNDGCR1); + tmp |= LNDGCR1_RDAT_INV; + out_le32(SERDES_LNDGCR1, tmp); + } +} + int sl28_variant(void) { return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK; @@ -34,3 +60,11 @@ void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = BOOT_DEVICE_SPI; } + +int board_early_init_f(void) +{ + fixup_sata_rx_polarity(); + fsl_lsch3_early_init_f(); + + return 0; +} diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 12720f343e..1759d5e1b9 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -62,6 +62,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 442fb58b97..5d818a708d 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -93,6 +93,7 @@ func(MMC, mmc, 1) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ func(DHCP, dhcp, 0) \ func(PXE, pxe, 0) #include From 3dbc47c9e5351227c1cad36df77eefe9aeb6c555 Mon Sep 17 00:00:00 2001 From: Nipun Gupta Date: Tue, 12 Jan 2021 18:42:46 +0530 Subject: [PATCH 12/61] armv8: ls1028a: fix stream id allocation When A-050382 errata is enabled, ECAM and EDMA have conflicting stream id 40. This patch fixes the same. Signed-off-by: Nipun Gupta Reviewed-by: Laurentiu Tudor Reviewed-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 36f36699a7..b36b6d3889 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2020 NXP + * Copyright 2015-2021 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -103,7 +103,7 @@ #define FSL_DPAA2_STREAM_ID_END 63 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ -#define FSL_ECAM_STREAM_ID_START 32 +#define FSL_ECAM_STREAM_ID_START 41 #define FSL_ECAM_STREAM_ID_END 63 #define FSL_SEC_STREAM_ID 64 From 67477bd0ac67ffcc0ef871403968c78e32c480e9 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Wed, 13 Jan 2021 12:01:23 +0100 Subject: [PATCH 13/61] armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit Multiple LX2(LX2160A/LX2162A SoC) personality variants exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b24f38cac9..887954eaa5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -113,10 +113,13 @@ enum boot_src get_boot_src(void); #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#define SVR_WO_CE 0xFFFFEE +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) +#else +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #endif #ifdef CONFIG_ARCH_LS1028A #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) From b99cc27111be8d0732c3bb7b9f5ad3814904da38 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Wed, 13 Jan 2021 16:20:35 +0000 Subject: [PATCH 14/61] board: keymile: common: fix qrio compilation for arm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch is fixing qrio driver compilation for ARM architecture: - It includes asm/io.h for in_/out_ access - It use correct names for set/clear_bits as defined in linux/bitops.h Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/common/qrio.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 06a4e67881..d4e75f2850 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -5,6 +5,7 @@ */ #include +#include #include #include "common.h" @@ -129,7 +130,7 @@ void qrio_prst(u8 bit, bool en, bool wden) void qrio_prstcfg(u8 bit, u8 mode) { - u32 prstcfg; + unsigned long prstcfg; u8 i; void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; @@ -137,9 +138,9 @@ void qrio_prstcfg(u8 bit, u8 mode) for (i = 0; i < 2; i++) { if (mode & (1 << i)) - set_bit(2 * bit + i, &prstcfg); + __set_bit(2 * bit + i, &prstcfg); else - clear_bit(2 * bit + i, &prstcfg); + __clear_bit(2 * bit + i, &prstcfg); } out_be32(qrio_base + PRSTCFG_OFF, prstcfg); From d141f4b298de23019405c68ccfb2a0de059e5565 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Wed, 13 Jan 2021 16:20:51 +0000 Subject: [PATCH 15/61] keymile: common: qrio: print QRIO id and revision number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add show_qrio function to print chip id and revision information. There are already multiple QRIO chip versions available and the upcoming designs may want to show used version. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/common/qrio.c | 12 ++++++++++++ board/keymile/common/qrio.h | 1 + 2 files changed, 13 insertions(+) diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index d4e75f2850..25937ee362 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -11,10 +11,22 @@ #include "common.h" #include "qrio.h" +/* QRIO ID register offset */ +#define ID_REV_OFF 0x00 + /* QRIO GPIO register offsets */ #define DIRECT_OFF 0x18 #define GPRT_OFF 0x1c +void show_qrio(void) +{ + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + u16 id_rev = in_be16(qrio_base + ID_REV_OFF); + + printf("QRIO: id = %u, revision = %u\n", + (id_rev >> 8) & 0xff, id_rev & 0xff); +} + int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt; diff --git a/board/keymile/common/qrio.h b/board/keymile/common/qrio.h index a04a73266f..757bcbf2f3 100644 --- a/board/keymile/common/qrio.h +++ b/board/keymile/common/qrio.h @@ -11,6 +11,7 @@ #define QRIO_GPIO_A 0x40 #define QRIO_GPIO_B 0x60 +void show_qrio(void); int qrio_get_gpio(u8 port_off, u8 gpio_nr); void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); From e081d9441e070f781e6a5bd693ce9a6a5a21aba7 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 19 Jan 2021 10:41:00 +0000 Subject: [PATCH 16/61] board/km/common: fix pnvramaddr and varaddr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Take into account SDRAM_BASE address when calculating pnvramaddr and varaddr offsets. Up to now Keymile designs had SDRAM_BASE equal to zero and the offsets where calculated correctly, this fix is for the upcoming designs that have SDRAM_BASE different then zero. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/common/common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index df507e2790..e3e9c4a399 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -49,8 +49,8 @@ int set_km_env(void) char *p; unsigned long rootfssize = 0; - pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - - CONFIG_KM_PNVRAM; + pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf((char *)buf, "0x%x", pnvramaddr); env_set("pnvramaddr", (char *)buf); @@ -63,7 +63,8 @@ int set_km_env(void) sprintf((char *)buf, "0x%x", pram); env_set("pram", (char *)buf); - varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; sprintf((char *)buf, "0x%x", varaddr); env_set("varaddr", (char *)buf); From c1a215b455c436532392edf9bde0ff853718b9a1 Mon Sep 17 00:00:00 2001 From: Niel Fourie Date: Thu, 21 Jan 2021 13:19:18 +0100 Subject: [PATCH 17/61] PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10 Pulled in the kmcent2.dts and all its dependents from Linux 5.10, commit 2c85ebc57b3e upstream. Replaced the license text with SPDX License Identifiers. Signed-off-by: Niel Fourie Cc: Holger Brunck Cc: Heiko Schocher Reviewed-by: Stefan Roese Reviewed-by: Priyanka Jain --- arch/powerpc/dts/elo3-dma-0.dtsi | 55 ++ arch/powerpc/dts/elo3-dma-1.dtsi | 55 ++ arch/powerpc/dts/kmcent2.dts | 338 ++++++++++++ arch/powerpc/dts/qoriq-bman1.dtsi | 14 + arch/powerpc/dts/qoriq-duart-0.dtsi | 24 + arch/powerpc/dts/qoriq-duart-1.dtsi | 24 + arch/powerpc/dts/qoriq-esdhc-0.dtsi | 13 + arch/powerpc/dts/qoriq-espi-0.dtsi | 14 + arch/powerpc/dts/qoriq-mpic.dtsi | 79 +++ arch/powerpc/dts/qoriq-qman3.dtsi | 14 + arch/powerpc/dts/qoriq-sata2-0.dtsi | 12 + arch/powerpc/dts/qoriq-sata2-1.dtsi | 12 + arch/powerpc/dts/qoriq-sec5.0-0.dtsi | 83 +++ arch/powerpc/dts/qoriq-usb2-dr-0.dtsi | 14 + arch/powerpc/dts/qoriq-usb2-mph-0.dtsi | 14 + arch/powerpc/dts/t1040si-post.dtsi | 727 +++++++++++++++++++++++++ arch/powerpc/dts/t104xsi-pre.dtsi | 88 +++ 17 files changed, 1580 insertions(+) create mode 100644 arch/powerpc/dts/elo3-dma-0.dtsi create mode 100644 arch/powerpc/dts/elo3-dma-1.dtsi create mode 100644 arch/powerpc/dts/kmcent2.dts create mode 100644 arch/powerpc/dts/qoriq-bman1.dtsi create mode 100644 arch/powerpc/dts/qoriq-duart-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-duart-1.dtsi create mode 100644 arch/powerpc/dts/qoriq-esdhc-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-espi-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-mpic.dtsi create mode 100644 arch/powerpc/dts/qoriq-qman3.dtsi create mode 100644 arch/powerpc/dts/qoriq-sata2-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-sata2-1.dtsi create mode 100644 arch/powerpc/dts/qoriq-sec5.0-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi create mode 100644 arch/powerpc/dts/t1040si-post.dtsi create mode 100644 arch/powerpc/dts/t104xsi-pre.dtsi diff --git a/arch/powerpc/dts/elo3-dma-0.dtsi b/arch/powerpc/dts/elo3-dma-0.dtsi new file mode 100644 index 0000000000..c3f7737256 --- /dev/null +++ b/arch/powerpc/dts/elo3-dma-0.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + */ + +dma0: dma@100300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + ranges = <0x0 0x100100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/elo3-dma-1.dtsi b/arch/powerpc/dts/elo3-dma-1.dtsi new file mode 100644 index 0000000000..a61c88649c --- /dev/null +++ b/arch/powerpc/dts/elo3-dma-1.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + */ + +dma1: dma@101300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x101300 0x4>, + <0x101600 0x4>; + ranges = <0x0 0x101100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <32 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <33 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <34 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <35 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <80 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <81 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <82 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <83 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/kmcent2.dts b/arch/powerpc/dts/kmcent2.dts new file mode 100644 index 0000000000..5d23ecb34b --- /dev/null +++ b/arch/powerpc/dts/kmcent2.dts @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS + * + * (C) Copyright 2016 + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com + * + * Copyright 2014 - 2015 Freescale Semiconductor Inc. + */ + +/include/ "t104xsi-pre.dtsi" + +/ { + model = "keymile,kmcent2"; + compatible = "keymile,kmcent2"; + + aliases { + front_phy = &front_phy; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bman_fbpr: bman-fbpr { + size = <0 0x1000000>; + alignment = <0 0x1000000>; + }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; + }; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x04000000 + 1 0 0xf 0xfa000000 0x00010000 + 2 0 0xf 0xfb000000 0x00010000 + 4 0 0xf 0xc0000000 0x08000000 + 6 0 0xf 0xd0000000 0x08000000 + 7 0 0xf 0xd8000000 0x08000000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x04000000>; + bank-width = <2>; + device-width = <2>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x1 0x0 0x10000>; + }; + + board-control@2,0 { + compatible = "keymile,qriox"; + reg = <0x2 0x0 0x80>; + }; + + chassis-mgmt@6,0 { + compatible = "keymile,bfticu"; + reg = <6 0 0x100>; + interrupt-controller; + interrupt-parent = <&mpic>; + interrupts = <11 1 0 0>; + #interrupt-cells = <1>; + }; + + }; + + memory { + device_type = "memory"; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01072000>; + }; + + bportals: bman-portals@ff4000000 { + ranges = <0x0 0xf 0xf4000000 0x2000000>; + }; + + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + + spi@110000 { + network-clock@1 { + compatible = "zarlink,zl30364"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + }; + + sdhc@114000 { + status = "disabled"; + }; + + i2c@118000 { + clock-frequency = <100000>; + + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + pagesize = <2>; + read-only; + label = "ddr3-spd"; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + temp-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + label = "SENSOR_0"; + }; + temp-sensor@4a { + compatible = "national,lm75"; + reg = <0x4a>; + label = "SENSOR_2"; + }; + temp-sensor@4b { + compatible = "national,lm75"; + reg = <0x4b>; + label = "SENSOR_3"; + }; + }; + }; + }; + + i2c@118100 { + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + }; + + i2c@119000 { + status = "disabled"; + }; + + i2c@119100 { + status = "disabled"; + }; + + serial2: serial@11d500 { + status = "disabled"; + }; + + serial3: serial@11d600 { + status = "disabled"; + }; + + usb0: usb@210000 { + status = "disabled"; + }; + usb1: usb@211000 { + status = "disabled"; + }; + + display@180000 { + status = "disabled"; + }; + + sata@220000 { + status = "disabled"; + }; + sata@221000 { + status = "disabled"; + }; + + fman@400000 { + ethernet@e0000 { + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@e2000 { + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@e4000 { + status = "disabled"; + }; + + ethernet@e6000 { + status = "disabled"; + }; + + ethernet@e8000 { + phy-handle = <&front_phy>; + phy-mode = "rgmii-id"; + }; + + mdio0: mdio@fc000 { + front_phy: ethernet-phy@11 { + reg = <0x11>; + }; + }; + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + status = "disabled"; + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 + 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + status = "disabled"; + reg = <0xf 0xfe260000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe270000 { + status = "disabled"; + reg = <0xf 0xfe270000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + qe: qe@ffe140000 { + ranges = <0x0 0xf 0xfe140000 0x40000>; + reg = <0xf 0xfe140000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + + si1: si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc_hdlc: ucc@2000 { + device_type = "hdlc"; + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk9"; + tx-clock-name = "clk9"; + fsl,hdlc-bus; + }; + }; +}; + +#include "t1040si-post.dtsi" diff --git a/arch/powerpc/dts/qoriq-bman1.dtsi b/arch/powerpc/dts/qoriq-bman1.dtsi new file mode 100644 index 0000000000..d6164bac8a --- /dev/null +++ b/arch/powerpc/dts/qoriq-bman1.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ] + * + * Copyright 2011 - 2014 Freescale Semiconductor Inc. + */ + +bman: bman@31a000 { + compatible = "fsl,bman"; + reg = <0x31a000 0x1000>; + interrupts = <16 2 1 2>; + fsl,bman-portals = <&bportals>; + memory-region = <&bman_fbpr>; +}; diff --git a/arch/powerpc/dts/qoriq-duart-0.dtsi b/arch/powerpc/dts/qoriq-duart-0.dtsi new file mode 100644 index 0000000000..0ac4843840 --- /dev/null +++ b/arch/powerpc/dts/qoriq-duart-0.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +serial0: serial@11c500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11c500 0x100>; + clock-frequency = <0>; + interrupts = <36 2 0 0>; +}; + +serial1: serial@11c600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11c600 0x100>; + clock-frequency = <0>; + interrupts = <36 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-duart-1.dtsi b/arch/powerpc/dts/qoriq-duart-1.dtsi new file mode 100644 index 0000000000..c712146aa6 --- /dev/null +++ b/arch/powerpc/dts/qoriq-duart-1.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +serial2: serial@11d500 { + cell-index = <2>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11d500 0x100>; + clock-frequency = <0>; + interrupts = <37 2 0 0>; +}; + +serial3: serial@11d600 { + cell-index = <3>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11d600 0x100>; + clock-frequency = <0>; + interrupts = <37 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-esdhc-0.dtsi b/arch/powerpc/dts/qoriq-esdhc-0.dtsi new file mode 100644 index 0000000000..dd24a49095 --- /dev/null +++ b/arch/powerpc/dts/qoriq-esdhc-0.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sdhc: sdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + interrupts = <48 2 0 0>; + clock-frequency = <0>; +}; diff --git a/arch/powerpc/dts/qoriq-espi-0.dtsi b/arch/powerpc/dts/qoriq-espi-0.dtsi new file mode 100644 index 0000000000..e87e6dd49b --- /dev/null +++ b/arch/powerpc/dts/qoriq-espi-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-mpic.dtsi b/arch/powerpc/dts/qoriq-mpic.dtsi new file mode 100644 index 0000000000..bec7c04e69 --- /dev/null +++ b/arch/powerpc/dts/qoriq-mpic.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; +}; + +timer@41100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x41100 0x100 0x41300 4>; + interrupts = <0 0 3 0 + 1 0 3 0 + 2 0 3 0 + 3 0 3 0>; +}; + +msi0: msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x200 0x44140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 0 0 + 0xe1 0 0 0 + 0xe2 0 0 0 + 0xe3 0 0 0 + 0xe4 0 0 0 + 0xe5 0 0 0 + 0xe6 0 0 0 + 0xe7 0 0 0>; +}; + +msi1: msi@41800 { + compatible = "fsl,mpic-msi"; + reg = <0x41800 0x200 0x45140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe8 0 0 0 + 0xe9 0 0 0 + 0xea 0 0 0 + 0xeb 0 0 0 + 0xec 0 0 0 + 0xed 0 0 0 + 0xee 0 0 0 + 0xef 0 0 0>; +}; + +msi2: msi@41a00 { + compatible = "fsl,mpic-msi"; + reg = <0x41a00 0x200 0x46140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xf0 0 0 0 + 0xf1 0 0 0 + 0xf2 0 0 0 + 0xf3 0 0 0 + 0xf4 0 0 0 + 0xf5 0 0 0 + 0xf6 0 0 0 + 0xf7 0 0 0>; +}; + +timer@42100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x42100 0x100 0x42300 4>; + interrupts = <4 0 3 0 + 5 0 3 0 + 6 0 3 0 + 7 0 3 0>; +}; diff --git a/arch/powerpc/dts/qoriq-qman3.dtsi b/arch/powerpc/dts/qoriq-qman3.dtsi new file mode 100644 index 0000000000..b1f8a777a2 --- /dev/null +++ b/arch/powerpc/dts/qoriq-qman3.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ] + * + * Copyright 2014 Freescale Semiconductor Inc. + */ + +qman: qman@318000 { + compatible = "fsl,qman"; + reg = <0x318000 0x2000>; + interrupts = <16 2 1 3>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; +}; diff --git a/arch/powerpc/dts/qoriq-sata2-0.dtsi b/arch/powerpc/dts/qoriq-sata2-0.dtsi new file mode 100644 index 0000000000..385b91784d --- /dev/null +++ b/arch/powerpc/dts/qoriq-sata2-0.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sata@220000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x220000 0x1000>; + interrupts = <68 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sata2-1.dtsi b/arch/powerpc/dts/qoriq-sata2-1.dtsi new file mode 100644 index 0000000000..d72dd39e02 --- /dev/null +++ b/arch/powerpc/dts/qoriq-sata2-1.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sata@221000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x221000 0x1000>; + interrupts = <69 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sec5.0-0.dtsi b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi new file mode 100644 index 0000000000..af0bb9dd6e --- /dev/null +++ b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <5>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v5.0-rtic", + "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi new file mode 100644 index 0000000000..ee135c67ca --- /dev/null +++ b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +usb@211000 { + compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; + reg = <0x211000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <45 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi new file mode 100644 index 0000000000..8579cc1e06 --- /dev/null +++ b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +usb@210000 { + compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; + reg = <0x210000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <44 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/t1040si-post.dtsi b/arch/powerpc/dts/t1040si-post.dtsi new file mode 100644 index 0000000000..c71cf33f8a --- /dev/null +++ b/arch/powerpc/dts/t1040si-post.dtsi @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * T1040 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 - 2014 Freescale Semiconductor Inc. + */ + +#include + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,ifc", "simple-bus"; + interrupts = <25 2 0 0>; +}; + +&pci0 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <20 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <20 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 40 1 0 0 + 0000 0 0 2 &mpic 1 1 0 0 + 0000 0 0 3 &mpic 2 1 0 0 + 0000 0 0 4 &mpic 3 1 0 0 + >; + }; +}; + +&pci1 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0 0xff>; + interrupts = <21 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <21 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 41 1 0 0 + 0000 0 0 2 &mpic 5 1 0 0 + 0000 0 0 3 &mpic 6 1 0 0 + 0000 0 0 4 &mpic 7 1 0 0 + >; + }; +}; + +&pci2 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <22 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <22 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 42 1 0 0 + 0000 0 0 2 &mpic 9 1 0 0 + 0000 0 0 3 &mpic 10 1 0 0 + 0000 0 0 4 &mpic 11 1 0 0 + >; + }; +}; + +&pci3 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <23 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <23 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 43 1 0 0 + 0000 0 0 2 &mpic 0 1 0 0 + 0000 0 0 3 &mpic 4 1 0 0 + 0000 0 0 4 &mpic 8 1 0 0 + >; + }; +}; + +&dcsr { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,dcsr", "simple-bus"; + + dcsr-epu@0 { + compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu"; + interrupts = <52 2 0 0 + 84 2 0 0 + 85 2 0 0>; + reg = <0x0 0x1000>; + }; + dcsr-npc { + compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc"; + reg = <0x1000 0x1000 0x1002000 0x10000>; + }; + dcsr-nxc@2000 { + compatible = "fsl,dcsr-nxc"; + reg = <0x2000 0x1000>; + }; + dcsr-corenet { + compatible = "fsl,dcsr-corenet"; + reg = <0x8000 0x1000 0x1A000 0x1000>; + }; + dcsr-dpaa@9000 { + compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa"; + reg = <0x9000 0x1000>; + }; + dcsr-ocn@11000 { + compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn"; + reg = <0x11000 0x1000>; + }; + dcsr-ddr@12000 { + compatible = "fsl,dcsr-ddr"; + dev-handle = <&ddr1>; + reg = <0x12000 0x1000>; + }; + dcsr-nal@18000 { + compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal"; + reg = <0x18000 0x1000>; + }; + dcsr-rcpm@22000 { + compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm"; + reg = <0x22000 0x1000>; + }; + dcsr-snpc@30000 { + compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x30000 0x1000 0x1022000 0x10000>; + }; + dcsr-snpc@31000 { + compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x31000 0x1000 0x1042000 0x10000>; + }; + dcsr-cpu-sb-proxy@100000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu0>; + reg = <0x100000 0x1000 0x101000 0x1000>; + }; + dcsr-cpu-sb-proxy@108000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu1>; + reg = <0x108000 0x1000 0x109000 0x1000>; + }; + dcsr-cpu-sb-proxy@110000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu2>; + reg = <0x110000 0x1000 0x111000 0x1000>; + }; + dcsr-cpu-sb-proxy@118000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu3>; + reg = <0x118000 0x1000 0x119000 0x1000>; + }; +}; + +&bportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + bman-portal@0 { + compatible = "fsl,bman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <105 2 0 0>; + }; + bman-portal@4000 { + compatible = "fsl,bman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <107 2 0 0>; + }; + bman-portal@8000 { + compatible = "fsl,bman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <109 2 0 0>; + }; + bman-portal@c000 { + compatible = "fsl,bman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <111 2 0 0>; + }; + bman-portal@10000 { + compatible = "fsl,bman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <113 2 0 0>; + }; + bman-portal@14000 { + compatible = "fsl,bman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <115 2 0 0>; + }; + bman-portal@18000 { + compatible = "fsl,bman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <117 2 0 0>; + }; + bman-portal@1c000 { + compatible = "fsl,bman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <119 2 0 0>; + }; + bman-portal@20000 { + compatible = "fsl,bman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <121 2 0 0>; + }; + bman-portal@24000 { + compatible = "fsl,bman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <123 2 0 0>; + }; +}; + +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + soc-sram-error { + compatible = "fsl,soc-sram-error"; + interrupts = <16 2 1 29>; + }; + + corenet-law@0 { + compatible = "fsl,corenet-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <16>; + }; + + ddr1: memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v5.0", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; + + cpc: l3-cache-controller@10000 { + compatible = "fsl,t1040-l3-cache-controller", "cache"; + reg = <0x10000 0x1000>; + interrupts = <16 2 1 27>; + }; + + corenet-cf@18000 { + compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; + reg = <0x18000 0x1000>; + interrupts = <16 2 1 31>; + fsl,ccf-num-csdids = <32>; + fsl,ccf-num-snoopids = <32>; + }; + + iommu@20000 { + compatible = "fsl,pamu-v1.0", "fsl,pamu"; + reg = <0x20000 0x1000>; + ranges = <0 0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = < + 24 2 0 0 + 16 2 1 30>; + pamu0: pamu@0 { + reg = <0 0x1000>; + fsl,primary-cache-geometry = <128 1>; + fsl,secondary-cache-geometry = <16 2>; + }; + }; + +/include/ "qoriq-mpic.dtsi" + + guts: global-utilities@e0000 { + compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + fsl,liodn-bits = <12>; + }; + +/include/ "qoriq-clockgen2.dtsi" + global-utilities@e1000 { + compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; + }; + + rcpm: global-utilities@e2000 { + compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1"; + reg = <0xe2000 0x1000>; + }; + + sfp: sfp@e8000 { + compatible = "fsl,t1040-sfp"; + reg = <0xe8000 0x1000>; + }; + + serdes: serdes@ea000 { + compatible = "fsl,t1040-serdes"; + reg = <0xea000 0x4000>; + }; + + tmu: tmu@f0000 { + compatible = "fsl,qoriq-tmu"; + reg = <0xf0000 0x1000>; + interrupts = <18 2 0 0>; + fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; + fsl,tmu-calibration = <0x00000000 0x00000025 + 0x00000001 0x00000028 + 0x00000002 0x0000002d + 0x00000003 0x00000031 + 0x00000004 0x00000036 + 0x00000005 0x0000003a + 0x00000006 0x00000040 + 0x00000007 0x00000044 + 0x00000008 0x0000004a + 0x00000009 0x0000004f + 0x0000000a 0x00000054 + + 0x00010000 0x0000000d + 0x00010001 0x00000013 + 0x00010002 0x00000019 + 0x00010003 0x0000001f + 0x00010004 0x00000025 + 0x00010005 0x0000002d + 0x00010006 0x00000033 + 0x00010007 0x00000043 + 0x00010008 0x0000004b + 0x00010009 0x00000053 + + 0x00020000 0x00000010 + 0x00020001 0x00000017 + 0x00020002 0x0000001f + 0x00020003 0x00000029 + 0x00020004 0x00000031 + 0x00020005 0x0000003c + 0x00020006 0x00000042 + 0x00020007 0x0000004d + 0x00020008 0x00000056 + + 0x00030000 0x00000012 + 0x00030001 0x0000001d>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 2>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert>; + cooling-device = + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map2 { + trip = <&cpu_alert>; + cooling-device = + <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map3 { + trip = <&cpu_alert>; + cooling-device = + <&cpu3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + scfg: global-utilities@fc000 { + compatible = "fsl,t1040-scfg"; + reg = <0xfc000 0x1000>; + }; + +/include/ "elo3-dma-0.dtsi" +/include/ "elo3-dma-1.dtsi" +/include/ "qoriq-espi-0.dtsi" + spi@110000 { + fsl,espi-num-chipselects = <4>; + }; + +/include/ "qoriq-esdhc-0.dtsi" + sdhc@114000 { + compatible = "fsl,t1040-esdhc", "fsl,esdhc"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ + sdhci,auto-cmd12; + }; +/include/ "qoriq-i2c-0.dtsi" +/include/ "qoriq-i2c-1.dtsi" +/include/ "qoriq-duart-0.dtsi" +/include/ "qoriq-duart-1.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-usb2-mph-0.dtsi" + usb0: usb@210000 { + compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ + phy_type = "utmi"; + port0; + }; +/include/ "qoriq-usb2-dr-0.dtsi" + usb1: usb@211000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ + dr_mode = "host"; + phy_type = "utmi"; + }; + + display@180000 { + compatible = "fsl,t1040-diu", "fsl,diu"; + reg = <0x180000 1000>; + interrupts = <74 2 0 0>; + }; + +/include/ "qoriq-sata2-0.dtsi" + sata@220000 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ + }; +/include/ "qoriq-sata2-1.dtsi" + sata@221000 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ + }; +/include/ "qoriq-sec5.0-0.dtsi" +/include/ "qoriq-qman3.dtsi" +/include/ "qoriq-bman1.dtsi" + +/include/ "qoriq-fman3l-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; + + seville_switch: ethernet-switch@800000 { + compatible = "mscc,vsc9953-switch"; + reg = <0x800000 0x290000>; + interrupts = <26 2 0 0>; + interrupt-names = "xtr"; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + seville_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + seville_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + seville_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + seville_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + seville_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + seville_port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + seville_port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + seville_port7: port@7 { + reg = <7>; + status = "disabled"; + }; + + seville_port8: port@8 { + reg = <8>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + seville_port9: port@9 { + reg = <9>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + }; +}; + +&qe { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; +}; diff --git a/arch/powerpc/dts/t104xsi-pre.dtsi b/arch/powerpc/dts/t104xsi-pre.dtsi new file mode 100644 index 0000000000..025872cfea --- /dev/null +++ b/arch/powerpc/dts/t104xsi-pre.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * T1040/T1042 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013-2014 Freescale Semiconductor Inc. + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + aliases { + ccsr = &soc; + dcsr = &dcsr; + + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + usb0 = &usb0; + usb1 = &usb1; + sdhc = &sdhc; + + crypto = &crypto; + + fman0 = &fman0; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + ethernet4 = &enet4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + clocks = <&clockgen 1 0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + clocks = <&clockgen 1 1>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu2: PowerPC,e5500@2 { + device_type = "cpu"; + reg = <2>; + clocks = <&clockgen 1 2>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu3: PowerPC,e5500@3 { + device_type = "cpu"; + reg = <3>; + clocks = <&clockgen 1 3>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + next-level-cache = <&cpc>; + }; + }; + }; +}; From df86d324c79e890141386b7e27adc1cb949e8d41 Mon Sep 17 00:00:00 2001 From: Niel Fourie Date: Thu, 21 Jan 2021 13:19:19 +0100 Subject: [PATCH 18/61] keymile: common: update to set_env_hex(), fix "pram" radix Replace instances of sprintf()/set_env() for setting hexadecimal values with set_env_hex(). In set_km_env() the "pram" variable was set to an hexadecimal value, while initr_mem() expects an unsigned decimal, so use set_env_ulong() instead. Signed-off-by: Niel Fourie Cc: Holger Brunck Cc: Heiko Schocher Reviewed-by: Stefan Roese [Rebased] Signed-off-by: Priyanka Jain --- board/keymile/common/common.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index e3e9c4a399..9c482d8454 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; */ int set_km_env(void) { - uchar buf[32]; unsigned int pnvramaddr; unsigned int pram; unsigned int varaddr; @@ -51,8 +50,7 @@ int set_km_env(void) pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; - sprintf((char *)buf, "0x%x", pnvramaddr); - env_set("pnvramaddr", (char *)buf); + env_set_hex("pnvramaddr", pnvramaddr); /* try to read rootfssize (ram image) from environment */ p = env_get("rootfssize"); @@ -60,17 +58,14 @@ int set_km_env(void) strict_strtoul(p, 16, &rootfssize); pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / 0x400; - sprintf((char *)buf, "0x%x", pram); - env_set("pram", (char *)buf); + env_set_ulong("pram", pram); varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; - sprintf((char *)buf, "0x%x", varaddr); - env_set("varaddr", (char *)buf); + env_set_hex("varaddr", varaddr); kernelmem = gd->ram_size - 0x400 * pram; - sprintf((char *)buf, "0x%x", kernelmem); - env_set("kernelmem", (char *)buf); + env_set_hex("kernelmem", kernelmem); return 0; } @@ -244,7 +239,6 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc, p = env_get("hwkey"); if (p) rc = strict_strtoul(p, 16, &envhwkey); - if (rc != 0) { printf("strict_strtoul returns error: %d", rc); return rc; @@ -306,15 +300,11 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc, * set the values in environment variables. */ if (bid == ivmbid && hwkey == ivmhwkey) { - char buf[10]; - found = 1; envbid = bid; envhwkey = hwkey; - sprintf(buf, "%lx", bid); - env_set("boardid", buf); - sprintf(buf, "%lx", hwkey); - env_set("hwkey", buf); + env_set_hex("boardid", bid); + env_set_hex("hwkey", hwkey); } } /* end while( ! found ) */ } From 37bfd9cb50b829be07ebf8e6634bb3b5457b4a79 Mon Sep 17 00:00:00 2001 From: Niel Fourie Date: Thu, 21 Jan 2021 13:19:20 +0100 Subject: [PATCH 19/61] PowerPC: keymile: Add support for kmcent2 board Add basic support for the Hitachi Power Grids kmcent2 board, based on the NXP QorIQ T1040 SoC. Signed-off-by: Valentin Longchamp Signed-off-by: Rainer Boschung Signed-off-by: Niel Fourie Cc: Holger Brunck Cc: Heiko Schocher Reviewed-by: Stefan Roese [Fixed blank line at EOF errors] Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/kmcent2-u-boot.dtsi | 97 +++++ board/keymile/Kconfig | 1 + board/keymile/common/ivm.c | 5 + board/keymile/kmcent2/Kconfig | 17 + board/keymile/kmcent2/MAINTAINERS | 8 + board/keymile/kmcent2/Makefile | 14 + board/keymile/kmcent2/ddr.c | 88 +++++ board/keymile/kmcent2/kmcent2.c | 353 ++++++++++++++++++ board/keymile/kmcent2/law.c | 23 ++ board/keymile/kmcent2/tlb.c | 104 ++++++ configs/kmcent2_defconfig | 92 +++++ include/configs/kmcent2.h | 513 +++++++++++++++++++++++++++ 14 files changed, 1320 insertions(+) create mode 100644 arch/powerpc/dts/kmcent2-u-boot.dtsi create mode 100644 board/keymile/kmcent2/Kconfig create mode 100644 board/keymile/kmcent2/MAINTAINERS create mode 100644 board/keymile/kmcent2/Makefile create mode 100644 board/keymile/kmcent2/ddr.c create mode 100644 board/keymile/kmcent2/kmcent2.c create mode 100644 board/keymile/kmcent2/law.c create mode 100644 board/keymile/kmcent2/tlb.c create mode 100644 configs/kmcent2_defconfig create mode 100644 include/configs/kmcent2.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 54c7fd9522..c1a3770671 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -256,6 +256,10 @@ config TARGET_KMP204X bool "Support kmp204x" select VENDOR_KM +config TARGET_KMCENT2 + bool "Support kmcent2" + select VENDOR_KM + config TARGET_XPEDITE520X bool "Support xpedite520x" select ARCH_MPC8548 diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 266d345f72..3ecda36538 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi new file mode 100644 index 0000000000..ab76a9f122 --- /dev/null +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2021 Niel Fourie + */ + +#include + +/ { + + aliases { + spi0 = "/soc@ffe000000/spi@110000"; + i2c0 = "/soc@ffe000000/i2c@118000"; + i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0"; + i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1"; + i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7"; + i2c4 = "/soc@ffe000000/i2c@118100"; + /delete-property/ pci1; + /delete-property/ pci2; + /delete-property/ pci3; + }; + + chosen { + stdout-path = "/soc@ffe000000/serial@11c500"; + }; + + soc@ffe000000 { + u-boot,dm-pre-reloc; + spi@110000 { + /* This documents where km_fpgacfg should be appear */ + fpga@0 { + compatible = "keymile,fpga-conf"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + }; + + sdhc@114000 { + status = "okay"; + }; + + i2c@118000 { + u-boot,dm-pre-reloc; + mux@70 { + i2c@1 { /* IVM bus */ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + serial@11c500 { + u-boot,dm-pre-reloc; + clock-frequency = <200000000>; + }; + + fman@400000 { + ethernet@e0000 { + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + phy-connection-type = "rgmii-id"; + }; + }; + + }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t104x"; + law_trgt_if = <0>; + }; + + binman { + filename = "u-boot-with-dtb.bin"; + skip-at-start = ; + sort-by-offset; + pad-byte = <0xff>; + size = ; + + u-boot-with-ucode-ptr { + offset = ; + optional-ucode; + }; + + u-boot-dtb-with-ucode { + align = <256>; + }; + powerpc-mpc85xx-bootpg-resetvec { + offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + }; + }; +}; diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index e5906906f3..6b7377c200 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -114,6 +114,7 @@ config SYS_IVM_EEPROM_PAGE_LEN Page size of inventory in EEPROM. source "board/keymile/km83xx/Kconfig" +source "board/keymile/kmcent2/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/keymile/km_arm/Kconfig" diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index e989bf609f..bc8ffd56e1 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) process_mac(valbuf, page2, mac_address_offset, true); env_set((char *)"eth1addr", (char *)valbuf); } + if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) { + /* 3rd ethernet interface */ + process_mac(valbuf, page2, 2, true); + env_set((char *)"eth4addr", (char *)valbuf); + } return 0; } diff --git a/board/keymile/kmcent2/Kconfig b/board/keymile/kmcent2/Kconfig new file mode 100644 index 0000000000..848d230fbd --- /dev/null +++ b/board/keymile/kmcent2/Kconfig @@ -0,0 +1,17 @@ +if TARGET_KMCENT2 + +config SYS_BOARD + default "kmcent2" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcent2" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_T1040 + select PHYS_64BIT + +endif diff --git a/board/keymile/kmcent2/MAINTAINERS b/board/keymile/kmcent2/MAINTAINERS new file mode 100644 index 0000000000..1426475556 --- /dev/null +++ b/board/keymile/kmcent2/MAINTAINERS @@ -0,0 +1,8 @@ +KMCENT2 BOARD +M: Niel Fourie +S: Maintained +F: board/keymile/kmcent2/ +F: include/configs/kmcent2.h +F: configs/kmcent2_defconfig +F: arch/powerpc/dts/kmcent2.dts +F: arch/powerpc/dts/kmcent2-u-boot.dtsi diff --git a/board/keymile/kmcent2/Makefile b/board/keymile/kmcent2/Makefile new file mode 100644 index 0000000000..6b26e861f6 --- /dev/null +++ b/board/keymile/kmcent2/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Keymile AG +# Rainer Boschung +# +# Copyright 2013 Freescale Semiconductor, Inc. +# + +obj-y += kmcent2.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += ../common/common.o +obj-y += ../common/ivm.o +obj-y += ../common/qrio.o diff --git a/board/keymile/kmcent2/ddr.c b/board/keymile/kmcent2/ddr.c new file mode 100644 index 0000000000..4f778206fe --- /dev/null +++ b/board/keymile/kmcent2/ddr.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8 +#define DQSn_START(n, start) ((start) << DQSn_POS(n)) + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + + /* 1/2 clk delay between wr command and data strobe */ + popts->write_data_delay = 4; + /* clk lauched 1/2 applied cylcle after address command */ + popts->clk_adjust = 4; + /* 1T timing: command/address held for only 1 cycle */ + popts->twot_en = 0; + popts->threet_en = 0; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x3b; + + /* we have only one module, half str should be OK */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + /* set for DDR3-1600 */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x7; + /* DQS write leveling start time according layout */ + popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) | + DQSn_START(2, 0x06) | + DQSn_START(3, 0x07) | + DQSn_START(4, 0x07)); + popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) | + DQSn_START(6, 0x08) | + DQSn_START(7, 0x08) | + DQSn_START(8, 0x08)); + + /* + * rtt and wtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +int dram_init(void) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c new file mode 100644 index 0000000000..4f5164e63c --- /dev/null +++ b/board/keymile/kmcent2/kmcent2.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" +#include "../common/qrio.h" + +DECLARE_GLOBAL_DATA_PTR; + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +int checkboard(void) +{ + printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME); + + return 0; +} + +#define RSTRQSR1_WDT_RR 0x00200000 +#define RSTRQSR1_SW_RR 0x00100000 + +int board_early_init_f(void) +{ + struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool cpuwd_flag = false; + + /* board specific IFC configuration: increased bus turnaround time */ + setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + /* configure mode for uP reset request */ + qrio_uprstreq(UPREQ_CORE_RST); + + /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */ + setbits_be32(&gur->ddrclkdr, 0x40000000); + + /* set reset reason according CPU register */ + if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == + RSTRQSR1_WDT_RR) + cpuwd_flag = true; + + qrio_cpuwd_flag(cpuwd_flag); + /* clear CPU bits by writing 1 */ + setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); + + /* configure PRST lines for the application: */ + /* + * ETHSW_DDR_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_ETHSW_DDR_RST, true); + /* + * XES_PHY_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_XES_PHY_RST, true); + /* + * ES_PHY_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_ES_PHY_RST, true); + /* + * EFE_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_EFE_RST, true); + /* + * BFTIC4_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_BFTIC4_RST, true); + /* + * DPAXE_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_DPAXE_RST, true); + /* + * PEXSW_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_PEXSW_RST, false, false); + /* + * PEXSW_NT_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_PEXSW_NT_RST, false, false); + /* + * BOBCAT_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_BOBCAT_RST, false, false); + /* + * FEMT_RST: + * reset at power-up and unit reset only and enable WD + */ + qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_FEMT_RST, true); + /* + * FOAM_RST: + * reset at power-up and unit reset only and enable WD + */ + qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_FOAM_RST, true); + + return 0; +} + +int board_early_init_r(void) +{ + int ret = 0; + + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); + setup_qbman_portals(); + + qrio_set_leds(); + + /* enable Application Buffer */ + qrio_enable_app_buffer(); + + return ret; +} + +unsigned long get_serial_clock(unsigned long dummy) +{ + return (gd->bus_clk / 2); +} + +unsigned long get_board_sys_clk(unsigned long dummy) +{ + return 66666666; +} + +int misc_init_f(void) +{ + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); + + /* + * CFE_RST (front phy): + * reset at power-up, unit and core reset, deasset reset w/o WD + */ + qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(KM_CFE_RST, false, false); + + /* + * ZL30158_RST (PTP clock generator): + * reset at power-up only, deassert reset and enable WD on it + */ + qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST); + qrio_prst(KM_ZL30158_RST, false, false); + + /* + * ZL30364_RST (EEC generator): + * reset at power-up only, deassert reset and enable WD on it + */ + qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST); + qrio_prst(KM_ZL30364_RST, false, false); + + return 0; +} + +#define USED_SRDS_BANK 0 +#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100 + +#define BRG01_IOCLK12 0x02000000 +#define EC2_GTX_CLK125 0x08000000 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG; + ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* check SERDES bank 0 reference clock */ + u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0); + + if (actual & SRDS_PLLCR0_POFF) + printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK); + if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) { + printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n", + USED_SRDS_BANK, + serdes_clock_to_string(EXPECTED_SRDS_RFCK), + serdes_clock_to_string(actual)); + } + + /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */ + out_be32(&scfg->qeioclkcr, + in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12); + + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + CONFIG_PIGGY_MAC_ADDRESS_OFFSET); + + /* Fix polarity of Card Detect and Write Protect */ + out_be32(&gur->sdhcpcr, 0xFFFFFFFF); + + /* + * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL + * to EC2 + */ + out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125); + + return 0; +} + +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} + +int last_stage_init(void) +{ + const char *kmem; + /* DIP switch support on BFTIC */ + struct bfticu_iomap *bftic4 = + (struct bfticu_iomap *)SYS_BFTIC_BASE; + u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK; + + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + env_set("actual_bank", "0"); + } + + set_km_env(); + + /* + * bootm_size is used to fixup the FDT memory node + * set it to kernelmem that has the same value + */ + kmem = env_get("kernelmem"); + if (kmem) + env_set("bootm_size", kmem); + + return 0; +} + +void fdt_fixup_fman_mac_addresses(void *blob) +{ + int node, ret; + char path[24]; + unsigned char mac_addr[6]; + + /* + * Just the fm1-mac5 must be set by us, u-boot handle the 2 others, + * get the mac addr from env + */ + if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) { + printf("eth4addr env variable not defined\n"); + return; + } + + /* local management port */ + strcpy(path, "/soc/fman/ethernet@e8000"); + node = fdt_path_offset(blob, path); + if (node < 0) { + printf("no %s\n", path); + return; + } + + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("%s\n\terror setting local-mac-address property\n", + path); + } +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_liodn(blob); + + fdt_fixup_fman_mac_addresses(blob); + + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); + return 0; +} + +/* DIC26_SELFTEST GPIO used to start factory test sw */ +#define SELFTEST_PORT QRIO_GPIO_A +#define SELFTEST_PIN 0 + +int post_hotkeys_pressed(void) +{ + qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); + return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); +} diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c new file mode 100644 index 0000000000..aa0f29f44f --- /dev/null +++ b/board/keymile/kmcent2/law.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), +/* other application LAW are not used in u-boot */ +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c new file mode 100644 index 0000000000..dbd3b9b064 --- /dev/null +++ b/board/keymile/kmcent2/tlb.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, + 0, 2, BOOKE_PAGESZ_128M, 1), + + /* *I*G* - PCI1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI1 I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), + /* QRIO */ + SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 11, BOOKE_PAGESZ_64K, 1), + /* MRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 12, BOOKE_PAGESZ_128M, 1), + /* BFTIC */ + SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 13, BOOKE_PAGESZ_128M, 1), + /* + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so do not use them here!!. + */ + /* PAXE */ + SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 16, BOOKE_PAGESZ_128M, 1) +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig new file mode 100644 index 0000000000..a34bb08432 --- /dev/null +++ b/configs/kmcent2_defconfig @@ -0,0 +1,92 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xebf40000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_KM_DEF_NETDEV="eth2" +CONFIG_KM_IVM_BUS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 +CONFIG_DEFAULT_DEVICE_TREE="kmcent2" +CONFIG_MPC85xx=y +CONFIG_TARGET_KMCENT2=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SATA is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y +CONFIG_MP=y +CONFIG_CMD_CRAMFS=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=ffa000000.flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),128k(zarlink),512k(res),62m(ubi0),128k(envred),128k(env),768k(u-boot);ffa000000.flash:-(ubi1);" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_ADDR=0xebf20000 +CONFIG_ENV_ADDR_REDUND=0xebf00000 +CONFIG_DM=y +# CONFIG_FSL_SATA is not set +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_FSL_CAAM=y +CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_FMAN_ENET=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCIE_FSL=y +CONFIG_U_QE=y +CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_MEM=y +CONFIG_FSL_ESPI=y +CONFIG_WATCHDOG=y +CONFIG_FS_CRAMFS=y +CONFIG_BCH=y +CONFIG_PANIC_HANG=y +CONFIG_LZO=y diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h new file mode 100644 index 0000000000..51a01d860f --- /dev/null +++ b/include/configs/kmcent2.h @@ -0,0 +1,513 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung + * + */ + +#ifndef __KMCENT2_H +#define __KMCENT2_H + +#define CONFIG_HOSTNAME "kmcent2" +#define KM_BOARD_NAME CONFIG_HOSTNAME + +/* + * The Linux fsl_fman driver needs to be able to process frames with more + * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot + * parameters + */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" + +#include "km/keymile-common.h" + +/* Application IFC chip selects */ +#define SYS_LAWAPP_BASE 0xc0000000 +#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) + +/* Application IFC CS4 MRAM */ +#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS +#define SYS_MRAM_CSPR_EXT (0x0f) +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ + CSPR_PORT_SIZE_8 | /* 8 bit */ \ + CSPR_MSEL_GPCM | /* msel = gpcm */ \ + CSPR_V /* bank is valid */) +#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */ +#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40 +/* MRAM Timing parameters for IFC CS4 */ +#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0xe)) +#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \ + FTIM2_GPCM_TCH(0x2) | \ + FTIM2_GPCM_TWP(0x8)) +#define SYS_MRAM_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR +#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK +#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR +#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 + +/* Application IFC CS6: BFTIC */ +#define SYS_BFTIC_BASE 0xd0000000 +#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE) +#define SYS_BFTIC_CSPR_EXT (0x0f) +#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40 +/* BFTIC Timing parameters for IFC CS6 */ +#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_BFTIC_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 + +/* Application IFC CS7 PAXE */ +#define CONFIG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define SYS_PAXE_CSPR_EXT (0x0f) +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40 +/* PAXE Timing parameters for IFC CS7 */ +#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_PAXE_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR +#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK +#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR +#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 + +/* PRST */ +#define KM_BFTIC4_RST 0 +#define KM_DPAXE_RST 1 +#define KM_FEMT_RST 3 +#define KM_FOAM_RST 4 +#define KM_EFE_RST 5 +#define KM_ES_PHY_RST 6 +#define KM_XES_PHY_RST 7 +#define KM_ZL30158_RST 8 +#define KM_ZL30364_RST 9 +#define KM_BOBCAT_RST 10 +#define KM_ETHSW_DDR_RST 12 +#define KM_CFE_RST 13 +#define KM_PEXSW_RST 14 +#define KM_PEXSW_NT_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ + +#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +/* Environment in parallel NOR-Flash */ +#define CONFIG_ENV_TOTAL_SIZE 0x040000 +#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +/* POST memory regions test */ +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM + */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) + +/* + * IFC Definitions + */ +/* NOR flash on IFC CS0 */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NOR | /* MSEL = NOR */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TWP(0xb) | \ + FTIM2_NOR_TWPH(0x6)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* More NOR Flash params */ +#define CONFIG_SYS_FLASH_QUIET_TEST + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC CS1*/ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xfa000000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NAND | /* MSEL = NAND */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ + CSOR_NAND_PGS_2K | /* Page size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64) | /* 64 Pages/Block */ \ + CSOR_NAND_TRHZ_40 | /**/ \ + CSOR_NAND_BCTLD) /**/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* More NAND Flash Params */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* QRIO on IFC CS2 */ +#define CONFIG_SYS_QRIO_BASE 0xfb000000 +#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define SYS_QRIO_CSPR_EXT (0x0f) +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\ + CSOR_GPCM_BCTLD) +/* QRIO Timing parameters for IFC CS2 */ +#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define SYS_QRIO_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR +#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK +#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 + +#define CONFIG_MISC_INIT_F +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + * Retain non-DM serial port for debug purposes. + */ +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#endif + +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000 +#define CONFIG_SYS_QE_FW_ADDR 0xE8040000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +/* Qman / Bman */ +/* RGMII (FM1@DTESC5) is local managemant interface */ +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CONFIG_ETHPRIME "fm1-mac5" + +/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#define __USB_PHY_TYPE utmi + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "fpgacfg=true\0" \ + "" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + CONFIG_KM_NEW_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* __KMCENT2_H */ From af6266c1c27add8beac7f3365c00b3525a9012c4 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Mon, 25 Jan 2021 03:55:20 +0000 Subject: [PATCH 20/61] mem: spi-mem: add declaration for spi_mem_default_supports_op spi_mem_default_supports_op is used internally by controller drivers to verify operation semantics are correct. It is used internally inside spi-mem but has not (in U-Boot) been declared in spi-mem.h for external use. Signed-off-by: Mathew McBride Reviewed-by: Pratyush Yadav Reviewed-by: Priyanka Jain --- include/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/spi-mem.h b/include/spi-mem.h index ca0f55c8fd..8be3e2bf6b 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -240,6 +240,9 @@ bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op); +bool spi_mem_default_supports_op(struct spi_slave *mem, + const struct spi_mem_op *op); + #ifndef __UBOOT__ int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv, struct module *owner); From 6b4eb604eac8d0dd4f119dcf5523545fc779fafa Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Mon, 25 Jan 2021 03:55:21 +0000 Subject: [PATCH 21/61] spi: fsl_qspi: Ensure width is respected in spi-mem operations Adapted from kernel commit b0177aca7aea From: Michael Walle Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown Signed-off-by: Mathew McBride [adapt for U-Boot] Reviewed-by: Priyanka Jain --- drivers/spi/fsl_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8bc7038a82..2a1f3a0c44 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -409,7 +409,7 @@ static bool fsl_qspi_supports_op(struct spi_slave *slave, op->data.nbytes > q->devtype_data->txfifo) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static void fsl_qspi_prepare_lut(struct fsl_qspi *q, From fd20097336aa1cbadca9db3cfe7a7681312271bd Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Mon, 25 Jan 2021 03:55:22 +0000 Subject: [PATCH 22/61] spi: fsl_qspi: apply the same settings for LS1088 as LS208x The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride Reviewed-by: Priyanka Jain --- drivers/spi/fsl_qspi.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2a1f3a0c44..f965301d6a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -259,14 +259,6 @@ static const struct fsl_qspi_devtype_data ls1021a_data = { .little_endian = false, }; -static const struct fsl_qspi_devtype_data ls1088a_data = { - .rxfifo = SZ_128, - .txfifo = SZ_128, - .ahb_buf_size = SZ_1K, - .quirks = QUADSPI_QUIRK_TKT253890, - .little_endian = true, -}; - static const struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -877,7 +869,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, - { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, { } }; From 584107337b6fd8701586acbca862ef43f7639d19 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 29 Jan 2021 12:47:05 +0800 Subject: [PATCH 23/61] pci: layerscape: Remove the shadow SVR definitions This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang Reviewed-by: Wasim Khan Reviewed-by: Priyanka Jain --- .../arm/include/asm/arch-fsl-layerscape/soc.h | 33 +-------------- .../arm/include/asm/arch-fsl-layerscape/svr.h | 42 +++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/svr.h | 13 ++++++ drivers/pci/pcie_layerscape.h | 12 +----- 4 files changed, 58 insertions(+), 42 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 arch/arm/include/asm/arch-ls102xa/svr.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 887954eaa5..bd41df1be4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -16,6 +16,7 @@ #include #endif #endif +#include #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,38 +78,6 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012A 0x870400 -#define SVR_LS1043A 0x879200 -#define SVR_LS1023A 0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P23 0x879202 -#define SVR_LS1023A_P23 0x87920A -#define SVR_LS1017A 0x870B24 -#define SVR_LS1018A 0x870B20 -#define SVR_LS1027A 0x870B04 -#define SVR_LS1028A 0x870B00 -#define SVR_LS1046A 0x870700 -#define SVR_LS1026A 0x870708 -#define SVR_LS1048A 0x870320 -#define SVR_LS1084A 0x870302 -#define SVR_LS1088A 0x870300 -#define SVR_LS1044A 0x870322 -#define SVR_LS2045A 0x870120 -#define SVR_LS2080A 0x870110 -#define SVR_LS2085A 0x870100 -#define SVR_LS2040A 0x870130 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873600 -#define SVR_LX2120A 0x873620 -#define SVR_LX2080A 0x873602 -#define SVR_LX2162A 0x873608 -#define SVR_LX2122A 0x873628 -#define SVR_LX2082A 0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 0000000000..e37c4a88b5 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 +#define SVR_LS1028A 0x870B00 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 +#define SVR_LS1048A 0x870320 +#define SVR_LS1084A 0x870302 +#define SVR_LS1088A 0x870300 +#define SVR_LS1044A 0x870322 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 0000000000..52b27e2d67 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e051..8cdf516d9f 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include #include +#include +#include #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA 0 -#define SVR_VAR_PER_SHIFT 8 -#define SVR_LS102XA_MASK 0x700 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 - /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL From d167667d1b9053534445a1c0748a0739fe3aa944 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 29 Jan 2021 13:22:02 +0800 Subject: [PATCH 24/61] pci: kconfig: layerscape: Change LX2162A PCIe node compatible string LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang Reviewed-by: Wasim Khan Tested-by: Wasim Khan Reviewed-by: Priyanka Jain --- drivers/pci/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b1de38f766..ba41787f64 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls2088a-pcie" if ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +229,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT From a1f57c393380d0245f8740ddf1497902b9f963f8 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Fri, 5 Feb 2021 06:02:01 +0000 Subject: [PATCH 25/61] board/km: move km i2c deblock declarations to a km/common.h Cleanup, move the declarations to keymile/common.h instead declaring them per-board config.h Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- board/keymile/common/common.h | 5 +++++ include/configs/km/km_arm.h | 4 ---- include/configs/kmp204x.h | 6 ------ 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 8251de4db8..15a3c3797d 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -136,6 +136,11 @@ int set_km_env(void); #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); + int i2c_soft_read_pin(void); int i2c_make_abort(void); #endif /* __KEYMILE_COMMON_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 29060fa96b..4115906c5d 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -110,10 +110,6 @@ #include #include extern void __set_direction(unsigned pin, int high); -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 #define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index d1eb7b574b..90e3702bd8 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -237,12 +237,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ From 19dba8bf9f4c87278b8e6e2133ebc39f4edb6592 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 5 Feb 2021 15:45:12 +0800 Subject: [PATCH 26/61] armv7: ls102xa: Enable I-Cache to speed up the boot time Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce472aa9bd..c6a39aa341 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -316,6 +316,8 @@ int arch_cpu_init(void) struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; + icache_enable(); + /* * The RCPM FSM state may not be reset after power-on. * So, reset them. From 43d1d391f6580a500659745343a6226c5034361e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 5 Feb 2021 14:01:11 +0530 Subject: [PATCH 27/61] mpc8xxx: fsl_pamu: Update data type in config_pamu Update data type of '1' to '1ull' in below assignment size = 1ull << sizebit; to fix incorrect assignment issue. e.g: when sizebit was 31, 0x80000000 got sign extended to 0xffffffff_80000000 Signed-off-by: Priyanka Jain Reported-by: Dean Saridakis Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 2c378b7615..5229949951 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -390,7 +390,7 @@ int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn) return -1; sizebit = __ilog2_roundup_64(size); - size = 1 << sizebit; + size = 1ull << sizebit; debug("min start_addr is %llx\n", min_addr); debug("max end_addr is %llx\n", max_addr); debug("size found is %llx\n", size); From c9cd2a31cc7580f869c6d582c39fc968649304f6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 5 Feb 2021 16:34:02 +0800 Subject: [PATCH 28/61] configs: T1042: Drop the CONFIG_VIDEO Drop the CONFIG_VIDEO to fix the following build warning. ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. UPD include/generated/dt.h Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. UPD include/generated/timestamp_autogenerated.h ==================================================== Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- configs/T1042D4RDB_NAND_defconfig | 1 - configs/T1042D4RDB_SDCARD_defconfig | 1 - configs/T1042D4RDB_SECURE_BOOT_defconfig | 1 - configs/T1042D4RDB_SPIFLASH_defconfig | 1 - configs/T1042D4RDB_defconfig | 1 - configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 - configs/T1042RDB_PI_NAND_defconfig | 1 - configs/T1042RDB_PI_SDCARD_defconfig | 1 - configs/T1042RDB_PI_SPIFLASH_defconfig | 1 - configs/T1042RDB_PI_defconfig | 1 - 10 files changed, 10 deletions(-) diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 855b00ad53..ee7b6faa42 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -84,7 +84,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index b43998a9a7..c64ad0b1fd 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -81,7 +81,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index b3ad98a957..5ce39120c5 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -57,7 +57,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 91f29c6ceb..46eaf5e979 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -83,7 +83,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 444c797f2e..3ac43772ae 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -69,7 +69,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index f93ca9c573..ebe361b5a5 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -78,7 +78,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 5a8a35f8ad..f0329297df 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -76,7 +76,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 70cd3e7fa0..04fda7b2cc 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -73,7 +73,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 3b4e2a4fbf..2bd9b8ce88 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -75,7 +75,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index b1daa41b23..07bf31fd18 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -60,7 +60,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 From 781188097d392563bce09afeb5bdacd0092b9408 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:47 +0800 Subject: [PATCH 29/61] gpio: mpc8xxx_gpio: Fix for litte endian Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++++ arch/arm/include/asm/arch-ls102xa/gpio.h | 16 +++++++ arch/powerpc/include/asm/immap_83xx.h | 13 +++++ drivers/gpio/mpc8xxx_gpio.c | 47 ++++--------------- 4 files changed, 47 insertions(+), 39 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b61666ed4b..b64d7fbc1b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -589,5 +589,15 @@ struct ccsr_serdes { u8 res5[0x19fc - 0xa00]; }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + #endif /*__ASSEMBLY__ */ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h index dad181e7ab..517652b5d0 100644 --- a/arch/arm/include/asm/arch-ls102xa/gpio.h +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -13,4 +13,20 @@ #ifndef __ASM_ARCH_LS102XA_GPIO_H_ #define __ASM_ARCH_LS102XA_GPIO_H_ +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 609869c715..a03f938d9f 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -966,6 +966,19 @@ typedef struct immap { } immap_t; #endif +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + union { + u32 gpibe; + u8 res0[0xE8]; + }; +}; + #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) #define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index a964347fa3..c733603289 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,7 +6,7 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include @@ -16,16 +16,6 @@ #include #include -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; - u32 gpibe; -}; - struct mpc8xxx_gpio_data { /* The bank's register base in memory */ struct ccsr_gpio __iomem *base; @@ -187,32 +177,11 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev); struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - fdt_addr_t addr; - u32 i; - u32 reg[4]; - if (ofnode_read_bool(dev_ofnode(dev), "little-endian")) + if (dev_read_bool(dev, "little-endian")) data->little_endian = true; - if (data->little_endian) - dev_read_u32_array(dev, "reg", reg, 4); - else - dev_read_u32_array(dev, "reg", reg, 2); - - if (data->little_endian) { - for (i = 0; i < 2; i++) - reg[i] = be32_to_cpu(reg[i]); - } - - addr = dev_translate_address(dev, reg); - - plat->addr = addr; - - if (data->little_endian) - plat->size = reg[3]; - else - plat->size = reg[1]; - + plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; - if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) { - unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) - - sizeof(u32); - - out_be32((unsigned int *)gpibe, 0xffffffff); + if (device_is_compatible(dev, "fsl,qoriq-gpio")) { + if (data->little_endian) + out_le32(&data->base->gpibe, 0xffffffff); + else + out_be32(&data->base->gpibe, 0xffffffff); } uc_priv->bank_name = str; From 2b3393cb3c0c58c9ecc0ec78c460621a11ebbe6c Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:48 +0800 Subject: [PATCH 30/61] arm: dts: ls1021a: add gpio node Add gpio node for SoC LS1021A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/ls1021a.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 0eeec43ccc..7b99ce02b3 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -98,6 +98,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1021a-scfg", "syscon"; reg = <0x1570000 0x10000>; From 56093005210e63c22bebd5afbc9ffd73af1f0273 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:49 +0800 Subject: [PATCH 31/61] arm64: dts: ls1012a: add gpio node Add gpio node for SoC LS1012A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index c401ba33ac..2894842cf2 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -71,6 +71,26 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; From f9428d761b9fb3b8848d7f1025ea375675c174e3 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:50 +0800 Subject: [PATCH 32/61] arm64: dts: ls1028a: add gpio node Add gpio node for SoC LS1028A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d0850237c7..5171bf28c7 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -380,6 +380,39 @@ status = "disabled"; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ From b609f1ad046d3563f7d889c595d35b556261d3af Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:51 +0800 Subject: [PATCH 33/61] arm64: dts: ls1043a: add gpio node Add gpio node for SoC LS1043A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1043a.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 8ca57ea7b9..d8171bd03b 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -79,6 +79,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; From b7ddedfab543d096a4c1df36967a67bb6e20816e Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:52 +0800 Subject: [PATCH 34/61] arm64: dts: ls1046a: add gpio node Add gpio node for SoC LS1046A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1046a.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 155455d591..9df419a87d 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -78,6 +78,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; From d62cbea84aed7c5d79dad00d2dbf90897253887f Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:53 +0800 Subject: [PATCH 35/61] arm64: dts: ls1088a: add gpio node Add gpio node for SoC LS1088A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1088a.dtsi | 47 ++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 7b4ac6d3de..64caa600ad 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,9 +2,10 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017, 2020 NXP + * Copyright 2017, 2020-2021 NXP */ +#include / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; @@ -115,6 +116,50 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = ; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; From eeeab2750e95563aebf4baab53e481250711c104 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:54 +0800 Subject: [PATCH 36/61] arm64: dts: ls208xa: add gpio node Add gpio node for SoC LS208xA Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls2080a.dtsi | 46 ++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index f0f4a82c14..7374d580e0 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls2080a SOC common device tree source * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * Copyright 2013-2015 Freescale Semiconductor, Inc. */ @@ -120,6 +120,50 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; From c5d0bd5dc8e68f45ed9711e43c590f072c33a783 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:55 +0800 Subject: [PATCH 37/61] configs: ls1012a: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for SoC LS1012A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1012a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 6cf6a31d76..f6b5d47c25 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -62,6 +62,13 @@ #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) From be7b6d59447ffea9bf01fcd254c6ba2f54a60d78 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:56 +0800 Subject: [PATCH 38/61] configs: ls1043a: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for SoC LS1043A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1043a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6584e39199..4e3e1a946b 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -119,6 +119,13 @@ #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* IFC */ #ifndef SPL_NO_IFC #if defined(CONFIG_TFABOOT) || \ From 90281f4c2721f6ff9c42d8d86e03d6ecb27ccced Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:57 +0800 Subject: [PATCH 39/61] configs: ls1028a: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1028a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 8345cd7acf..1c4af7d176 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -36,6 +36,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C From 97e81208508e641e80f27dbd3f4863b1725eb4ad Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:58 +0800 Subject: [PATCH 40/61] configs: ls1088a: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for LS1088A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1088a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index f9e349871c..b9a956b90b 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -53,6 +53,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C From 04f26d616dc47c3a4d06f9ceb7d39c87b2427d83 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:59 +0800 Subject: [PATCH 41/61] configs: ls208xa: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for LS208xA Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls2080a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 444bb8c3b5..1042555a8c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -66,6 +66,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C From 2a95d7c76faf37b369a3c018f4eba652297bb5cf Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:00 +0800 Subject: [PATCH 42/61] configs: lx2160a: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for SoC LX2160A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 4bd0ddbdad..466484c199 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -160,6 +160,13 @@ #define NXP_FSPI_FLASH_NUM 1 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); From 0077d711c912d59a91887f707e61da302c423be1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:01 +0800 Subject: [PATCH 43/61] configs: ls1046a: enable MPC8XXX_GPIO Enable MPC8XXX_GPIO for SoC LS1046A Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1046a_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index d44a7f105e..32658cf641 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -126,6 +126,13 @@ #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C From 7c1f095acad195c6801d1991506b1e4876bbd8f8 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:02 +0800 Subject: [PATCH 44/61] configs: ls1021atwr: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for board ls1021atwr Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1021atwr.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3e85bb3850..dfb56437d9 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -219,6 +219,13 @@ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID From d58ea6380e42d6881170b8300083f83c1f0e4cfa Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:03 +0800 Subject: [PATCH 45/61] configs: ls1021aqds: enable CONFIG_MPC8XXX_GPIO Enable CONFIG_MPC8XXX_GPIO for board ls1021aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1021aqds.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index eb6f1c1e5b..b4c70333de 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -341,6 +341,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID From 0c6dd9011985c81d50db7651f9beb697007d1b27 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:04 +0800 Subject: [PATCH 46/61] configs: ls1012afrwy: enable CMD_GPIO Enable CMD_GPIO for ls1012afrwy Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index a0217fdd85..2cc4cd3fb8 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 6b8212c76d..9def6655b5 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b85513115f..3d5407d928 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index b773738a6b..30a7ed889d 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y From fb35072ce6f4444f4eb5f93fe10d5592642b852b Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:05 +0800 Subject: [PATCH 47/61] configs: ls1012ardb: enable CMD_GPIO Enable CMD_GPIO for ls1012ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_tfa_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index be59d29dc2..ade297a0a1 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index e6742ecb21..2967877da3 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index fdf4703d20..168d4f759f 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 42bfa9b188..d38272d051 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y From d268833b0d211915c3e84cb85a8fe3dc00e0e850 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:06 +0800 Subject: [PATCH 48/61] configs: ls1021aqds: enable CMD_GPIO Enable CMD_GPIO for board ls1021aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index a581f9bdc0..4053a4e406 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 1bba6f5250..095bc0e3f5 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index c32f5e1948..d8abdb917b 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index ea490708cc..7e1ed5c591 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 7ba5d2d07c..216d0fc470 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 13ce8588d3..7bb003142d 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index dcf0dbb4a6..a606e2ac7c 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 5e6f531ee8..1b2d016901 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 5477d702b2..3f08c28034 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y From 7379bd524641be05534796e1d975f7fe079b3676 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:07 +0800 Subject: [PATCH 49/61] configs: ls1021atwr: enable CMD_GPIO Enable CMD_GPIO for ls1021atwr Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + 7 files changed, 7 insertions(+) diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index f13428d4f0..59c537ad7a 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index a17b66ea4c..8108d160f7 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 10ce045445..91767e0a9f 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index bd9dc934a0..e08f77f06f 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 41b16758f5..e51dab0788 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 5a40bb213a..60e907a2b4 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 957790288d..3365d7399c 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y From dd5186c530d1cdffe1e748ff84767e2f6994d592 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:08 +0800 Subject: [PATCH 50/61] configs: ls1028aqds: enable CMD_GPIO Enable CMD_GPIO for board ls1028aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 14c49cd0d6..7e75a2f121 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 09a6923708..886556b600 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index a3749b5627..1ec187d260 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y From 230b5a6d67fd71fbf5ae264a7bb24f288c5601c6 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:09 +0800 Subject: [PATCH 51/61] configs: ls1028ardb: enable CMD_GPIO Enable CMD_GPIO for board ls1028ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index b034580aef..1f53f436df 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 4bed352420..eb501be091 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y From 614d28b9d01c450ad698b9036eeee18060aef0a7 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:10 +0800 Subject: [PATCH 52/61] configs: ls1043aqds: enable CMD_GPIO Enable CMD_GPIO for board ls1043aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index b24a316e49..b4e100dfa7 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 805e69d8b2..647cf311fb 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 6b8c77b614..a7aad4a19f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 5c07c912cd..6f303fbed4 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 6188ac5e43..32e894760e 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index a6e77fc4f6..65aa811757 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index b426569aab..ddd6b1b1f6 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1e3ac53070..faf0142eff 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 43ac60e18b..ecb0b8daf0 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From 9c7ae9a6c53943d965a194c1a1e3b329306cb1bb Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:11 +0800 Subject: [PATCH 53/61] configs: ls1043ardb: enable CMD_GPIO Enable CMD_GPIO for board ls1043ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 22277a8eb3..c1cede2c59 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -17,6 +17,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index f32573d98e..c45dc20d72 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -17,6 +17,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 84b2950bd6..cfa4ea161d 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index bb0e2bf419..0fab89c5f0 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 34cbd24d0b..849f0d7938 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ff2e669905..f500420338 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 93f9b9a981..e8976304c1 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index a74f124107..4b1f679acb 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -20,6 +20,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From ece1fc4fcad9626d61201a4aab89a0caa4df9c4c Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:12 +0800 Subject: [PATCH 54/61] configs: ls1046ardb: enable CMD_GPIO Enable CMD_GPIO for board ls1046ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index efb88d034f..49b26c1d26 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 50356dca88..8be734b8a4 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index ac1d5abf36..d494c650af 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index b1ac6e0a89..91319c6f0d 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 525caa6881..0a2c71f919 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 069b2282b8..a10262e0b4 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index a4b67a5ca9..a7c68feca9 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 4ed3317018..f8572ccd79 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From 327c539ceaf0250354e94a03c52996d4ed46a217 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:13 +0800 Subject: [PATCH 55/61] configs: ls1046aqds: enable CMD_GPIO Enable CMD_GPIO for board ls1046aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + 9 files changed, 9 insertions(+) diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index ff0f1ccfc4..da63214b55 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 10a23af7b6..13310e5d3a 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 6b07708cae..7ed38abd09 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 03be431622..9e54ed0392 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index deb6ac19a7..1e77ac9d3c 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 4ea8142265..ffe3c6b314 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index b031fce4e1..808625197e 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 49f9cb4b10..d1ce22aca2 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 547848ffeb..95aabde52b 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From 1fd573e5877e57a81fcd0078cdd7b1fb08300ece Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:14 +0800 Subject: [PATCH 56/61] configs: ls2088ardb: enable DM_GPIO and CMD_GPIO Enable DM_GPIO and CMD_GPIO for board ls2088ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_qspi_defconfig | 2 ++ configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + 4 files changed, 6 insertions(+) diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 4dbdc1fcb1..7d7443e6f4 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -17,9 +17,11 @@ CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index f81e2ae6de..58757f2db7 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -20,9 +20,11 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index ccf79c1e64..bd7b4dfdae 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 4277f9cb72..2c60c85cba 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From bf965a2838c28ba128096df85850c31976d54780 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:15 +0800 Subject: [PATCH 57/61] configs: ls2088aqds: enable CMD_GPIO Enable CMD_GPIO for board ls2088aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls2088aqds_tfa_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9e6e9f63ad..f5e8cfbeb4 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y From 010e61339f0a260a9308eb2c5603a499f51492b8 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:16 +0800 Subject: [PATCH 58/61] configs: ls1088aqds: enable DM_GPIO and CMD_GPIO Enable DM_GPIO and CMD_GPIO for board ls1088aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 1 + 6 files changed, 11 insertions(+) diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index e95e871445..f777fc64df 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -20,9 +20,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index a053ea86a7..bd6f364bd9 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -22,9 +22,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 2b0d21d208..c03a9648ec 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -23,9 +23,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 725f6bb0bb..e3ef9340a9 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -31,9 +31,11 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index e775e490b1..549e8242a5 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -33,9 +33,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 019d8995ed..9c65c49f3b 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -29,6 +29,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y From f5a9b76b37177fd99240d611bd77c80fc673c8ae Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:17 +0800 Subject: [PATCH 59/61] configs: ls1088ardb: enable DM_GPIO and CMD_GPIO Enable DM_GPIO and CMD_GPIO for board ls1088ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + 6 files changed, 10 insertions(+) diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index b4fdc00aa5..2c461816bc 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -39,6 +40,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 40fe7c4520..f474119d59 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -24,6 +24,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -42,6 +43,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20300000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 9c7a85fe62..83b99e1236 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -52,6 +53,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SPL_DM=y CONFIG_SCSI_AHCI=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index d409ef3f94..7f49253f53 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -52,6 +53,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 6a07577015..095a85bb59 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -41,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index d9b11eba71..49a49cd6d9 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -46,6 +46,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y From 28e3bfc01f27d464fc5aa0eae7e336cad47f89a5 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:18 +0800 Subject: [PATCH 60/61] configs: lx2160ardb: enable CMD_GPIO Enable CMD_GPIO for board lx2160ardb Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 0551ef0793..a57ed79c11 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 52ac1264ae..bd2e839ee3 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_OPTEE_RPMB=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index d9c1674026..5afb2d055b 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y From 5e7a207ebf8501b4ab1c6a081b7b806698ce0f6d Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:02:19 +0800 Subject: [PATCH 61/61] configs: lx2160aqds: enable CMD_GPIO Enable CMD_GPIO for board lx2160aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index cf4bf8a19a..13f817eedc 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index f0e8dca8f9..2bc023f780 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y