board/freescale/common:QIXIS:Fix magic number usage
QIXIS FPGA layout defines the address of registers but The actual register bit implementation is board-specific, So avoid use of magic numbers as it may vary across different boards's QIXIS FPGA implementation. Also, Avoid board specific defines in common/qixis.h Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -32,22 +32,22 @@ void qixis_write(unsigned int reg, u8 value)
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void qixis_reset(void)
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{
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QIXIS_WRITE(rst_ctl, 0x83);
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QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
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}
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void qixis_bank_reset(void)
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{
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
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QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
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}
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/* Set the boot bank to the power-on default bank0 */
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/* Set the boot bank to the power-on default bank */
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void clear_altbank(void)
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{
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u8 reg;
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reg = QIXIS_READ(brdcfg[0]);
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reg = reg & ~QIXIS_LBMAP_MASK;
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reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
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QIXIS_WRITE(brdcfg[0], reg);
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}
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@ -115,7 +115,8 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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for (i = 0; i < ARRAY_SIZE(period); i++) {
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if (strcmp(argv[2], period[i]) == 0) {
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/* disable watchdog */
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QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
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QIXIS_WRITE(rcfg_ctl,
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rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
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QIXIS_WRITE(watch, ((i<<2) - 1));
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QIXIS_WRITE(rcfg_ctl, rcfg);
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return 0;
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@ -86,12 +86,6 @@ struct qixis {
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u8 res15[16];
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};
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#define QIXIS_BASE 0xffdf0000
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#define QIXIS_LBMAP_SWITCH 7
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_ALTBANK 0x04
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u8 qixis_read(unsigned int reg);
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void qixis_write(unsigned int reg, u8 value);
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