net: Remove lan91c96 driver
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
2e808fadf6
commit
9bd2ab4b39
@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
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obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
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obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
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obj-$(CONFIG_KSZ9477) += ksz9477.o
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obj-$(CONFIG_LAN91C96) += lan91c96.o
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obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
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obj-$(CONFIG_MACB) += macb.o
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obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
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@ -1,799 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*------------------------------------------------------------------------
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* lan91c96.c
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* This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
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* on the SMC91111 driver from U-Boot.
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Rolf Offermanns <rof@sysgo.de>
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*
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* Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
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* Developed by Simple Network Magic Corporation (SNMC)
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* Copyright (C) 1996 by Erik Stahlman (ES)
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*
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* Information contained in this file was obtained from the LAN91C96
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* manual from SMC. To get a copy, if you really want one, you can find
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* information under www.smsc.com.
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*
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* "Features" of the SMC chip:
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* 6144 byte packet memory. ( for the 91C96 )
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* EEPROM for configuration
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* AUI/TP selection ( mine has 10Base2/10BaseT select )
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*
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* Arguments:
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* io = for the base address
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* irq = for the IRQ
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*
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* author:
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* Erik Stahlman ( erik@vt.edu )
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* Daris A Nevil ( dnevil@snmc.com )
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*
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*
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* Hardware multicast code from Peter Cammaert ( pc@denkart.be )
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*
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* Sources:
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* o SMSC LAN91C96 databook (www.smsc.com)
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* o smc91111.c (u-boot driver)
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* o smc9194.c (linux kernel driver)
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* o lan91c96.c (Intel Diagnostic Manager driver)
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*
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* History:
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* 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
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* for lan91c96
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*---------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <malloc.h>
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#include <linux/delay.h>
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#include "lan91c96.h"
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#include <net.h>
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#include <linux/compiler.h>
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/*------------------------------------------------------------------------
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*
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* Configuration options, for the experienced user to change.
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*
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-------------------------------------------------------------------------*/
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/* Use power-down feature of the chip */
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#define POWER_DOWN 0
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/*
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* Wait time for memory to be free. This probably shouldn't be
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* tuned that much, as waiting for this means nothing else happens
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* in the system
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*/
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#define MEMORY_WAIT_TIME 16
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#define SMC_DEBUG 0
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#if (SMC_DEBUG > 2 )
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#define PRINTK3(args...) printf(args)
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#else
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#define PRINTK3(args...)
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#endif
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#if SMC_DEBUG > 1
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#define PRINTK2(args...) printf(args)
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#else
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#define PRINTK2(args...)
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#endif
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#ifdef SMC_DEBUG
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#define PRINTK(args...) printf(args)
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#else
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#define PRINTK(args...)
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#endif
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/*------------------------------------------------------------------------
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*
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* The internal workings of the driver. If you are changing anything
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* here with the SMC stuff, you should have the datasheet and know
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* what you are doing.
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*
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*------------------------------------------------------------------------
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*/
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#define DRIVER_NAME "LAN91C96"
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#define SMC_ALLOC_MAX_TRY 5
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#define SMC_TX_TIMEOUT 30
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#define ETH_ZLEN 60
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#ifdef CONFIG_LAN91C96_USE_32_BIT
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#define USE_32_BIT 1
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#else
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#undef USE_32_BIT
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#endif
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/* See if a MAC address is defined in the current environment. If so use it. If not
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. print a warning and set the environment and other globals with the default.
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. If an EEPROM is present it really should be consulted.
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*/
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static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev);
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static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
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/* ------------------------------------------------------------
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* Internal routines
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* ------------------------------------------------------------
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*/
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static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
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/*
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* This function must be called before smc_open() if you want to override
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* the default mac address.
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*/
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static void smc_set_mac_addr(const unsigned char *addr)
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{
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int i;
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for (i = 0; i < sizeof (smc_mac_addr); i++) {
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smc_mac_addr[i] = addr[i];
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}
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}
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/***********************************************
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* Show available memory *
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***********************************************/
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void dump_memory_info(struct eth_device *dev)
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{
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__maybe_unused word mem_info;
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word old_bank;
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old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF;
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SMC_SELECT_BANK(dev, 0);
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mem_info = SMC_inw(dev, LAN91C96_MIR);
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PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
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SMC_SELECT_BANK(dev, old_bank);
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}
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/*
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* A rather simple routine to print out a packet for debugging purposes.
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*/
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#if SMC_DEBUG > 2
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static void print_packet (byte *, int);
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#endif
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static int poll4int (struct eth_device *dev, byte mask, int timeout)
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{
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int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
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int is_timeout = 0;
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word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT);
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PRINTK2 ("Polling...\n");
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SMC_SELECT_BANK(dev, 2);
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while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) {
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if (get_timer (0) >= tmo) {
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is_timeout = 1;
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break;
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}
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}
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/* restore old bank selection */
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SMC_SELECT_BANK(dev, old_bank);
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if (is_timeout)
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return 1;
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else
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return 0;
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}
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/*
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* Function: smc_reset
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* Purpose:
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* This sets the SMC91111 chip to its normal state, hopefully from whatever
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* mess that any other DOS driver has put it in.
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*
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* Maybe I should reset more registers to defaults in here? SOFTRST should
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* do that for me.
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*
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* Method:
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* 1. send a SOFT RESET
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* 2. wait for it to finish
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* 3. enable autorelease mode
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* 4. reset the memory management unit
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* 5. clear all interrupts
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*
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*/
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static void smc_reset(struct eth_device *dev)
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{
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PRINTK2("%s:smc_reset\n", dev->name);
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/* This resets the registers mostly to defaults, but doesn't
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affect EEPROM. That seems unnecessary */
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SMC_SELECT_BANK(dev, 0);
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SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
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udelay(10);
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/* Disable transmit and receive functionality */
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SMC_outw(dev, 0, LAN91C96_RCR);
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SMC_outw(dev, 0, LAN91C96_TCR);
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/* set the control register */
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SMC_SELECT_BANK(dev, 1);
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SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
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LAN91C96_CONTROL);
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/* Disable all interrupts */
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SMC_outb(dev, 0, LAN91C96_INT_MASK);
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}
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/*
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* Function: smc_enable
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* Purpose: let the chip talk to the outside work
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* Method:
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* 1. Initialize the Memory Configuration Register
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* 2. Enable the transmitter
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* 3. Enable the receiver
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*/
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static void smc_enable(struct eth_device *dev)
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{
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PRINTK2("%s:smc_enable\n", dev->name);
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SMC_SELECT_BANK(dev, 0);
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/* Initialize the Memory Configuration Register. See page
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49 of the LAN91C96 data sheet for details. */
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SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
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/* Initialize the Transmit Control Register */
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SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR);
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/* Initialize the Receive Control Register
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* FIXME:
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* The promiscuous bit set because I could not receive ARP reply
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* packets from the server when I send a ARP request. It only works
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* when I set the promiscuous bit
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*/
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SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
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}
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/*
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* Function: smc_shutdown
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* Purpose: closes down the SMC91xxx chip.
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* Method:
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* 1. zero the interrupt mask
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* 2. clear the enable receive flag
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* 3. clear the enable xmit flags
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*
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* TODO:
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* (1) maybe utilize power down mode.
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* Why not yet? Because while the chip will go into power down mode,
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* the manual says that it will wake up in response to any I/O requests
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* in the register space. Empirical results do not show this working.
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*/
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static void smc_shutdown(struct eth_device *dev)
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{
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PRINTK2("%s:smc_shutdown\n", dev->name);
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/* no more interrupts for me */
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SMC_SELECT_BANK(dev, 2);
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SMC_outb(dev, 0, LAN91C96_INT_MASK);
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/* and tell the card to stay away from that nasty outside world */
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SMC_SELECT_BANK(dev, 0);
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SMC_outb(dev, 0, LAN91C96_RCR);
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SMC_outb(dev, 0, LAN91C96_TCR);
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}
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/*
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* Function: smc_hardware_send_packet(struct net_device * )
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* Purpose:
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* This sends the actual packet to the SMC9xxx chip.
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*
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* Algorithm:
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* First, see if a saved_skb is available.
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* ( this should NOT be called if there is no 'saved_skb'
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* Now, find the packet number that the chip allocated
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* Point the data pointers at it in memory
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* Set the length word in the chip's memory
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* Dump the packet to chip memory
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* Check if a last byte is needed ( odd length packet )
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* if so, set the control flag right
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* Tell the card to send it
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* Enable the transmit interrupt, so I know if it failed
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* Free the kernel data if I actually sent it.
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*/
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static int smc_send_packet(struct eth_device *dev, void *packet,
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int packet_length)
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{
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byte packet_no;
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byte *buf;
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int length;
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int numPages;
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int try = 0;
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int time_out;
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byte status;
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PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
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length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
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/* allocate memory
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** The MMU wants the number of pages to be the number of 256 bytes
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** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
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**
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** The 91C111 ignores the size bits, but the code is left intact
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** for backwards and future compatibility.
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**
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** Pkt size for allocating is data length +6 (for additional status
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** words, length and ctl!)
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**
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** If odd size then last byte is included in this header.
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*/
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numPages = ((length & 0xfffe) + 6);
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numPages >>= 8; /* Divide by 256 */
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if (numPages > 7) {
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printf("%s: Far too big packet error. \n", dev->name);
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return 0;
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}
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/* now, try to allocate the memory */
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SMC_SELECT_BANK(dev, 2);
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SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
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again:
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try++;
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time_out = MEMORY_WAIT_TIME;
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do {
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status = SMC_inb(dev, LAN91C96_INT_STATS);
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if (status & LAN91C96_IST_ALLOC_INT) {
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SMC_outb(dev, LAN91C96_IST_ALLOC_INT,
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LAN91C96_INT_STATS);
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break;
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}
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} while (--time_out);
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if (!time_out) {
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PRINTK2 ("%s: memory allocation, try %d failed ...\n",
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dev->name, try);
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if (try < SMC_ALLOC_MAX_TRY)
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goto again;
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else
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return 0;
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}
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PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
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dev->name, try);
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/* I can send the packet now.. */
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buf = (byte *) packet;
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/* If I get here, I _know_ there is a packet slot waiting for me */
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packet_no = SMC_inb(dev, LAN91C96_ARR);
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if (packet_no & LAN91C96_ARR_FAILED) {
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/* or isn't there? BAD CHIP! */
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printf("%s: Memory allocation failed. \n", dev->name);
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return 0;
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}
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/* we have a packet address, so tell the card to use it */
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SMC_outb(dev, packet_no, LAN91C96_PNR);
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/* point to the beginning of the packet */
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SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
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PRINTK3("%s: Trying to xmit packet of length %x\n",
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dev->name, length);
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#if SMC_DEBUG > 2
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printf ("Transmitting Packet\n");
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print_packet (buf, length);
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#endif
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/* send the packet length ( +6 for status, length and ctl byte )
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and the status word ( set to zeros ) */
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#ifdef USE_32_BIT
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SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH);
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#else
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SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
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/* send the packet length ( +6 for status words, length, and ctl */
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SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH);
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#endif /* USE_32_BIT */
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/* send the actual data
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* I _think_ it's faster to send the longs first, and then
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* mop up by sending the last word. It depends heavily
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* on alignment, at least on the 486. Maybe it would be
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* a good idea to check which is optimal? But that could take
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* almost as much time as is saved?
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*/
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#ifdef USE_32_BIT
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SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2);
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if (length & 0x2)
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SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))),
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LAN91C96_DATA_HIGH);
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#else
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SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1);
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#endif /* USE_32_BIT */
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/* Send the last byte, if there is one. */
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if ((length & 1) == 0) {
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SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
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} else {
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SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
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}
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/* and let the chipset deal with it */
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SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
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/* poll for TX INT */
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if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
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/* sending failed */
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PRINTK2("%s: TX timeout, sending failed...\n", dev->name);
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/* release packet */
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SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
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/* wait for MMU getting ready (low) */
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while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
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udelay(10);
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PRINTK2("MMU ready\n");
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return 0;
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} else {
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/* ack. int */
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SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
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PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
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/* release packet */
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SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
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/* wait for MMU getting ready (low) */
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while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
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udelay(10);
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PRINTK2 ("MMU ready\n");
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}
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return length;
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}
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|
||||
|
||||
/*
|
||||
* Open and Initialize the board
|
||||
*
|
||||
* Set up everything, reset the card, etc ..
|
||||
*
|
||||
*/
|
||||
static int smc_open(struct bd_info *bd, struct eth_device *dev)
|
||||
{
|
||||
int i, err; /* used to set hw ethernet address */
|
||||
|
||||
PRINTK2("%s:smc_open\n", dev->name);
|
||||
|
||||
/* reset the hardware */
|
||||
|
||||
smc_reset(dev);
|
||||
smc_enable(dev);
|
||||
|
||||
SMC_SELECT_BANK(dev, 1);
|
||||
/* set smc_mac_addr, and sync it with u-boot globals */
|
||||
err = smc_get_ethaddr(bd, dev);
|
||||
if (err < 0)
|
||||
return -1;
|
||||
#ifdef USE_32_BIT
|
||||
for (i = 0; i < 6; i += 2) {
|
||||
word address;
|
||||
|
||||
address = smc_mac_addr[i + 1] << 8;
|
||||
address |= smc_mac_addr[i];
|
||||
SMC_outw(dev, address, LAN91C96_IA0 + i);
|
||||
}
|
||||
#else
|
||||
for (i = 0; i < 6; i++)
|
||||
SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------
|
||||
*
|
||||
* smc_rcv - receive a packet from the card
|
||||
*
|
||||
* There is ( at least ) a packet waiting to be read from
|
||||
* chip-memory.
|
||||
*
|
||||
* o Read the status
|
||||
* o If an error, record it
|
||||
* o otherwise, read in the packet
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
static int smc_rcv(struct eth_device *dev)
|
||||
{
|
||||
int packet_number;
|
||||
word status;
|
||||
word packet_length;
|
||||
int is_error = 0;
|
||||
|
||||
#ifdef USE_32_BIT
|
||||
dword stat_len;
|
||||
#endif
|
||||
|
||||
|
||||
SMC_SELECT_BANK(dev, 2);
|
||||
packet_number = SMC_inw(dev, LAN91C96_FIFO);
|
||||
|
||||
if (packet_number & LAN91C96_FIFO_RXEMPTY) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
PRINTK3("%s:smc_rcv\n", dev->name);
|
||||
/* start reading from the start of the packet */
|
||||
SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
|
||||
LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
|
||||
|
||||
/* First two words are status and packet_length */
|
||||
#ifdef USE_32_BIT
|
||||
stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH);
|
||||
status = stat_len & 0xffff;
|
||||
packet_length = stat_len >> 16;
|
||||
#else
|
||||
status = SMC_inw(dev, LAN91C96_DATA_HIGH);
|
||||
packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH);
|
||||
#endif
|
||||
|
||||
packet_length &= 0x07ff; /* mask off top bits */
|
||||
|
||||
PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
|
||||
|
||||
if (!(status & FRAME_FILTER)) {
|
||||
/* Adjust for having already read the first two words */
|
||||
packet_length -= 4; /*4; */
|
||||
|
||||
|
||||
/* set odd length for bug in LAN91C111, */
|
||||
/* which never sets RS_ODDFRAME */
|
||||
/* TODO ? */
|
||||
|
||||
|
||||
#ifdef USE_32_BIT
|
||||
PRINTK3 (" Reading %d dwords (and %d bytes) \n",
|
||||
packet_length >> 2, packet_length & 3);
|
||||
/* QUESTION: Like in the TX routine, do I want
|
||||
to send the DWORDs or the bytes first, or some
|
||||
mixture. A mixture might improve already slow PIO
|
||||
performance */
|
||||
SMC_insl(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
|
||||
packet_length >> 2);
|
||||
/* read the left over bytes */
|
||||
if (packet_length & 3) {
|
||||
int i;
|
||||
|
||||
byte *tail = (byte *)(net_rx_packets[0] +
|
||||
(packet_length & ~3));
|
||||
dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH);
|
||||
|
||||
for (i = 0; i < (packet_length & 3); i++)
|
||||
*tail++ = (byte) (leftover >> (8 * i)) & 0xff;
|
||||
}
|
||||
#else
|
||||
PRINTK3(" Reading %d words and %d byte(s)\n",
|
||||
(packet_length >> 1), packet_length & 1);
|
||||
SMC_insw(dev, LAN91C96_DATA_HIGH, net_rx_packets[0],
|
||||
packet_length >> 1);
|
||||
|
||||
#endif /* USE_32_BIT */
|
||||
|
||||
#if SMC_DEBUG > 2
|
||||
printf ("Receiving Packet\n");
|
||||
print_packet((byte *)net_rx_packets[0], packet_length);
|
||||
#endif
|
||||
} else {
|
||||
/* error ... */
|
||||
/* TODO ? */
|
||||
is_error = 1;
|
||||
}
|
||||
|
||||
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
|
||||
udelay(1); /* Wait until not busy */
|
||||
|
||||
/* error or good, tell the card to get rid of this packet */
|
||||
SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
|
||||
|
||||
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
|
||||
udelay(1); /* Wait until not busy */
|
||||
|
||||
if (!is_error) {
|
||||
/* Pass the packet up to the protocol layers. */
|
||||
net_process_received_packet(net_rx_packets[0], packet_length);
|
||||
return packet_length;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------
|
||||
* smc_close
|
||||
*
|
||||
* this makes the board clean up everything that it can
|
||||
* and not talk to the outside world. Caused by
|
||||
* an 'ifconfig ethX down'
|
||||
*
|
||||
-----------------------------------------------------*/
|
||||
static int smc_close(struct eth_device *dev)
|
||||
{
|
||||
PRINTK2("%s:smc_close\n", dev->name);
|
||||
|
||||
/* clear everything */
|
||||
smc_shutdown(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if SMC_DEBUG > 2
|
||||
static void print_packet(byte *buf, int length)
|
||||
{
|
||||
#if 0
|
||||
int i;
|
||||
int remainder;
|
||||
int lines;
|
||||
|
||||
printf ("Packet of length %d \n", length);
|
||||
|
||||
lines = length / 16;
|
||||
remainder = length % 16;
|
||||
|
||||
for (i = 0; i < lines; i++) {
|
||||
int cur;
|
||||
|
||||
for (cur = 0; cur < 8; cur++) {
|
||||
byte a, b;
|
||||
|
||||
a = *(buf++);
|
||||
b = *(buf++);
|
||||
printf ("%02x%02x ", a, b);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
for (i = 0; i < remainder / 2; i++) {
|
||||
byte a, b;
|
||||
|
||||
a = *(buf++);
|
||||
b = *(buf++);
|
||||
printf ("%02x%02x ", a, b);
|
||||
}
|
||||
printf ("\n");
|
||||
#endif /* 0 */
|
||||
}
|
||||
#endif /* SMC_DEBUG > 2 */
|
||||
|
||||
static int lan91c96_init(struct eth_device *dev, struct bd_info *bd)
|
||||
{
|
||||
return smc_open(bd, dev);
|
||||
}
|
||||
|
||||
static void lan91c96_halt(struct eth_device *dev)
|
||||
{
|
||||
smc_close(dev);
|
||||
}
|
||||
|
||||
static int lan91c96_recv(struct eth_device *dev)
|
||||
{
|
||||
return smc_rcv(dev);
|
||||
}
|
||||
|
||||
static int lan91c96_send(struct eth_device *dev, void *packet,
|
||||
int length)
|
||||
{
|
||||
return smc_send_packet(dev, packet, length);
|
||||
}
|
||||
|
||||
/* smc_get_ethaddr
|
||||
*
|
||||
* This checks both the environment and the ROM for an ethernet address. If
|
||||
* found, the environment takes precedence.
|
||||
*/
|
||||
|
||||
static int smc_get_ethaddr(struct bd_info *bd, struct eth_device *dev)
|
||||
{
|
||||
uchar v_mac[6];
|
||||
|
||||
if (!eth_env_get_enetaddr("ethaddr", v_mac)) {
|
||||
/* get ROM mac value if any */
|
||||
if (!get_rom_mac(dev, v_mac)) {
|
||||
printf("\n*** ERROR: ethaddr is NOT set !!\n");
|
||||
return -1;
|
||||
}
|
||||
eth_env_set_enetaddr("ethaddr", v_mac);
|
||||
}
|
||||
|
||||
smc_set_mac_addr(v_mac); /* use old function to update smc default */
|
||||
PRINTK("Using MAC Address %pM\n", v_mac);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_rom_mac()
|
||||
* Note, this has omly been tested for the OMAP730 P2.
|
||||
*/
|
||||
|
||||
static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac)
|
||||
{
|
||||
int i;
|
||||
SMC_SELECT_BANK(dev, 1);
|
||||
for (i=0; i<6; i++)
|
||||
{
|
||||
v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i);
|
||||
}
|
||||
return (1);
|
||||
}
|
||||
|
||||
/* Structure to detect the device IDs */
|
||||
struct id_type {
|
||||
u8 id;
|
||||
char *name;
|
||||
};
|
||||
static struct id_type supported_chips[] = {
|
||||
{0, ""}, /* Dummy entry to prevent id check failure */
|
||||
{9, "LAN91C110"},
|
||||
{8, "LAN91C100FD"},
|
||||
{7, "LAN91C100"},
|
||||
{5, "LAN91C95"},
|
||||
{4, "LAN91C94/96"},
|
||||
{3, "LAN91C90/92"},
|
||||
};
|
||||
/* lan91c96_detect_chip
|
||||
* See:
|
||||
* http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf
|
||||
* page 71 - that is the closest we get to detect this device
|
||||
*/
|
||||
static int lan91c96_detect_chip(struct eth_device *dev)
|
||||
{
|
||||
u8 chip_id;
|
||||
int r;
|
||||
SMC_SELECT_BANK(dev, 3);
|
||||
chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4;
|
||||
SMC_SELECT_BANK(dev, 0);
|
||||
for (r = 0; r < ARRAY_SIZE(supported_chips); r++)
|
||||
if (chip_id == supported_chips[r].id)
|
||||
return r;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int lan91c96_initialize(u8 dev_num, int base_addr)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
int r = 0;
|
||||
|
||||
dev = malloc(sizeof(*dev));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
|
||||
dev->iobase = base_addr;
|
||||
|
||||
/* Try to detect chip. Will fail if not present. */
|
||||
r = lan91c96_detect_chip(dev);
|
||||
if (!r) {
|
||||
free(dev);
|
||||
return 0;
|
||||
}
|
||||
get_rom_mac(dev, dev->enetaddr);
|
||||
|
||||
dev->init = lan91c96_init;
|
||||
dev->halt = lan91c96_halt;
|
||||
dev->send = lan91c96_send;
|
||||
dev->recv = lan91c96_recv;
|
||||
sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num);
|
||||
|
||||
eth_register(dev);
|
||||
return 0;
|
||||
}
|
||||
@ -1,616 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*------------------------------------------------------------------------
|
||||
* lan91c96.h
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Rolf Offermanns <rof@sysgo.de>
|
||||
* Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
|
||||
* Developed by Simple Network Magic Corporation (SNMC)
|
||||
* Copyright (C) 1996 by Erik Stahlman (ES)
|
||||
*
|
||||
* This file contains register information and access macros for
|
||||
* the LAN91C96 single chip ethernet controller. It is a modified
|
||||
* version of the smc9111.h file.
|
||||
*
|
||||
* Information contained in this file was obtained from the LAN91C96
|
||||
* manual from SMC. To get a copy, if you really want one, you can find
|
||||
* information under www.smsc.com.
|
||||
*
|
||||
* Authors
|
||||
* Erik Stahlman ( erik@vt.edu )
|
||||
* Daris A Nevil ( dnevil@snmc.com )
|
||||
*
|
||||
* History
|
||||
* 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
|
||||
* for lan91c96
|
||||
*-------------------------------------------------------------------------
|
||||
*/
|
||||
#ifndef _LAN91C96_H_
|
||||
#define _LAN91C96_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <config.h>
|
||||
|
||||
/* I want some simple types */
|
||||
|
||||
typedef unsigned char byte;
|
||||
typedef unsigned short word;
|
||||
typedef unsigned long int dword;
|
||||
|
||||
/*
|
||||
* DEBUGGING LEVELS
|
||||
*
|
||||
* 0 for normal operation
|
||||
* 1 for slightly more details
|
||||
* >2 for various levels of increasingly useless information
|
||||
* 2 for interrupt tracking, status flags
|
||||
* 3 for packet info
|
||||
* 4 for complete packet dumps
|
||||
*/
|
||||
/*#define SMC_DEBUG 0 */
|
||||
|
||||
/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
|
||||
|
||||
#define SMC_IO_EXTENT 16
|
||||
|
||||
#ifdef CONFIG_CPU_PXA25X
|
||||
|
||||
#define SMC_IO_SHIFT 0
|
||||
|
||||
#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
|
||||
|
||||
#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
|
||||
#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
|
||||
#define SMC_inb(edev, p) ({ \
|
||||
unsigned int __p = p; \
|
||||
unsigned int __v = SMC_inw(edev, __p & ~1); \
|
||||
if (__p & 1) __v >>= 8; \
|
||||
else __v &= 0xff; \
|
||||
__v; })
|
||||
|
||||
#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
|
||||
#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
|
||||
#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
|
||||
word __w = SMC_inw(edev, (r)&~1); \
|
||||
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
|
||||
__w |= ((r)&1) ? __d<<8 : __d; \
|
||||
SMC_outw(edev, __w, (r)&~1); \
|
||||
})
|
||||
|
||||
#define SMC_outsl(edev, r, b, l) ({ int __i; \
|
||||
dword *__b2; \
|
||||
__b2 = (dword *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
SMC_outl(edev, *(__b2 + __i),\
|
||||
r); \
|
||||
} \
|
||||
})
|
||||
|
||||
#define SMC_outsw(edev, r, b, l) ({ int __i; \
|
||||
word *__b2; \
|
||||
__b2 = (word *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
SMC_outw(edev, *(__b2 + __i),\
|
||||
r); \
|
||||
} \
|
||||
})
|
||||
|
||||
#define SMC_insl(edev, r, b, l) ({ int __i ; \
|
||||
dword *__b2; \
|
||||
__b2 = (dword *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
*(__b2 + __i) = SMC_inl(edev,\
|
||||
r); \
|
||||
SMC_inl(edev, 0); \
|
||||
}; \
|
||||
})
|
||||
|
||||
#define SMC_insw(edev, r, b, l) ({ int __i ; \
|
||||
word *__b2; \
|
||||
__b2 = (word *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
*(__b2 + __i) = SMC_inw(edev,\
|
||||
r); \
|
||||
SMC_inw(edev, 0); \
|
||||
}; \
|
||||
})
|
||||
|
||||
#define SMC_insb(edev, r, b, l) ({ int __i ; \
|
||||
byte *__b2; \
|
||||
__b2 = (byte *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
*(__b2 + __i) = SMC_inb(edev,\
|
||||
r); \
|
||||
SMC_inb(edev, 0); \
|
||||
}; \
|
||||
})
|
||||
|
||||
#else /* if not CONFIG_CPU_PXA25X */
|
||||
|
||||
/*
|
||||
* We have only 16 Bit PCMCIA access on Socket 0
|
||||
*/
|
||||
|
||||
#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
|
||||
#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
|
||||
SMC_inw(edev, r)&0xFF)
|
||||
|
||||
#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
|
||||
#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
|
||||
word __w = SMC_inw(edev, (r)&~1); \
|
||||
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
|
||||
__w |= ((r)&1) ? __d<<8 : __d; \
|
||||
SMC_outw(edev, __w, (r)&~1); \
|
||||
})
|
||||
#define SMC_outsw(edev, r, b, l) ({ int __i; \
|
||||
word *__b2; \
|
||||
__b2 = (word *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
SMC_outw(edev, *(__b2 + __i),\
|
||||
r); \
|
||||
} \
|
||||
})
|
||||
|
||||
#define SMC_insw(edev, r, b, l) ({ int __i ; \
|
||||
word *__b2; \
|
||||
__b2 = (word *) b; \
|
||||
for (__i = 0; __i < l; __i++) { \
|
||||
*(__b2 + __i) = SMC_inw(edev,\
|
||||
r); \
|
||||
SMC_inw(edev, 0); \
|
||||
}; \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Bank Select Field
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
|
||||
#define LAN91C96_BANKSELECT (0x3UC << 0)
|
||||
#define BANK0 0x00
|
||||
#define BANK1 0x01
|
||||
#define BANK2 0x02
|
||||
#define BANK3 0x03
|
||||
#define BANK4 0x04
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* EEPROM Addresses.
|
||||
****************************************************************************
|
||||
*/
|
||||
#define EEPROM_MAC_OFFSET_1 0x6020
|
||||
#define EEPROM_MAC_OFFSET_2 0x6021
|
||||
#define EEPROM_MAC_OFFSET_3 0x6022
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Bank 0 Register Map in I/O Space
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_TCR 0 /* Transmit Control Register */
|
||||
#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
|
||||
#define LAN91C96_RCR 4 /* Receive Control Register */
|
||||
#define LAN91C96_COUNTER 6 /* Counter Register */
|
||||
#define LAN91C96_MIR 8 /* Memory Information Register */
|
||||
#define LAN91C96_MCR 10 /* Memory Configuration Register */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Transmit Control Register - Bank 0 - Offset 0
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_TCR_TXENA (0x1U << 0)
|
||||
#define LAN91C96_TCR_LOOP (0x1U << 1)
|
||||
#define LAN91C96_TCR_FORCOL (0x1U << 2)
|
||||
#define LAN91C96_TCR_TXP_EN (0x1U << 3)
|
||||
#define LAN91C96_TCR_PAD_EN (0x1U << 7)
|
||||
#define LAN91C96_TCR_NOCRC (0x1U << 8)
|
||||
#define LAN91C96_TCR_MON_CSN (0x1U << 10)
|
||||
#define LAN91C96_TCR_FDUPLX (0x1U << 11)
|
||||
#define LAN91C96_TCR_STP_SQET (0x1U << 12)
|
||||
#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
|
||||
#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
|
||||
#define LAN91C96_TCR_FDSE (0x1U << 15)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* EPH Status Register - Bank 0 - Offset 2
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
|
||||
#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
|
||||
#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
|
||||
#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
|
||||
#define LAN91C96_EPHSR_16COL (0x1U << 4)
|
||||
#define LAN91C96_EPHSR_SQET (0x1U << 5)
|
||||
#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
|
||||
#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
|
||||
#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
|
||||
#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
|
||||
#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
|
||||
#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
|
||||
#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
|
||||
|
||||
#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
|
||||
#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
|
||||
|
||||
#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
|
||||
LAN91C96_EPHSR_MUL_COL | \
|
||||
LAN91C96_EPHSR_16COL | \
|
||||
LAN91C96_EPHSR_SQET | \
|
||||
LAN91C96_EPHSR_TX_DEFR | \
|
||||
LAN91C96_EPHSR_LATCOL | \
|
||||
LAN91C96_EPHSR_LOST_CARR | \
|
||||
LAN91C96_EPHSR_EXC_DEF | \
|
||||
LAN91C96_EPHSR_LINK_OK | \
|
||||
LAN91C96_EPHSR_TX_UNRN)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Receive Control Register - Bank 0 - Offset 4
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
|
||||
#define LAN91C96_RCR_PRMS (0x1U << 1)
|
||||
#define LAN91C96_RCR_ALMUL (0x1U << 2)
|
||||
#define LAN91C96_RCR_RXEN (0x1U << 8)
|
||||
#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
|
||||
#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
|
||||
#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Counter Register - Bank 0 - Offset 6
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
|
||||
#define LAN91C96_ECR_MULT_COL (0xFU << 5)
|
||||
#define LAN91C96_ECR_DEF_TX (0xFU << 8)
|
||||
#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Memory Information Register - Bank 0 - OFfset 8
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Memory Configuration Register - Bank 0 - Offset 10
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
|
||||
#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
|
||||
#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
|
||||
|
||||
#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Bank 1 Register Map in I/O Space
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_CONFIG 0 /* Configuration Register */
|
||||
#define LAN91C96_BASE 2 /* Base Address Register */
|
||||
#define LAN91C96_IA0 4 /* Individual Address Register - 0 */
|
||||
#define LAN91C96_IA1 5 /* Individual Address Register - 1 */
|
||||
#define LAN91C96_IA2 6 /* Individual Address Register - 2 */
|
||||
#define LAN91C96_IA3 7 /* Individual Address Register - 3 */
|
||||
#define LAN91C96_IA4 8 /* Individual Address Register - 4 */
|
||||
#define LAN91C96_IA5 9 /* Individual Address Register - 5 */
|
||||
#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
|
||||
#define LAN91C96_CONTROL 12 /* Control Register */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Configuration Register - Bank 1 - Offset 0
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
|
||||
#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
|
||||
#define LAN91C96_CR_RES (0x3U << 3)
|
||||
#define LAN91C96_CR_DIS_LINK (0x1U << 6)
|
||||
#define LAN91C96_CR_16BIT (0x1U << 7)
|
||||
#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
|
||||
#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
|
||||
#define LAN91C96_CR_FULL_STEP (0x1U << 10)
|
||||
#define LAN91C96_CR_NO_WAIT (0x1U << 12)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Base Address Register - Bank 1 - Offset 2
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_BAR_RA_BITS (0x27U << 0)
|
||||
#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
|
||||
#define LAN91C96_BAR_A_BITS (0xFFU << 8)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Control Register - Bank 1 - Offset 12
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_CTR_STORE (0x1U << 0)
|
||||
#define LAN91C96_CTR_RELOAD (0x1U << 1)
|
||||
#define LAN91C96_CTR_EEPROM (0x1U << 2)
|
||||
#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
|
||||
#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
|
||||
#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
|
||||
#define LAN91C96_CTR_BIT_8 (0x1U << 8)
|
||||
#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
|
||||
#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
|
||||
#define LAN91C96_CTR_PWRDN (0x1U << 13)
|
||||
#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Bank 2 Register Map in I/O Space
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MMU 0 /* MMU Command Register */
|
||||
#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
|
||||
#define LAN91C96_PNR 2 /* Packet Number Register */
|
||||
#define LAN91C96_ARR 3 /* Allocation Result Register */
|
||||
#define LAN91C96_FIFO 4 /* FIFO Ports Register */
|
||||
#define LAN91C96_POINTER 6 /* Pointer Register */
|
||||
#define LAN91C96_DATA_HIGH 8 /* Data High Register */
|
||||
#define LAN91C96_DATA_LOW 10 /* Data Low Register */
|
||||
#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
|
||||
#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
|
||||
#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* MMU Command Register - Bank 2 - Offset 0
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
|
||||
#define LAN91C96_MMUCR_N1 (0x1U << 1)
|
||||
#define LAN91C96_MMUCR_N2 (0x1U << 2)
|
||||
#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
|
||||
#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
|
||||
#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
|
||||
#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
|
||||
#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
|
||||
#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
|
||||
#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
|
||||
#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
|
||||
#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Auto Tx Start Register - Bank 2 - Offset 1
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_AUTOTX (0xFFU << 0)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Packet Number Register - Bank 2 - Offset 2
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_PNR_TX (0x1FU << 0)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Allocation Result Register - Bank 2 - Offset 3
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
|
||||
#define LAN91C96_ARR_FAILED (0x1U << 7)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* FIFO Ports Register - Bank 2 - Offset 4
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
|
||||
#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
|
||||
#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
|
||||
#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Pointer Register - Bank 2 - Offset 6
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_PTR_LOW (0xFFU << 0)
|
||||
#define LAN91C96_PTR_HIGH (0x7U << 8)
|
||||
#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
|
||||
#define LAN91C96_PTR_ETEN (0x1U << 12)
|
||||
#define LAN91C96_PTR_READ (0x1U << 13)
|
||||
#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
|
||||
#define LAN91C96_PTR_RCV (0x1U << 15)
|
||||
|
||||
#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
|
||||
LAN91C96_PTR_AUTO_INCR | \
|
||||
LAN91C96_PTR_READ)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Data Register - Bank 2 - Offset 8
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
|
||||
#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Interrupt Status Register - Bank 2 - Offset 12
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_IST_RCV_INT (0x1U << 0)
|
||||
#define LAN91C96_IST_TX_INT (0x1U << 1)
|
||||
#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
|
||||
#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
|
||||
#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
|
||||
#define LAN91C96_IST_EPH_INT (0x1U << 5)
|
||||
#define LAN91C96_IST_ERCV_INT (0x1U << 6)
|
||||
#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Interrupt Acknowledge Register - Bank 2 - Offset 12
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ACK_TX_INT (0x1U << 1)
|
||||
#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
|
||||
#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
|
||||
#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Interrupt Mask Register - Bank 2 - Offset 13
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MSK_RCV_INT (0x1U << 0)
|
||||
#define LAN91C96_MSK_TX_INT (0x1U << 1)
|
||||
#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
|
||||
#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
|
||||
#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
|
||||
#define LAN91C96_MSK_EPH_INT (0x1U << 5)
|
||||
#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
|
||||
#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Bank 3 Register Map in I/O Space
|
||||
**************************************************************************
|
||||
*/
|
||||
#define LAN91C96_MGMT_MDO (0x1U << 0)
|
||||
#define LAN91C96_MGMT_MDI (0x1U << 1)
|
||||
#define LAN91C96_MGMT_MCLK (0x1U << 2)
|
||||
#define LAN91C96_MGMT_MDOE (0x1U << 3)
|
||||
#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
|
||||
#define LAN91C96_MGMT_IOS0 (0x1U << 8)
|
||||
#define LAN91C96_MGMT_IOS1 (0x1U << 9)
|
||||
#define LAN91C96_MGMT_IOS2 (0x1U << 10)
|
||||
#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
|
||||
#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Revision Register - Bank 3 - Offset 10
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_REV_REVID (0xFU << 0)
|
||||
#define LAN91C96_REV_CHIPID (0xFU << 4)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Early RCV Register - Bank 3 - Offset 12
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
|
||||
#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* PCMCIA Configuration Registers
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
|
||||
#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* PCMCIA Ethernet Configuration Option Register (ECOR)
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ECOR_ENABLE (0x1U << 0)
|
||||
#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
|
||||
#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
|
||||
#define LAN91C96_ECOR_SRESET (0x1U << 7)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* PCMCIA Ethernet Configuration and Status Register (ECSR)
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_ECSR_INTR (0x1U << 1)
|
||||
#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
|
||||
#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Receive Frame Status Word - See page 38 of the LAN91C96 specification.
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_TOO_SHORT (0x1U << 10)
|
||||
#define LAN91C96_TOO_LONG (0x1U << 11)
|
||||
#define LAN91C96_ODD_FRM (0x1U << 12)
|
||||
#define LAN91C96_BAD_CRC (0x1U << 13)
|
||||
#define LAN91C96_BROD_CAST (0x1U << 14)
|
||||
#define LAN91C96_ALGN_ERR (0x1U << 15)
|
||||
|
||||
#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Default MAC Address
|
||||
****************************************************************************
|
||||
*/
|
||||
#define MAC_DEF_HI 0x0800
|
||||
#define MAC_DEF_MED 0x3333
|
||||
#define MAC_DEF_LO 0x0100
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* Default I/O Signature - 0x33
|
||||
****************************************************************************
|
||||
*/
|
||||
#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
|
||||
#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
|
||||
#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
|
||||
|
||||
#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
|
||||
#define ETHERNET_MAX_LENGTH 1514
|
||||
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* I define some macros to make it easier to do somewhat common
|
||||
* or slightly complicated, repeated tasks.
|
||||
*-------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* select a register bank, 0 to 3 */
|
||||
|
||||
#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
|
||||
|
||||
/* this enables an interrupt in the interrupt mask register */
|
||||
#define SMC_ENABLE_INT(edev, x) {\
|
||||
unsigned char mask;\
|
||||
SMC_SELECT_BANK(edev, 2);\
|
||||
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
|
||||
mask |= (x);\
|
||||
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
|
||||
}
|
||||
|
||||
/* this disables an interrupt from the interrupt mask register */
|
||||
|
||||
#define SMC_DISABLE_INT(edev, x) {\
|
||||
unsigned char mask;\
|
||||
SMC_SELECT_BANK(edev, 2);\
|
||||
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
|
||||
mask &= ~(x);\
|
||||
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* Define the interrupts that I want to receive from the card
|
||||
*
|
||||
* I want:
|
||||
* LAN91C96_IST_EPH_INT, for nasty errors
|
||||
* LAN91C96_IST_RCV_INT, for happy received packets
|
||||
* LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
|
||||
*-------------------------------------------------------------------------
|
||||
*/
|
||||
#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
|
||||
|
||||
#endif /* _LAN91C96_H_ */
|
||||
Loading…
Reference in New Issue
Block a user