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sunxi: Also set Auxiliary Ctl SMP bit in SPL

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There is no reason not to and this make the #ifdef-ery easier to read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Hans de Goede 2015-04-06 20:16:36 +02:00
parent dcfa530f09
commit 92bcc6cb1e
1 changed files with 3 additions and 2 deletions
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5
arch/arm/cpu/armv7/sunxi/board.c
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@ -94,8 +94,9 @@ void s_init(void)
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN8I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"