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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga

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- Various gen5 fixes
This commit is contained in:
Tom Rini
2019-07-29 09:03:11 -04:00
parent ad4a699cfe a89c2adc3d
commit 92430b8fc8
21 changed files with 893 additions and 698 deletions
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4
arch/arm/Kconfig
View File

@@ -895,10 +895,14 @@ config ARCH_SOCFPGA
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY

1
arch/arm/mach-socfpga/Makefile
View File

@@ -8,7 +8,6 @@
obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o

1
arch/arm/mach-socfpga/include/mach/reset_manager.h
View File

@@ -11,6 +11,7 @@ void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
/*

41
arch/arm/mach-socfpga/reset_manager.c
View File

@@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include <asm/arch/mailbox_s10.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
#endif
/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
{
/* request a warm reset */
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
mbox_reset_cold();
#else
writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
&reset_manager_base->ctrl);
#endif
/*
* infinite loop here as watchdog will trigger and reset
* the processor
*/
while (1)
;
}