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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga

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- Various gen5 fixes
This commit is contained in:
Tom Rini 2019-07-29 09:03:11 -04:00
commit 92430b8fc8
21 changed files with 893 additions and 698 deletions
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1
MAINTAINERS
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@ -94,6 +94,7 @@ M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
S: Maintainted
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
M: Neil Armstrong <narmstrong@baylibre.com>

4
arch/arm/Kconfig
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@ -895,10 +895,14 @@ config ARCH_SOCFPGA
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY

1
arch/arm/mach-socfpga/Makefile
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@ -8,7 +8,6 @@
obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o

1
arch/arm/mach-socfpga/include/mach/reset_manager.h
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@ -11,6 +11,7 @@ void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
/*

41
arch/arm/mach-socfpga/reset_manager.c
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@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include <asm/arch/mailbox_s10.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
#endif
/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
{
/* request a warm reset */
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
mbox_reset_cold();
#else
writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
&reset_manager_base->ctrl);
#endif
/*
* infinite loop here as watchdog will trigger and reset
* the processor
*/
while (1)
;
}

1
configs/evb-rk3036_defconfig
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@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PINCTRL=y
# CONFIG_SPL_DM_SERIAL is not set
# CONFIG_SPL_SYSRESET is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y

1
configs/kylin-rk3036_defconfig
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@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_DM_SERIAL is not set
# CONFIG_SPL_SYSRESET is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y

1
configs/sandbox_spl_defconfig
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@ -3,6 +3,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_FIRMWARE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0

6
drivers/Makefile
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@ -4,7 +4,9 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
obj-$(CONFIG_$(SPL_TPL_)DM) += core/
obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/
obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/
obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/
obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/
obj-$(CONFIG_$(SPL_TPL_)LED) += led/
@ -81,7 +83,6 @@ obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
obj-y += firmware/
obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
@ -96,7 +97,6 @@ obj-y += rtc/
obj-y += scsi/
obj-y += sound/
obj-y += spmi/
obj-y += sysreset/
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/

1354
drivers/ddr/altera/sequencer.c
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File diff suppressed because it is too large Load Diff

36
drivers/ddr/altera/sequencer.h
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@ -6,14 +6,16 @@
#ifndef _SEQUENCER_H_
#define _SEQUENCER_H_
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
/ rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
/ rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
/ seq->rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
seq->rwcfg->true_mem_data_mask_width \
/ seq->rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
/ rwcfg->mem_if_write_dqs_width)
#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
/ seq->rwcfg->mem_if_write_dqs_width)
#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
/ NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
@ -256,6 +258,26 @@ struct socfpga_sdr {
u8 _align9[0xea4];
};
struct socfpga_sdrseq {
const struct socfpga_sdram_rw_mgr_config *rwcfg;
const struct socfpga_sdram_io_config *iocfg;
const struct socfpga_sdram_misc_config *misccfg;
/* calibration steps requested by the rtl */
u16 dyn_calib_steps;
/*
* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
* instead of static, we use boolean logic to select between
* non-skip and skip values
*
* The mask is set to include all bits when not-skipping, but is
* zero when skipping
*/
u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
struct gbl_type gbl;
struct param_type param;
};
int sdram_calibration_full(struct socfpga_sdr *sdr);
#endif /* _SEQUENCER_H_ */

7
drivers/firmware/Kconfig
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@ -1,9 +1,13 @@
config FIRMWARE
bool "Enable Firmware driver support"
config SPL_FIRMWARE
bool "Enable Firmware driver support in SPL"
depends on FIRMWARE
config SPL_ARM_PSCI_FW
bool
select FIRMWARE
select SPL_FIRMWARE
config ARM_PSCI_FW
bool
@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL
tristate "TI System Control Interface (TISCI) Message Protocol"
depends on K3_SEC_PROXY
select FIRMWARE
select SPL_FIRMWARE if SPL
help
TI System Control Interface (TISCI) Message Protocol is used to manage
compute systems such as ARM, DSP etc with the system controller in

9
drivers/fpga/socfpga_arria10.c
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@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
fpgamgr_program_write(rbf_data, rbf_size);
status = fpgamgr_program_finish();
if (status) {
config_pins(gd->fdt_blob, "fpga");
puts("FPGA: Enter user mode.\n");
}
if (status)
return status;
config_pins(gd->fdt_blob, "fpga");
puts("FPGA: Enter user mode.\n");
return status;
}

19
drivers/reset/reset-socfpga.c
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@ -14,6 +14,7 @@
#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/of_access.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev)
return 0;
}
static int socfpga_reset_bind(struct udevice *dev)
{
int ret;
struct udevice *sys_child;
/*
* The sysreset driver does not have a device node, so bind it here.
* Bind it to the node, too, so that it can get its base address.
*/
ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
dev->node, &sys_child);
if (ret)
debug("Warning: No sysreset driver: ret=%d\n", ret);
return 0;
}
static const struct udevice_id socfpga_reset_match[] = {
{ .compatible = "altr,rst-mgr" },
{ /* sentinel */ },
@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
.name = "socfpga-reset",
.id = UCLASS_RESET,
.of_match = socfpga_reset_match,
.bind = socfpga_reset_bind,
.probe = socfpga_reset_probe,
.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
.ops = &socfpga_reset_ops,

15
drivers/sysreset/Kconfig
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@ -50,10 +50,25 @@ config SYSRESET_MICROBLAZE
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
select SPL_ARM_PSCI_FW if SPL
help
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
config SYSRESET_SOCFPGA
bool "Enable support for Intel SOCFPGA family"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
help
This enables the system reset driver support for Intel SOCFPGA SoCs
(Cyclone 5, Arria 5 and Arria 10).
config SYSRESET_SOCFPGA_S10
bool "Enable support for Intel SOCFPGA Stratix 10"
depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
help
This enables the system reset driver support for Intel SOCFPGA
Stratix SoCs.
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
depends on TI_SCI_PROTOCOL

2
drivers/sysreset/Makefile
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@ -11,6 +11,8 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o

56
drivers/sysreset/sysreset_socfpga.c Normal file
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@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Pepperl+Fuchs
* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
struct socfpga_sysreset_data {
struct socfpga_reset_manager *rstmgr_base;
};
static int socfpga_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
struct socfpga_sysreset_data *data = dev_get_priv(dev);
switch (type) {
case SYSRESET_WARM:
writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
&data->rstmgr_base->ctrl);
break;
case SYSRESET_COLD:
writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
&data->rstmgr_base->ctrl);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static int socfpga_sysreset_probe(struct udevice *dev)
{
struct socfpga_sysreset_data *data = dev_get_priv(dev);
data->rstmgr_base = devfdt_get_addr_ptr(dev);
return 0;
}
static struct sysreset_ops socfpga_sysreset = {
.request = socfpga_sysreset_request,
};
U_BOOT_DRIVER(sysreset_socfpga) = {
.id = UCLASS_SYSRESET,
.name = "socfpga_sysreset",
.priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data),
.ops = &socfpga_sysreset,
.probe = socfpga_sysreset_probe,
};

29
drivers/sysreset/sysreset_socfpga_s10.c Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Pepperl+Fuchs
* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/arch/mailbox_s10.h>
static int socfpga_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
mbox_reset_cold();
return -EINPROGRESS;
}
static struct sysreset_ops socfpga_sysreset = {
.request = socfpga_sysreset_request,
};
U_BOOT_DRIVER(sysreset_socfpga) = {
.id = UCLASS_SYSRESET,
.name = "socfpga_sysreset",
.ops = &socfpga_sysreset,
};

3
include/configs/socfpga_dbm_soc1.h
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@ -87,7 +87,8 @@
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
"fi\0"
"fi\0" \
"socfpga_legacy_reset_compat=1\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

3
include/configs/socfpga_stratix10_socdk.h
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@ -113,7 +113,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"scriptaddr=0x02100000\0" \
"scriptfile=u-boot.scr\0" \
"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
"then source ${scriptaddr}; fi\0"
"then source ${scriptaddr}; fi\0" \
"socfpga_legacy_reset_compat=1\0"
/*
* Generic Interrupt Controller Definitions

1
include/configs/socfpga_vining_fpga.h
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@ -145,6 +145,7 @@
"run ubi_ubi ; " \
"else echo \"Unsupported boot mode: \"${bootmode} ; " \
"fi\0" \
"socfpga_legacy_reset_compat=1\0"
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE