Merge git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
Tom Rini
@@ -116,6 +116,67 @@
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#define CONFIG_SYS_FSL_ERRATUM_A008751
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_ARCH_LS1088A)
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
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#define CONFIG_GICV3
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#define CONFIG_FSL_TZPC_BP147
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#define CONFIG_FSL_TZASC_400
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define SRDS_MAX_LANES 4
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_IFC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* SFP */
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#define CONFIG_SYS_FSL_SFP_VER_3_4
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#define CONFIG_SYS_FSL_SFP_LE
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#define CONFIG_SYS_FSL_SRK_LE
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/* Security Monitor */
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#define CONFIG_SYS_FSL_SEC_MON_LE
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/* Secure Boot */
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#define CONFIG_ESBC_HDR_LS
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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@@ -218,7 +279,6 @@
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#define GICC_BASE 0x01420000
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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@@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
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CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
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CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
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CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
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CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
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CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
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CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
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};
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#ifndef CONFIG_SYS_DCACHE_OFF
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@@ -199,7 +203,8 @@ static struct mm_region final_map[] = {
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},
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{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
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CONFIG_SYS_FSL_QSPI_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
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CONFIG_SYS_FSL_QSPI_SIZE2,
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@@ -208,7 +213,8 @@ static struct mm_region final_map[] = {
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},
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
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CONFIG_SYS_FSL_IFC_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE,
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@@ -9,7 +9,7 @@
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#include <config.h>
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#ifdef CONFIG_ARCH_LS2080A
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#ifdef CONFIG_FSL_LSCH3
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enum srds_prtcl {
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/*
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* Nobody will check whether the device 'NONE' has been configured,
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@@ -158,6 +158,8 @@ void fsl_serdes_init(void);
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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int is_serdes_prtcl_valid(int serdes, u32 prtcl);
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int serdes_get_number(int serdes, int cfg);
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void fsl_rgmii_init(void);
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#ifdef CONFIG_FSL_LSCH2
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const char *serdes_clock_to_string(u32 clock);
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@@ -15,7 +15,6 @@
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#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
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#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
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@@ -338,6 +337,25 @@ struct ccsr_gur {
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#define SCFG_USBPWRFAULT_USB2_SHIFT 2
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#define SCFG_USBPWRFAULT_USB1_SHIFT 0
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#define SCFG_BASE 0x01570000
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#define SCFG_USB3PRM1CR_USB1 0x070
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#define SCFG_USB3PRM2CR_USB1 0x074
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#define SCFG_USB3PRM1CR_USB2 0x07C
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#define SCFG_USB3PRM2CR_USB2 0x080
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#define SCFG_USB3PRM1CR_USB3 0x088
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#define SCFG_USB3PRM2CR_USB3 0x08c
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#define SCFG_USB_TXVREFTUNE 0x9
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#define SCFG_USB_SQRXTUNE_MASK 0x7
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#define SCFG_USB_PCSTXSWINGFULL 0x47
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#define SCFG_USB_PHY1 0x084F0000
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#define SCFG_USB_PHY2 0x08500000
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#define SCFG_USB_PHY3 0x08510000
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#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
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#define USB_PHY_RX_EQ_VAL_1 0x0000
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#define USB_PHY_RX_EQ_VAL_2 0x0080
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#define USB_PHY_RX_EQ_VAL_3 0x0380
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#define USB_PHY_RX_EQ_VAL_4 0x0b80
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#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
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#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
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#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
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@@ -544,54 +562,6 @@ struct ccsr_serdes {
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u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
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};
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#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
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#define CCI400_CTRLORD_EN_BARRIER 0
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#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
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#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
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#define CCI400_SNOOP_REQ_EN 0x00000001
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/* CCI-400 registers */
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struct ccsr_cci400 {
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u32 ctrl_ord; /* Control Override */
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u32 spec_ctrl; /* Speculation Control */
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u32 secure_access; /* Secure Access */
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u32 status; /* Status */
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u32 impr_err; /* Imprecise Error */
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u8 res_14[0x100 - 0x14];
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u32 pmcr; /* Performance Monitor Control */
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u8 res_104[0xfd0 - 0x104];
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u32 pid[8]; /* Peripheral ID */
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u32 cid[4]; /* Component ID */
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struct {
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u32 snoop_ctrl; /* Snoop Control */
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u32 sha_ord; /* Shareable Override */
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u8 res_1008[0x1100 - 0x1008];
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u32 rc_qos_ord; /* read channel QoS Value Override */
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u32 wc_qos_ord; /* read channel QoS Value Override */
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u8 res_1108[0x110c - 0x1108];
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u32 qos_ctrl; /* QoS Control */
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u32 max_ot; /* Max OT */
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u8 res_1114[0x1130 - 0x1114];
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u32 target_lat; /* Target Latency */
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u32 latency_regu; /* Latency Regulation */
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u32 qos_range; /* QoS Range */
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u8 res_113c[0x2000 - 0x113c];
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} slave[5]; /* Slave Interface */
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u8 res_6000[0x9004 - 0x6000];
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u32 cycle_counter; /* Cycle counter */
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u32 count_ctrl; /* Count Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_9010[0xa000 - 0x9010];
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struct {
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u32 event_select; /* Event Select */
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u32 event_count; /* Event Count */
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u32 counter_ctrl; /* Counter Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_a010[0xb000 - 0xa010];
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} pcounter[4]; /* Performance Counter */
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u8 res_e004[0x10000 - 0xe004];
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};
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/* MMU 500 */
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#define SMMU_SCR0 (SMMU_BASE + 0x0)
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#define SMMU_SCR1 (SMMU_BASE + 0x4)
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@@ -107,10 +107,16 @@
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
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#ifdef CONFIG_ARCH_LS1088A
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
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#else
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
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#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
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#endif
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/* Device Configuration */
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#define DCFG_BASE 0x01e00000
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@@ -133,8 +139,19 @@
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#define SCFG_BASE 0x01fc0000
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#define SCFG_USB3PRM1CR 0x000
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#define SCFG_USB3PRM1CR_INIT 0x27672b2a
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#define SCFG_USB_TXVREFTUNE 0x9
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#define SCFG_USB_SQRXTUNE_MASK 0x7
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#define SCFG_QSPICLKCTLR 0x10
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#define DCSR_BASE 0x700000000ULL
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#define DCSR_USB_PHY1 0x4600000
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#define DCSR_USB_PHY2 0x4610000
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#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
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#define USB_PHY_RX_EQ_VAL_1 0x0000
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#define USB_PHY_RX_EQ_VAL_2 0x0080
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#define USB_PHY_RX_EQ_VAL_3 0x0380
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#define USB_PHY_RX_EQ_VAL_4 0x0b80
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#define TP_ITYP_AV 0x00000001 /* Initiator available */
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#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
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#define TP_ITYP_TYPE_ARM 0x0
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@@ -246,6 +263,23 @@ struct ccsr_gur {
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#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
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#define FSL_CHASSIS3_SRDS1_REGSR 29
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#define FSL_CHASSIS3_SRDS2_REGSR 29
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#elif defined(CONFIG_ARCH_LS1088A)
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#define FSL_CHASSIS3_EC1_REGSR 26
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#define FSL_CHASSIS3_EC2_REGSR 26
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#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
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#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
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#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
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#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
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#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
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#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
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#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
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#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
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#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
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#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
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#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
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#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
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#define FSL_CHASSIS3_SRDS1_REGSR 29
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#define FSL_CHASSIS3_SRDS2_REGSR 30
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#endif
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#define RCW_SB_EN_REG_INDEX 9
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#define RCW_SB_EN_MASK 0x00000400
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@@ -29,9 +29,13 @@
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#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define scfg_in32(a) in_le32(a)
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#define scfg_out32(a, v) out_le32(a, v)
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#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
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#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
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#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
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#define scfg_in32(a) in_be32(a)
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#define scfg_out32(a, v) out_be32(a, v)
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#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
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#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
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#endif
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#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
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@@ -57,6 +61,10 @@ struct cpu_type {
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#define SVR_LS1023A 0x879208
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#define SVR_LS1046A 0x870700
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#define SVR_LS1026A 0x870708
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#define SVR_LS1048A 0x870320
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#define SVR_LS1084A 0x870302
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#define SVR_LS1088A 0x870300
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#define SVR_LS1044A 0x870322
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#define SVR_LS2045A 0x870120
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#define SVR_LS2080A 0x870110
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#define SVR_LS2085A 0x870100
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@@ -66,12 +66,26 @@
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#define FSL_USB2_STREAM_ID 2
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#define FSL_SDMMC_STREAM_ID 3
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#define FSL_SATA1_STREAM_ID 4
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#if defined(CONFIG_ARCH_LS2080A)
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#define FSL_SATA2_STREAM_ID 5
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#endif
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#if defined(CONFIG_ARCH_LS2080A)
|
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#define FSL_DMA_STREAM_ID 6
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#elif defined(CONFIG_ARCH_LS1088A)
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#define FSL_DMA_STREAM_ID 5
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#endif
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/* PCI - programmed in PEXn_LUT */
|
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#define FSL_PEX_STREAM_ID_START 7
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#if defined(CONFIG_ARCH_LS2080A)
|
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#define FSL_PEX_STREAM_ID_END 22
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#elif defined(CONFIG_ARCH_LS1088A)
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#define FSL_PEX_STREAM_ID_END 18
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#endif
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/* DPAA2 - set in MC DPC and alloced by MC */
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#define FSL_DPAA2_STREAM_ID_START 23
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@@ -20,7 +20,6 @@
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#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
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@@ -6,6 +6,7 @@
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|
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#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
|
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#define __ASM_ARCH_LS102XA_IMMAP_H_
|
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#include <fsl_immap.h>
|
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|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
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@@ -173,6 +174,21 @@ struct ccsr_gur {
|
||||
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
|
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#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
|
||||
|
||||
#define SCFG_BASE 0x01570000
|
||||
#define SCFG_USB3PRM1CR 0x070
|
||||
#define SCFG_USB_TXVREFTUNE 0x9
|
||||
#define SCFG_USB_SQRXTUNE_MASK 0x7
|
||||
#define SCFG_USB3PRM2CR 0x074
|
||||
#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
|
||||
#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
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|
||||
#define USB_PHY_BASE 0x08510000
|
||||
#define USB_PHY_RX_OVRD_IN_HI 0x200c
|
||||
#define USB_PHY_RX_EQ_VAL_1 0x0000
|
||||
#define USB_PHY_RX_EQ_VAL_2 0x8000
|
||||
#define USB_PHY_RX_EQ_VAL_3 0x8004
|
||||
#define USB_PHY_RX_EQ_VAL_4 0x800C
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr;
|
||||
@@ -374,53 +390,7 @@ struct ccsr_serdes {
|
||||
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
|
||||
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
|
||||
#define CCI400_SNOOP_REQ_EN 0x00000001
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
/* AHCI (sata) register map */
|
||||
struct ccsr_ahci {
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@@ -71,55 +72,49 @@
|
||||
* DDR memory map
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x580e00000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa0e00000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x20600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000
|
||||
#else /* NOR BOOT */
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x580600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
|
||||
#endif /*ifdef CONFIG_QSPI_BOOT */
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00004000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa0600000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
|
||||
#else
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
/* For SD boot address and size are assigned in terms of sector
|
||||
* offset and no. of sectors respectively.
|
||||
*/
|
||||
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
|
||||
#else
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
|
||||
#endif
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00000940
|
||||
#define CONFIG_BS_HDR_SIZE 0x00000010
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00003000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
|
||||
#define CONFIG_BS_SIZE 0x00000008
|
||||
#define CONFIG_BS_HDR_SIZE 0x00000010
|
||||
#elif defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00802000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#elif defined(CONFIG_QSPI_BOOT)
|
||||
#ifdef CONFIG_ARCH_LS1046A
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x40800000
|
||||
#elif defined(CONFIG_ARCH_LS1012A)
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x40060000
|
||||
#else
|
||||
#error "Platform not supported"
|
||||
#endif
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x40600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#else /* Default NOR Boot */
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x60060000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x60600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#endif
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
|
||||
#define CONFIG_BS_ADDR_RAM 0x81020000
|
||||
#define CONFIG_BS_ADDR_RAM 0x81000000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
|
||||
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
|
||||
#else
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
|
||||
/* BOOTSCRIPT_ADDR is not required */
|
||||
|
||||
Reference in New Issue
Block a user