Coldfire: M5271EVB: Board header update (dependencies)
Cleanup for M5271EVB: Added clarification on the use of CONFIG_SYS_CLOCK. Modified to use u-boot's HUSH parser. Cleanup on environment settings. Removed compiler warning by defining CONFIG_SYS_CS0_* Dependencies: Added the use of CONFIG_SYS_MCF_SYNCR for clock multiplier. This depends on a patch to include/asm-m68k/m5271.h that defines the multiplier and divider ratios. Removed the definition of CONFIG_SYS_FECI2C. This depends on a patch that removes the use of it in cpu/mcf52x2/cpu_init.c Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
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@ -82,7 +82,10 @@
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#define CONFIG_CMD_MISC
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
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#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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@ -116,7 +119,7 @@
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#define CONFIG_SYS_I2C_OFFSET 0x00000300
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
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#define CONFIG_BOOTFILE "u-boot.bin"
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_RETRY_COUNT 5
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@ -128,16 +131,16 @@
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif /* FEC_ENET */
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#define CONFIG_HOSTNAME M5235EVB
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#define CONFIG_HOSTNAME M5271EVB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"uboot=u-boot.bin\0" \
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"load=tftp $loadaddr $uboot\0" \
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"upd=run load; run prog\0" \
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"prog=prot off ffe00000 ffe2ffff;" \
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"era ffe00000 ffe2ffff;" \
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"cp.b ${loadaddr} 0 ${filesize};" \
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"prog=prot off ffe00000 ffe3ffff;" \
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"era ffe00000 ffe3ffff;" \
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"cp.b $loadaddr ffe00000 $filesize;" \
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"save\0" \
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""
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@ -159,7 +162,17 @@
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#define CONFIG_SYS_MEMTEST_END 0x380000
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#define CONFIG_SYS_HZ 1000000
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/* Clock configuration
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* The external oscillator is a 25.000 MHz
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* CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
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* bus_clk = (cpu_clk/2) (fixed ratio)
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*
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* If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
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* match the new clock speed. Max cpu_clk is 150 MHz.
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*/
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#define CONFIG_SYS_CLK 100000000
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#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
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/*
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* Low Level Configuration Settings
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@ -216,7 +229,14 @@
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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/* Port configuration */
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#define CONFIG_SYS_FECI2C 0xF0
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/* Chip Select 0 : Boot Flash */
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#define CONFIG_SYS_CS0_BASE 0xFFE00000
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#define CONFIG_SYS_CS0_MASK 0x001F0001
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#define CONFIG_SYS_CS0_CTRL 0x00001980
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/* Chip Select 1 : External SRAM */
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#define CONFIG_SYS_CS1_BASE 0x30000000
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#define CONFIG_SYS_CS1_MASK 0x00070001
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#define CONFIG_SYS_CS1_CTRL 0x00001900
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#endif /* _M5271EVB_H */
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