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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

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This commit is contained in:
Wolfgang Denk
2008-04-29 20:06:42 +02:00
parent 3a427fd2ec f4c4d21a88
commit 8466647684
7 changed files with 31 additions and 45 deletions
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5
cpu/ppc4xx/44x_spd_ddr2.c
View File

@@ -40,6 +40,7 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
@@ -237,7 +238,6 @@ static void DQS_calibration_process(void);
static void ppc440sp_sdram_register_dump(void);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
static u32 mfdcr_any(u32 dcr)
{
@@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address,
} else {
/* ECC bit set method for cached memory */
dcbz_area(start_address, num_bytes);
dflush();
/* Write modified dcache lines back to memory */
clean_dcache_range(start_address, start_address + num_bytes);
}
blank_string(strlen(str));

5
cpu/ppc4xx/denali_spd_ddr2.c
View File

@@ -45,6 +45,7 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -92,7 +93,6 @@
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
extern void dcbz_area(u32 start_address, u32 num_bytes);
extern void dflush(void);
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
@@ -1201,7 +1201,8 @@ long int initdram(int board_type)
#else
#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
#endif
dflush();
/* Write modified dcache lines back to memory */
clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
debug("Completed\n");
sync();
remove_tlb(CFG_SDRAM_BASE, dram_size);

10
cpu/ppc4xx/fdt.c
View File

@@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
else
do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
/*

29
cpu/ppc4xx/start.S
View File

@@ -1675,35 +1675,6 @@ trap_reloc:
sync
blr
function_epilog(dcbz_area)
/*----------------------------------------------------------------------------+
| dflush. Assume 32K at vector address is cachable.
+----------------------------------------------------------------------------*/
function_prolog(dflush)
mfmsr r9
rlwinm r8,r9,0,15,13
rlwinm r8,r8,0,17,15
mtmsr r8
mfspr r8,dvlim
addi r3,r0,0x0000
mtspr dvlim,r3
mfspr r3,ivpr
addi r4,r0,1024
mtctr r4
..dflush_loop:
lwz r6,0x0(r3)
addi r3,r3,32
bdnz ..dflush_loop
addi r3,r3,-32
mtctr r4
..ag: dcbf r0,r3
addi r3,r3,-32
bdnz ..ag
mtspr dvlim,r8
sync
mtmsr r9
blr
function_epilog(dflush)
#endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */