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* Vince Husovsky, 7 Nov 2002:

Browse Source 
Add "-n" to linker options to get rid of "Not enough room for
  program headers" problem

* Patch by David Mller, 05 Nov 2002
  Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
  so we can use an already existing name

* Patch by Pierre Aubert, 05 Nov 2002
  Hardware related improvements in FDC boot code

* Patch by Holger Schurig, 5 Nov 2002:
  Make the PXA really change it's frequency

* Patch by Pierre Aubert, 05 Nov 2002
  Add support for slave serial Spartan 2 FPGAs

* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
  drivers
This commit is contained in:
wdenk
2002-11-10 22:06:23 +00:00
parent 2a3cb02076
commit 7f6c2cbc2b
17 changed files with 302 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
cpu/arm920t/speed.c
View File

@@ -42,7 +42,7 @@
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_PLL_INPUT_FREQ should be defined as the input frequency of the PLL.
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
@@ -64,7 +64,7 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
return((CONFIG_PLL_INPUT_FREQ * m) / (p << s));
return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
}
/* return FCLK frequency */

1
cpu/mpc8xx/fec.c
View File

@@ -76,6 +76,7 @@ int fec_initialize(bd_t *bis)
struct eth_device* dev;
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FEC ETHERNET");
dev->iobase = 0;

1
cpu/mpc8xx/scc.c
View File

@@ -75,6 +75,7 @@ int scc_initialize(bd_t *bis)
struct eth_device* dev;
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "SCC ETHERNET");
dev->iobase = 0;

7
cpu/xscale/start.S
View File

@@ -175,10 +175,11 @@ OSTIMER_BASE: .word 0x40a00000
#define OIER 0x1C
/* Clock Manager Registers */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CFG_CPUSPEED
#endif
/* RS: ??? */
.macro CPWAIT
mrc p15,0,r0,c2,c0,0
@@ -194,10 +195,14 @@ cpu_init_crit:
mov r1, #0x00
str r1, [r0, #ICMR]
#ifdef CFG_CPUSPEED
/* set clock speed */
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
mov r0, #3
mcr p14, 0, r0, c6, c0, 0
#endif
/*
* before relocating, we have to setup RAM timing