Merge branch '2021-09-24-arm64-optimized-str-funcs' into next
- Bring in, but disable by default, asm optimized string functions for arm64.
This commit is contained in:
Tom Rini
commit
7d1fcaea12
@ -455,8 +455,8 @@ config ARM_CORTEX_CPU_IS_UP
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config USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy"
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default y
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depends on !ARM64
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default y if !ARM64
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depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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@ -465,7 +465,7 @@ config USE_ARCH_MEMCPY
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config SPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for SPL"
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default y if USE_ARCH_MEMCPY
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depends on !ARM64 && SPL
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depends on SPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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@ -474,16 +474,43 @@ config SPL_USE_ARCH_MEMCPY
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config TPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for TPL"
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default y if USE_ARCH_MEMCPY
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depends on !ARM64 && TPL
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depends on TPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove" if !ARM64
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default USE_ARCH_MEMCPY if ARM64
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depends on ARM64
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
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default SPL_USE_ARCH_MEMCPY if ARM64
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depends on SPL && ARM64
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
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default TPL_USE_ARCH_MEMCPY if ARM64
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depends on TPL && ARM64
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset"
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default y
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depends on !ARM64
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default y if !ARM64
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depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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@ -492,7 +519,7 @@ config USE_ARCH_MEMSET
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config SPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for SPL"
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default y if USE_ARCH_MEMSET
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depends on !ARM64 && SPL
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depends on SPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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@ -501,7 +528,7 @@ config SPL_USE_ARCH_MEMSET
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config TPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for TPL"
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default y if USE_ARCH_MEMSET
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depends on !ARM64 && TPL
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depends on TPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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@ -19,7 +19,11 @@ extern char * strchr(const char * s, int c);
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#endif
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extern void * memcpy(void *, const void *, __kernel_size_t);
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#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE)
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#define __HAVE_ARCH_MEMMOVE
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#else
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#undef __HAVE_ARCH_MEMMOVE
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#endif
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extern void * memmove(void *, const void *, __kernel_size_t);
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#undef __HAVE_ARCH_MEMCHR
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@ -39,8 +39,13 @@ obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
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obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
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obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
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endif
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ifdef CONFIG_ARM64
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o
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else
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
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endif
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obj-$(CONFIG_SEMIHOSTING) += semihosting.o
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obj-y += bdinfo.o
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98
arch/arm/lib/asmdefs.h
Normal file
98
arch/arm/lib/asmdefs.h
Normal file
@ -0,0 +1,98 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Macros for asm code.
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*
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* Copyright (c) 2019, Arm Limited.
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*/
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#ifndef _ASMDEFS_H
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#define _ASMDEFS_H
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#if defined(__aarch64__)
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/* Branch Target Identitication support. */
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#define BTI_C hint 34
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#define BTI_J hint 36
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/* Return address signing support (pac-ret). */
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#define PACIASP hint 25; .cfi_window_save
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#define AUTIASP hint 29; .cfi_window_save
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/* GNU_PROPERTY_AARCH64_* macros from elf.h. */
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#define FEATURE_1_AND 0xc0000000
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#define FEATURE_1_BTI 1
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#define FEATURE_1_PAC 2
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/* Add a NT_GNU_PROPERTY_TYPE_0 note. */
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#define GNU_PROPERTY(type, value) \
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.section .note.gnu.property, "a"; \
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.p2align 3; \
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.word 4; \
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.word 16; \
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.word 5; \
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.asciz "GNU"; \
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.word type; \
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.word 4; \
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.word value; \
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.word 0; \
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.text
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/* If set then the GNU Property Note section will be added to
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mark objects to support BTI and PAC-RET. */
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#ifndef WANT_GNU_PROPERTY
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#define WANT_GNU_PROPERTY 1
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#endif
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#if WANT_GNU_PROPERTY
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/* Add property note with supported features to all asm files. */
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GNU_PROPERTY (FEATURE_1_AND, FEATURE_1_BTI|FEATURE_1_PAC)
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#endif
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#define ENTRY_ALIGN(name, alignment) \
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.global name; \
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.type name,%function; \
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.align alignment; \
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name: \
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.cfi_startproc; \
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BTI_C;
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#else
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#define END_FILE
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#define ENTRY_ALIGN(name, alignment) \
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.global name; \
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.type name,%function; \
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.align alignment; \
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name: \
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.cfi_startproc;
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#endif
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#define ENTRY(name) ENTRY_ALIGN(name, 6)
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#define ENTRY_ALIAS(name) \
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.global name; \
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.type name,%function; \
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name:
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#define END(name) \
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.cfi_endproc; \
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.size name, .-name;
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#define L(l) .L ## l
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#ifdef __ILP32__
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/* Sanitize padding bits of pointer arguments as per aapcs64 */
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#define PTR_ARG(n) mov w##n, w##n
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#else
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#define PTR_ARG(n)
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#endif
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#ifdef __ILP32__
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/* Sanitize padding bits of size arguments as per aapcs64 */
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#define SIZE_ARG(n) mov w##n, w##n
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#else
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#define SIZE_ARG(n)
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#endif
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#endif
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242
arch/arm/lib/memcpy-arm64.S
Normal file
242
arch/arm/lib/memcpy-arm64.S
Normal file
@ -0,0 +1,242 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* memcpy - copy memory area
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*
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* Copyright (c) 2012-2020, Arm Limited.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses.
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*
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*/
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#include "asmdefs.h"
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#define dstin x0
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#define src x1
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#define count x2
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#define dst x3
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#define srcend x4
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#define dstend x5
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#define A_l x6
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#define A_lw w6
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#define A_h x7
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#define B_l x8
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#define B_lw w8
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#define B_h x9
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#define C_l x10
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#define C_lw w10
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#define C_h x11
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#define D_l x12
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#define D_h x13
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#define E_l x14
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#define E_h x15
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#define F_l x16
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#define F_h x17
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#define G_l count
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#define G_h dst
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#define H_l src
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#define H_h srcend
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#define tmp1 x14
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/* This implementation handles overlaps and supports both memcpy and memmove
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from a single entry point. It uses unaligned accesses and branchless
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sequences to keep the code small, simple and improve performance.
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Copies are split into 3 main cases: small copies of up to 32 bytes, medium
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copies of up to 128 bytes, and large copies. The overhead of the overlap
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check is negligible since it is only required for large copies.
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Large copies use a software pipelined loop processing 64 bytes per iteration.
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The destination pointer is 16-byte aligned to minimize unaligned accesses.
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The loop tail is handled by always copying 64 bytes from the end.
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*/
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ENTRY_ALIAS (memmove)
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ENTRY (memcpy)
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PTR_ARG (0)
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PTR_ARG (1)
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SIZE_ARG (2)
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add srcend, src, count
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add dstend, dstin, count
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cmp count, 128
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b.hi L(copy_long)
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cmp count, 32
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b.hi L(copy32_128)
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/* Small copies: 0..32 bytes. */
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cmp count, 16
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b.lo L(copy16)
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ldp A_l, A_h, [src]
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ldp D_l, D_h, [srcend, -16]
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stp A_l, A_h, [dstin]
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stp D_l, D_h, [dstend, -16]
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ret
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/* Copy 8-15 bytes. */
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L(copy16):
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tbz count, 3, L(copy8)
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ldr A_l, [src]
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ldr A_h, [srcend, -8]
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str A_l, [dstin]
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str A_h, [dstend, -8]
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ret
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.p2align 3
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/* Copy 4-7 bytes. */
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L(copy8):
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tbz count, 2, L(copy4)
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ldr A_lw, [src]
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ldr B_lw, [srcend, -4]
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str A_lw, [dstin]
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str B_lw, [dstend, -4]
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ret
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/* Copy 0..3 bytes using a branchless sequence. */
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L(copy4):
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cbz count, L(copy0)
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lsr tmp1, count, 1
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ldrb A_lw, [src]
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ldrb C_lw, [srcend, -1]
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ldrb B_lw, [src, tmp1]
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strb A_lw, [dstin]
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strb B_lw, [dstin, tmp1]
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strb C_lw, [dstend, -1]
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L(copy0):
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ret
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.p2align 4
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/* Medium copies: 33..128 bytes. */
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L(copy32_128):
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ldp A_l, A_h, [src]
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [srcend, -32]
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||||
ldp D_l, D_h, [srcend, -16]
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cmp count, 64
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b.hi L(copy128)
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||||
stp A_l, A_h, [dstin]
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||||
stp B_l, B_h, [dstin, 16]
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||||
stp C_l, C_h, [dstend, -32]
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||||
stp D_l, D_h, [dstend, -16]
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||||
ret
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||||
|
||||
.p2align 4
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||||
/* Copy 65..128 bytes. */
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L(copy128):
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||||
ldp E_l, E_h, [src, 32]
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||||
ldp F_l, F_h, [src, 48]
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||||
cmp count, 96
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b.ls L(copy96)
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||||
ldp G_l, G_h, [srcend, -64]
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||||
ldp H_l, H_h, [srcend, -48]
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||||
stp G_l, G_h, [dstend, -64]
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||||
stp H_l, H_h, [dstend, -48]
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||||
L(copy96):
|
||||
stp A_l, A_h, [dstin]
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||||
stp B_l, B_h, [dstin, 16]
|
||||
stp E_l, E_h, [dstin, 32]
|
||||
stp F_l, F_h, [dstin, 48]
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||||
stp C_l, C_h, [dstend, -32]
|
||||
stp D_l, D_h, [dstend, -16]
|
||||
ret
|
||||
|
||||
.p2align 4
|
||||
/* Copy more than 128 bytes. */
|
||||
L(copy_long):
|
||||
/* Use backwards copy if there is an overlap. */
|
||||
sub tmp1, dstin, src
|
||||
cbz tmp1, L(copy0)
|
||||
cmp tmp1, count
|
||||
b.lo L(copy_long_backwards)
|
||||
|
||||
/* Copy 16 bytes and then align dst to 16-byte alignment. */
|
||||
|
||||
ldp D_l, D_h, [src]
|
||||
and tmp1, dstin, 15
|
||||
bic dst, dstin, 15
|
||||
sub src, src, tmp1
|
||||
add count, count, tmp1 /* Count is now 16 too large. */
|
||||
ldp A_l, A_h, [src, 16]
|
||||
stp D_l, D_h, [dstin]
|
||||
ldp B_l, B_h, [src, 32]
|
||||
ldp C_l, C_h, [src, 48]
|
||||
ldp D_l, D_h, [src, 64]!
|
||||
subs count, count, 128 + 16 /* Test and readjust count. */
|
||||
b.ls L(copy64_from_end)
|
||||
|
||||
L(loop64):
|
||||
stp A_l, A_h, [dst, 16]
|
||||
ldp A_l, A_h, [src, 16]
|
||||
stp B_l, B_h, [dst, 32]
|
||||
ldp B_l, B_h, [src, 32]
|
||||
stp C_l, C_h, [dst, 48]
|
||||
ldp C_l, C_h, [src, 48]
|
||||
stp D_l, D_h, [dst, 64]!
|
||||
ldp D_l, D_h, [src, 64]!
|
||||
subs count, count, 64
|
||||
b.hi L(loop64)
|
||||
|
||||
/* Write the last iteration and copy 64 bytes from the end. */
|
||||
L(copy64_from_end):
|
||||
ldp E_l, E_h, [srcend, -64]
|
||||
stp A_l, A_h, [dst, 16]
|
||||
ldp A_l, A_h, [srcend, -48]
|
||||
stp B_l, B_h, [dst, 32]
|
||||
ldp B_l, B_h, [srcend, -32]
|
||||
stp C_l, C_h, [dst, 48]
|
||||
ldp C_l, C_h, [srcend, -16]
|
||||
stp D_l, D_h, [dst, 64]
|
||||
stp E_l, E_h, [dstend, -64]
|
||||
stp A_l, A_h, [dstend, -48]
|
||||
stp B_l, B_h, [dstend, -32]
|
||||
stp C_l, C_h, [dstend, -16]
|
||||
ret
|
||||
|
||||
.p2align 4
|
||||
|
||||
/* Large backwards copy for overlapping copies.
|
||||
Copy 16 bytes and then align dst to 16-byte alignment. */
|
||||
L(copy_long_backwards):
|
||||
ldp D_l, D_h, [srcend, -16]
|
||||
and tmp1, dstend, 15
|
||||
sub srcend, srcend, tmp1
|
||||
sub count, count, tmp1
|
||||
ldp A_l, A_h, [srcend, -16]
|
||||
stp D_l, D_h, [dstend, -16]
|
||||
ldp B_l, B_h, [srcend, -32]
|
||||
ldp C_l, C_h, [srcend, -48]
|
||||
ldp D_l, D_h, [srcend, -64]!
|
||||
sub dstend, dstend, tmp1
|
||||
subs count, count, 128
|
||||
b.ls L(copy64_from_start)
|
||||
|
||||
L(loop64_backwards):
|
||||
stp A_l, A_h, [dstend, -16]
|
||||
ldp A_l, A_h, [srcend, -16]
|
||||
stp B_l, B_h, [dstend, -32]
|
||||
ldp B_l, B_h, [srcend, -32]
|
||||
stp C_l, C_h, [dstend, -48]
|
||||
ldp C_l, C_h, [srcend, -48]
|
||||
stp D_l, D_h, [dstend, -64]!
|
||||
ldp D_l, D_h, [srcend, -64]!
|
||||
subs count, count, 64
|
||||
b.hi L(loop64_backwards)
|
||||
|
||||
/* Write the last iteration and copy 64 bytes from the start. */
|
||||
L(copy64_from_start):
|
||||
ldp G_l, G_h, [src, 48]
|
||||
stp A_l, A_h, [dstend, -16]
|
||||
ldp A_l, A_h, [src, 32]
|
||||
stp B_l, B_h, [dstend, -32]
|
||||
ldp B_l, B_h, [src, 16]
|
||||
stp C_l, C_h, [dstend, -48]
|
||||
ldp C_l, C_h, [src]
|
||||
stp D_l, D_h, [dstend, -64]
|
||||
stp G_l, G_h, [dstin, 48]
|
||||
stp A_l, A_h, [dstin, 32]
|
||||
stp B_l, B_h, [dstin, 16]
|
||||
stp C_l, C_h, [dstin]
|
||||
ret
|
||||
|
||||
END (memcpy)
|
||||
148
arch/arm/lib/memset-arm64.S
Normal file
148
arch/arm/lib/memset-arm64.S
Normal file
@ -0,0 +1,148 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* memset - fill memory with a constant byte
|
||||
*
|
||||
* Copyright (c) 2012-2021, Arm Limited.
|
||||
*/
|
||||
|
||||
/* Assumptions:
|
||||
*
|
||||
* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/macro.h>
|
||||
#include "asmdefs.h"
|
||||
|
||||
#define dstin x0
|
||||
#define val x1
|
||||
#define valw w1
|
||||
#define count x2
|
||||
#define dst x3
|
||||
#define dstend x4
|
||||
#define zva_val x5
|
||||
|
||||
ENTRY (memset)
|
||||
PTR_ARG (0)
|
||||
SIZE_ARG (2)
|
||||
|
||||
/*
|
||||
* The optimized memset uses the dc opcode, which causes problems
|
||||
* when the cache is disabled. Let's check if the cache is disabled
|
||||
* and use a very simple memset implementation in this case. Otherwise
|
||||
* jump to the optimized version.
|
||||
*/
|
||||
switch_el x6, 3f, 2f, 1f
|
||||
3: mrs x6, sctlr_el3
|
||||
b 0f
|
||||
2: mrs x6, sctlr_el2
|
||||
b 0f
|
||||
1: mrs x6, sctlr_el1
|
||||
0:
|
||||
tst x6, #CR_C
|
||||
bne 9f
|
||||
|
||||
/*
|
||||
* A very "simple" memset implementation without the use of the
|
||||
* dc opcode. Can be run with caches disabled.
|
||||
*/
|
||||
mov x3, #0x0
|
||||
cmp count, x3 /* check for zero length */
|
||||
beq 8f
|
||||
4: strb valw, [dstin, x3]
|
||||
add x3, x3, #0x1
|
||||
cmp count, x3
|
||||
bne 4b
|
||||
8: ret
|
||||
9:
|
||||
|
||||
/* Here the optimized memset version starts */
|
||||
dup v0.16B, valw
|
||||
add dstend, dstin, count
|
||||
|
||||
cmp count, 96
|
||||
b.hi L(set_long)
|
||||
cmp count, 16
|
||||
b.hs L(set_medium)
|
||||
mov val, v0.D[0]
|
||||
|
||||
/* Set 0..15 bytes. */
|
||||
tbz count, 3, 1f
|
||||
str val, [dstin]
|
||||
str val, [dstend, -8]
|
||||
ret
|
||||
.p2align 4
|
||||
1: tbz count, 2, 2f
|
||||
str valw, [dstin]
|
||||
str valw, [dstend, -4]
|
||||
ret
|
||||
2: cbz count, 3f
|
||||
strb valw, [dstin]
|
||||
tbz count, 1, 3f
|
||||
strh valw, [dstend, -2]
|
||||
3: ret
|
||||
|
||||
/* Set 17..96 bytes. */
|
||||
L(set_medium):
|
||||
str q0, [dstin]
|
||||
tbnz count, 6, L(set96)
|
||||
str q0, [dstend, -16]
|
||||
tbz count, 5, 1f
|
||||
str q0, [dstin, 16]
|
||||
str q0, [dstend, -32]
|
||||
1: ret
|
||||
|
||||
.p2align 4
|
||||
/* Set 64..96 bytes. Write 64 bytes from the start and
|
||||
32 bytes from the end. */
|
||||
L(set96):
|
||||
str q0, [dstin, 16]
|
||||
stp q0, q0, [dstin, 32]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
.p2align 4
|
||||
L(set_long):
|
||||
and valw, valw, 255
|
||||
bic dst, dstin, 15
|
||||
str q0, [dstin]
|
||||
cmp count, 160
|
||||
ccmp valw, 0, 0, hs
|
||||
b.ne L(no_zva)
|
||||
|
||||
#ifndef SKIP_ZVA_CHECK
|
||||
mrs zva_val, dczid_el0
|
||||
and zva_val, zva_val, 31
|
||||
cmp zva_val, 4 /* ZVA size is 64 bytes. */
|
||||
b.ne L(no_zva)
|
||||
#endif
|
||||
str q0, [dst, 16]
|
||||
stp q0, q0, [dst, 32]
|
||||
bic dst, dst, 63
|
||||
sub count, dstend, dst /* Count is now 64 too large. */
|
||||
sub count, count, 128 /* Adjust count and bias for loop. */
|
||||
|
||||
.p2align 4
|
||||
L(zva_loop):
|
||||
add dst, dst, 64
|
||||
dc zva, dst
|
||||
subs count, count, 64
|
||||
b.hi L(zva_loop)
|
||||
stp q0, q0, [dstend, -64]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
L(no_zva):
|
||||
sub count, dstend, dst /* Count is 16 too large. */
|
||||
sub dst, dst, 16 /* Dst is biased by -32. */
|
||||
sub count, count, 64 + 16 /* Adjust count and bias for loop. */
|
||||
L(no_zva_loop):
|
||||
stp q0, q0, [dst, 32]
|
||||
stp q0, q0, [dst, 64]!
|
||||
subs count, count, 64
|
||||
b.hi L(no_zva_loop)
|
||||
stp q0, q0, [dstend, -64]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
END (memset)
|
||||
Loading…
Reference in New Issue
Block a user